JPS61294838A - Electrode and wiring of semiconductor device - Google Patents
Electrode and wiring of semiconductor deviceInfo
- Publication number
- JPS61294838A JPS61294838A JP60136027A JP13602785A JPS61294838A JP S61294838 A JPS61294838 A JP S61294838A JP 60136027 A JP60136027 A JP 60136027A JP 13602785 A JP13602785 A JP 13602785A JP S61294838 A JPS61294838 A JP S61294838A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wire
- semiconductor
- electrode
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置の高安定電極、配線に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to highly stable electrodes and wiring for semiconductor devices.
従来、半導体装置の電極・配線でＣｕ添加のＡｌが、例
えば米国特許第３７４３８９４号公報に記載のよウニ、
エレクトロマイグレーション即ち電気移動の問題を回避
するために用いられてきた。Conventionally, Cu-doped Al was used in electrodes and wiring of semiconductor devices, for example, as described in U.S. Pat. No. 3,743,894,
It has been used to avoid electromigration problems.
半導体装置の配線Ｖ′ｉＡｌが一般に用いられるこの装
置を高電流と高温状態の下で作動させるとき、Ａｌ配線
膜げそれを流れる電流により移動せしめられてこの金属
をある区域では盛上けらせ他の区域では空所を形成きせ
る。この空所は十分大きくなるとこの空所が生じた区域
での金属接触の抵抗を十分増大させて抵抗加熱を起こし
接触金属を溶融はせ、それによりこの装置の早期の事故
を起させる可能性がある。When the device is operated under high current and high temperature conditions in which semiconductor device wiring V'iAl is commonly used, the Al wiring film is moved by the current flowing through it, causing the metal to bulge in certain areas. A void is formed in the area. When this void is large enough, it can increase the resistance of the metal contact in the area where it occurs sufficiently to cause resistive heating and melting of the contact metal, thereby potentially causing premature failure of the device. be.
上記米国特許によれば、このエレクトロマイグレーショ
ンの問題を回避するためにＡｌに１〜】０重量幅のＣｕ
を混入する。そのためＣｕ Ａ ｌ ２粒子の細粒構造
を形成してこれがＡｌ粒界と粒界三重点に介在し、Ａｌ
の原子移動を防げエレクトロマイグレーションに対する
装置の寿命を長くすることができる。According to the above US patent, in order to avoid this electromigration problem, Cu with a weight range of 1 to ]0 is added to Al.
Mix in. Therefore, a fine grain structure of Cu Al 2 particles is formed, which is interposed at Al grain boundaries and grain boundary triple points, and Al
This can prolong the life of the device against electromigration.
本発明げＡｌよりも抵抗率の低いＣｕを用いて配線膜を
形成するもので、ＡｌＶＣ比べ電流密度を大きくとるこ
とができる。更ｖｃＣｕの融点ＵＡｌよシも４００Ｃ以
上高いため、エレクトロマイグレーションによる装置の
早期の事故を防ぐことができる。このように配線をＣＬ
Ｉで形成することによって配線膜の幅を小きくすること
ができ半導体基板の実装密度を上げることができる。同
時に工レフトロマイグレーションによる装置の早期破壊
を防止できる。In the present invention, the wiring film is formed using Cu, which has a lower resistivity than Al, and can have a higher current density than AlVC. Furthermore, since the melting point of vcCu is higher than that of UA1 by 400C or more, it is possible to prevent an early failure of the device due to electromigration. Connect the wiring like this to CL
By forming the wiring film using I, the width of the wiring film can be reduced and the packaging density of the semiconductor substrate can be increased. At the same time, it is possible to prevent premature destruction of the device due to left-field migration.
本発明の目的は従来の半導体Ａｌ配線膜に代わす、耐エ
レクトロマイグレーション性に優れたＣｕを用いること
によって、信頼性の高い半導体素子を提供することにあ
る。An object of the present invention is to provide a highly reliable semiconductor element by using Cu, which has excellent electromigration resistance, in place of the conventional semiconductor Al wiring film.
従来、半導体装置の電極・配線には純Ａｌ又はＳｉ入、
ＱＡｌが用いられていた。しかし、純Ａｌ。Conventionally, electrodes and wiring of semiconductor devices contain pure Al or Si,
QAl was used. However, pure Al.
３ｉ人りＡｌｆｌエレクトロマイグレーション耐量が小
ざく、高電流密度の電流を流すと、電極と半導体基体と
のコンタクト抵抗が増大する。あるいぼ、原子移動によ
り配線が断線してしまう等の欠点があった。3i Alfl electromigration resistance is small, and when a current with a high current density is passed, the contact resistance between the electrode and the semiconductor substrate increases. There were drawbacks such as warts and wire breakage due to atomic movement.
またＣｕ人Ｆ）Ａｌ配線は耐エレクトロマイグレー７ヨ
ン性を有しているが、ＣＬＩ添加によりＡｌ配線の比抵
抗が上昇するため、電流を流した際、素子の温度が著し
く上昇し、素子の動作不良の原因となる。またＣｕ入す
Ａｌ配線でけＡｌ基地中にＣｕが分散しているため、エ
ツチングの際１’ｒＡ／ｌ。Furthermore, although Cu and Al interconnects have electromigration resistance, the addition of CLI increases the specific resistance of the Al interconnects, so when current is applied, the temperature of the device increases significantly, causing the device to may cause malfunction. In addition, since Cu is dispersed in the Al base in the Al wiring containing Cu, the etching rate is 1'rA/l.
原子とＣｕ原子とが局部電池として作用し、Ａｌ配線の
パターン精度が悪くなるという欠点がある。There is a drawback that the atoms and Cu atoms act as a local battery and the pattern accuracy of the Al wiring deteriorates.
特に集積密度を高めた素子に於ける配線幅１μｍ以下の
Ｃｕ入シフＡｌ配線げパターニング精度を確保するため
、高度の加工技術を必要とする。In particular, advanced processing technology is required to ensure patterning accuracy for Cu-containing Schiff Al wiring with a wiring width of 1 μm or less in devices with increased integration density.
本発明では、これらの欠点を除去するために、半導体と
のコンタクトをとる電極部分には純ＡｌあるいけＳｉ入
りＡｌを用い、電流が流れる配線部分子／ｃｔｌＣｕを
用いたもので、その目的は高集積、高精度を要求される
半導体装置の高安定電極・配線を実現することにある。In the present invention, in order to eliminate these drawbacks, pure Al or Si-containing Al is used for the electrode part that makes contact with the semiconductor, and the wiring part through which current flows is made of /ctlCu. The aim is to realize highly stable electrodes and wiring for semiconductor devices that require high integration and high precision.
またリードフレームと素子を接続するボンディングワイ
ヤとしてＣｕワイヤを用いることにより、半導体基体上
のＣｕ配線膜のポンディングパッド部分とＣｕワイヤと
を直接接合できる利点がある。更にその際、銅製のリー
ドフレームを用いることにより、半導体基体上の配線膜
、ポンディフグワイヤ、リードフレーム全てを銅で構成
することになり、耐湿信頼性・安定性に非常に優れた半
導体装置を提供するととができる。Further, by using a Cu wire as a bonding wire for connecting a lead frame and an element, there is an advantage that the bonding pad portion of the Cu wiring film on the semiconductor substrate and the Cu wire can be directly bonded. Furthermore, by using a copper lead frame, the wiring film on the semiconductor substrate, the Pondy wire, and the lead frame are all made of copper, resulting in a semiconductor device with excellent moisture resistance and stability. You can do this by providing .
更にＣｕ配線膜の結晶粒を配線幅よりも小さく、結晶性
を半導体基板に対して〔１１１〕又は［ｏＯ）方向に優
先配向させることによシ、耐エレクトロマイグレーショ
ン性をより高めることができる。Further, by making the crystal grains of the Cu wiring film smaller than the wiring width and preferentially oriented the crystallinity in the [111] or [oO) direction with respect to the semiconductor substrate, electromigration resistance can be further improved.
次に、その理由を述べる。３ｉ入りｋｔの電気比抵抗が
３．１μΩαなのに対しＣｕのそれが１．５μΩｍと小
さく、また３ｉ人りＡｌの融点が、６６００以下である
のに対し、 ＣＬＩのそれが１０８３０と高いため、同
一電流密度の通電でげＣｕの方が温度上昇が少なく、軟
化の度合も小さい。更に結晶の辷り面の多少を示す積層
欠陥エネルギは、（１１１）面内でＣｕでは小さく （
４０ｅｒｇ／ｃｒｒ？）、Ａ／、では大きい（２００ｅ
ｒｇｚ２ｍ”）。これはＡｌの辷シ面の密度がＣｕのそ
れの数倍ある事を意味し、ＡｌＯ方が電流を流した時の
エレクトロマイグレーションを起こし易いことを意味し
ている。Next, I will explain the reason. The electrical resistivity of KT containing 3i is 3.1 μΩα, while that of Cu is small at 1.5 μΩm, and the melting point of Al containing 3i is 6600 or less, whereas that of CLI is high at 10830, so it is the same. When the current density is applied to Cu, the temperature rise is smaller and the degree of softening is smaller. Furthermore, the stacking fault energy, which indicates the extent of the sliding plane of the crystal, is small in Cu in the (111) plane (
40erg/crr? ), A/, is large (200e
rgz2m''). This means that the density of the lattice surface of Al is several times that of Cu, and means that AlO is more likely to cause electromigration when a current is passed through it.
一方、Ｃｕ配線ＫＣｕワイヤをボンディングするばかり
でなく、従来のＡｕワイヤあるいはＡｌワイヤによるボ
ンディングを行なうため、半導体基体上のＣｕ配線膜の
ポンディングパッド部にボンディングの安定性にすぐれ
た純Ａｌ又はＮｉ。On the other hand, in order to bond not only the Cu wiring KCu wire but also the conventional Au wire or Al wire, pure Al or Ni, which has excellent bonding stability, is bonded to the bonding pad part of the Cu wiring film on the semiconductor substrate. .
Ｐｄ、Ｐｔのうち少くとも１種以上を添加したＭ層を堆
積させればよい。この方法を用いることにより、従来設
備を生かし、Ｃｕワイヤでボンディングしたのと同等の
高信頼性を有する半導体装置を提供することができる。An M layer doped with at least one of Pd and Pt may be deposited. By using this method, it is possible to make use of conventional equipment and provide a semiconductor device having the same high reliability as bonding with Cu wire.
このようにしてｌ’）：襄した半導体装ｌｔをセラミク
スモールドすることによシ劣悪な環境下でも製品の信頼
性を確保できる。また、セラミクスモールドの替わ、９
Ｋ、エポキシ樹脂を主とする樹脂モールドを行なうこと
によっても外部環境から内部の半導体基板を保護するこ
とができる。In this way, the reliability of the product can be ensured even under harsh environments by ceramic molding the soldered semiconductor device lt. Also, instead of ceramic mold, 9
K. The internal semiconductor substrate can also be protected from the external environment by performing resin molding mainly using epoxy resin.
以下、本発明を実施例によって詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の実施例の構造を示した断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.
図において、１は半導体基板（Ｓｉ基板。In the figure, 1 is a semiconductor substrate (Si substrate).
Ｑａ−Ａｓ基板）、２＃：を不純物（例えばＰ、Ａｓ。Qa-As substrate), 2#: impurities (e.g. P, As.
Ｂ、Ａｌ等）を拡散した拡散層、３け窓明けされた絶縁
物（例えば厚き０．１〜０．５μｍのｓｉｏ、膜乃至Ｐ
ＥＧ膜）、４は純Ａｌ又は３ｉ人少Ａｌ層で形成（例え
ば蒸着、スパッタ、ＣＶＤ法等により厚さ０．１〜０．
５μｍ堆積させ、フォトエツチングによシバターニング
後３５０〜５５０Ｃの熱処理を５〜６０分間施して安定
化する。）された電極であシ、拡散層２とコンタクト５
で接触している。６Ｆ１ｋｔｖｃ比べ電気比抵抗が半分
のＣｕ層で形成（例えば蒸着、スパッタ、ＣＶＤ法等に
よシ厚さ０．５〜２μｍ堆積させ、パターニング後２５
０〜５５０Ｃの熱処理を５〜６０分間施こして安定化す
る。）された配線であり、電極４と接触している。７は
素子表面を保護する保護膜（例えば厚ざ０．５〜２．０
７７ｍの８ｓＯｔ膜乃至ＰＳＧ膜）でポンディングパッ
ド部分８が開口されている。９はＣｕボンディングワイ
ヤでパッド部８にボンディング（熱圧着又は超音波ボン
ディング等による。）される。B, Al, etc.) diffused layer, insulator with 3-hole opening (for example, 0.1 to 0.5 μm thick SIO, film or P)
EG film), 4 is formed of pure Al or 3i thin Al layer (for example, formed by vapor deposition, sputtering, CVD, etc. to a thickness of 0.1-0.
The film is deposited to a thickness of 5 .mu.m, and after photoetching and patterning, it is stabilized by heat treatment at 350 to 550 C for 5 to 60 minutes. ) electrode, diffusion layer 2 and contact 5
I am in contact with. Formed with a Cu layer with half the electrical resistivity compared to 6F1ktvc (for example, deposited with a thickness of 0.5 to 2 μm by evaporation, sputtering, CVD, etc., and after patterning,
Heat treatment at 0-550C for 5-60 minutes is performed to stabilize. ) and is in contact with the electrode 4. 7 is a protective film that protects the element surface (for example, a thickness of 0.5 to 2.0
The bonding pad portion 8 is opened in 77 m of 8sOt film to PSG film. Reference numeral 9 is a Cu bonding wire that is bonded to the pad portion 8 (by thermocompression bonding, ultrasonic bonding, etc.).
このように構成すると、以下に述べるように配線部分を
純Ａｌ又はＳｉ入りＡｌを用いた場合に比べ耐エレクト
ロマイグレーション性が高く、また従来のＡｌ配線膜、
Ａｕボンディングワイヤで構成された樹脂モールド半導
体製品に比べて耐湿信頼性も向上する。With this structure, as described below, the electromigration resistance is higher than when pure Al or Si-containing Al is used for the wiring portion, and the conventional Al wiring film,
Moisture-resistance reliability is also improved compared to resin-molded semiconductor products made of Au bonding wires.
第２図は本発明の詳細な説明するためのグラフであり、
配線材料として、従来のＳｉ入、ＯＡｌを用いた場合と
、本発明のＣｕ配線を用いた場合の高温通電試験におけ
る抵抗値の経時変化を示す。FIG. 2 is a graph for explaining the present invention in detail,
2 shows the change in resistance value over time in a high temperature current conduction test when conventional Si-containing OAl is used as the wiring material and when the Cu wiring of the present invention is used.
図から明らかなようＫＳｉ入りＡｌＶｃ比べＣｕ配線の
方が安定である。As is clear from the figure, Cu wiring is more stable than AlVc containing KSi.
この理由に、Ｓｉ人ｎｈｔの電気比抵抗が３．１μΩの
なのに対しＣｕのそれが１．５μΩ譚と小さく、またＳ
ｉ入フシＡｌ融点が６６０Ｃ以下であるのに対し、Ｃｕ
のそれが１０８３０と高いため、同一電流密度の通電で
はＣｕの方が温度上昇が少なく、軟化の度合も小さいた
めである。The reason for this is that the electrical resistivity of Si nht is 3.1 μΩ, while that of Cu is as small as 1.5 μΩ, and
While the melting point of aluminum containing aluminum is below 660C, Cu
This is because Cu has a higher temperature of 10830, so when the same current density is applied, the temperature rise in Cu is smaller and the degree of softening is smaller.
第３図は樹脂モールドした場合のＣｕ配線、Ｃｕボンデ
ィングワイヤの組合せと、従来のＳｉ入クシＡｌ配線Ａ
ｕボンデイングワイーヤを組合せた場合の加速寿命試験
（２気圧飽和水蒸気中放置試験）の結果を示す。図から
明らかなように従来の方法に比べＣｕ配線Ｃｕワイヤの
組合せの方が耐湿信頼性に優れ、寿命が２〜２．５倍に
なる。Figure 3 shows the combination of Cu wiring and Cu bonding wire when molded with resin, and the conventional Si-filled comb Al wiring A.
The results of an accelerated life test (standing test in 2-atmosphere saturated steam) when U-bonding wires are combined are shown. As is clear from the figure, compared to the conventional method, the combination of Cu wiring and Cu wire has superior moisture resistance and reliability, and has a service life 2 to 2.5 times longer.
この理由に、従来の方法ではＡｌとＡｕを接合させてお
り、その接合部に水分が侵入してくると局部電池を形成
し電気的に卑なＡｌが浴けてしまうのに対し、本発明で
１１ｃｕ配線Ｃｕワイヤの組合せのため局部電池が形成
されず耐食性が向上するものと考えられる。The reason for this is that in the conventional method, Al and Au are bonded, and if moisture enters the bond, a local battery is formed and the electrically base Al is exposed, whereas the present invention It is thought that because of the combination of 11 cu wiring Cu wire, no local battery is formed and corrosion resistance is improved.
以上をまとめると、本発明によれば、エレクトロマイグ
レーションに対する信頼性と耐湿信頼性の２つを同時に
満足できると考えられる。To summarize the above, it is considered that according to the present invention, both reliability against electromigration and reliability against moisture can be simultaneously satisfied.
第４図は本発明のもう一つの実施例の構造を示した断面
図である。図において、前出の図１に於ける同一符号の
ものは同−又は均等部分を示すものとする。この実施例
は、第１図の実施例におけるＣＯ配−のポンディングパ
ッド部分８とＡｕ又はＡ／＝又ｎＣｕワイヤ１１の中間
Ｋ Ｎ ｉ 、 Ｐｄ、 Ｐｔのうち少くとも１種以上
の元素を０．０１〜３係含むＡｌ層１０（例えば厚ｇｏ
、１〜１．０μｍ）を堆積したものである。このＡｌ層
１０は耐食性を有していることが知、られており、ボン
ディングワイヤとＣｕ配線膜間のボンディングの安定性
を損なうのを防止するとともに耐湿信頼性を持たせる役
割をはたす。FIG. 4 is a sectional view showing the structure of another embodiment of the present invention. In the figures, the same reference numerals as in FIG. 1 above indicate the same or equivalent parts. In this embodiment, at least one element among KNi, Pd, and Pt is added between the bonding pad portion 8 of the CO arrangement and the Au or A/=nCu wire 11 in the embodiment of FIG. Al layer 10 (for example, thickness go
, 1 to 1.0 μm). This Al layer 10 is known to have corrosion resistance, and plays the role of preventing deterioration of the stability of the bonding between the bonding wire and the Cu wiring film and providing moisture resistance reliability.
以上説明したように、本発明によれば、エレクトロマイ
グレーション耐性が高く、かつ耐湿信頼性にすぐれた配
線が得られる。As described above, according to the present invention, wiring having high electromigration resistance and excellent moisture resistance reliability can be obtained.
また、耐食性を有するＡｌ−をポンディングパッド上に
設けることによシ、Ａｕ、Ａ／＝、ＣＯ何れのワイヤも
容易にボンディングでき、かつ電極・配線形成後に熱処
理が加わる場合でも、ボンディングの安定性は維持され
、セラミクスモールド又は樹脂モールドを行った際に高
信頼性の半導体素子を作製できる。In addition, by providing corrosion-resistant Al- on the bonding pad, it is possible to easily bond Au, A/=, and CO wires, and the bonding is stable even when heat treatment is applied after electrode/wiring formation. properties are maintained, and a highly reliable semiconductor element can be produced when ceramic molding or resin molding is performed.
次に、ＣＬＩ配線膜の構造について本発明の詳細な説明
する。第５図ばＣｕ配線膜を形成する際に基板温度を変
身、て結晶粒の大きさを配線幅（１μｍ）よりも小さく
していった場合の高温通電試１険における抵抗値の経時
変化を示す。図から明らかなように結晶粒が小さなもの
程安定度が高く、結晶粒が配線幅よりも大きなものでは
寿命が短かい。Next, the structure of the CLI wiring film will be described in detail. Figure 5 shows the change in resistance value over time during a high-temperature current test when the substrate temperature was changed to make the crystal grain size smaller than the wiring width (1 μm) when forming a Cu wiring film. show. As is clear from the figure, the smaller the crystal grain is, the higher the stability is, and the shorter the life is if the crystal grain is larger than the wiring width.
この理由は結晶粒が小さなもの程、粒界拡散が均一に起
こり、配線幅と結晶粒の大きざが同程度になると粒界拡
散の影響で粒界から配線が断線するためだと考えられる
。The reason for this is thought to be that the smaller the crystal grains are, the more uniform the grain boundary diffusion occurs, and when the wiring width and the size of the crystal grains are about the same, the wiring will be disconnected from the grain boundary due to the influence of grain boundary diffusion.
第６図げＣｕ配線膜の結晶性を半導体基板に対して［１
１１１又１（１００）方向に優先配向させた場合（例え
ば、基板ｇｌｆ１５０Ｃ以上でスパッタ法により形成す
る。）と結晶の配向性が無い場合の、高温通電試験にお
ける抵抗値の経時変化を示す。図から明らかなように〔
１１１〕又は（１００）方向に優先配向させたものでに
安定度が高い。Figure 6: The crystallinity of the Cu wiring film is compared to the semiconductor substrate [1].
111 or 1 (100) direction (for example, formed by sputtering on a substrate glf of 150C or higher) and when there is no crystal orientation, the change in resistance value over time in a high temperature current conduction test is shown. As is clear from the figure
111] or (100) direction has high stability.
この理由ｋｌ Ｃｕが面心立方格子であるため、辷り変
形する際の剪断応力最大の辷り系＃’！（１１１）面と
なる。その際、結晶が半導体基板に対して〔１１１〕又
ｆｌ［１００］方向に優先配向していると、（１１１）
面上を移動してくる転位は不動転位の障壁に向かって堆
積し、転位の移動が妨げられることによりＣｕ配線膜が
強化されることになるためと考えられる。The reason for this is that kl Cu has a face-centered cubic lattice, so the sliding system #' has the maximum shear stress during sliding deformation! It becomes a (111) plane. At that time, if the crystal is preferentially oriented in the [111] or fl[100] direction with respect to the semiconductor substrate, (111)
This is thought to be because dislocations moving on the surface accumulate toward the barrier of immobile dislocations, and the Cu wiring film is strengthened by preventing the movement of dislocations.
以上説明したように、本発明による構造のＣｕ配線膜を
用いれば、エレクトロマイグレーション耐性が高い高信
頼性の半導体素子を作製できる。As explained above, by using the Cu wiring film having the structure according to the present invention, a highly reliable semiconductor element with high electromigration resistance can be manufactured.
本発明によれば、耐食性、耐エレクトロマイグレーショ
ン性ともに優れた半導体用配線膜が得られる。その結果
、樹脂モールドあるいけセラミクスモールドの半導体素
子の高密度、微細配線パターンに適用でき、半導体装置
の信頼性の向上を図ることができる。According to the present invention, a semiconductor wiring film having excellent corrosion resistance and electromigration resistance can be obtained. As a result, the present invention can be applied to high-density, fine wiring patterns of resin-molded or ceramic-molded semiconductor elements, and the reliability of semiconductor devices can be improved.
第１図及び第４図はそれぞれ本発明の実施例の構造を示
した断面図、第２図、第５図及び第６図ケ本発明の効果
による耐エレクトロマイグレーション性を示した線図、
第３図は本発明による耐湿性の効果を示したグラフであ
る。
１・・・半導体基板、２・・・拡散層、３・・・絶縁物
、６・・・Ｃｕｅ、７・・・保護膜、８・・・ポンディ
ングパッド、９・・・Ｃｕワイヤ、１１・・・ボンディ
ングワイヤ。1 and 4 are cross-sectional views showing the structure of an embodiment of the present invention, and FIGS. 2, 5, and 6 are diagrams showing electromigration resistance due to the effects of the present invention,
FIG. 3 is a graph showing the effect of moisture resistance according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffusion layer, 3... Insulator, 6... Cue, 7... Protective film, 8... Bonding pad, 9... Cu wire, 11 ...bonding wire.
Claims (1)
Ｓｉ入りＡｌ層を用い、配線膜はそのＡｌ層上に堆積し
たＣｕ層を用いることを特徴とする半導体装置の電極・
配線。1. An electrode for a semiconductor device characterized in that an Al layer or a Si-containing Al layer is used as an electrode for making contact with a semiconductor substrate, and a Cu layer deposited on the Al layer is used as a wiring film.
wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60136027A JPH0624205B2 (en) | 1985-06-24 | 1985-06-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60136027A JPH0624205B2 (en) | 1985-06-24 | 1985-06-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61294838A true JPS61294838A (en) | 1986-12-25 |
| JPH0624205B2 JPH0624205B2 (en) | 1994-03-30 |
Family
ID=15165470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60136027A Expired - Lifetime JPH0624205B2 (en) | 1985-06-24 | 1985-06-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0624205B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03131021A (en) * | 1989-10-16 | 1991-06-04 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Production process of semiconductor device |
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7755192B2 (en) | 2008-03-25 | 2010-07-13 | Tohoku University | Copper interconnection structure, barrier layer including carbon and hydrogen |
| JP2013219385A (en) * | 2013-06-21 | 2013-10-24 | Renesas Electronics Corp | Semiconductor device |
| US8912540B2 (en) | 2008-03-31 | 2014-12-16 | Renesas Electronics Corporations | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4943570A (en) * | 1972-08-29 | 1974-04-24 | ||
| JPS53116089A (en) * | 1977-03-22 | 1978-10-11 | Hitachi Ltd | Wiring constituent body |
| JPS5818345U (en) * | 1981-07-28 | 1983-02-04 | 株式会社日立製作所 | Migration resistant Al wiring |
| JPS59143320A (en) * | 1983-02-04 | 1984-08-16 | Tdk Corp | Formation of patterned conductive layer |
-
1985
- 1985-06-24 JP JP60136027A patent/JPH0624205B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4943570A (en) * | 1972-08-29 | 1974-04-24 | ||
| JPS53116089A (en) * | 1977-03-22 | 1978-10-11 | Hitachi Ltd | Wiring constituent body |
| JPS5818345U (en) * | 1981-07-28 | 1983-02-04 | 株式会社日立製作所 | Migration resistant Al wiring |
| JPS59143320A (en) * | 1983-02-04 | 1984-08-16 | Tdk Corp | Formation of patterned conductive layer |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03131021A (en) * | 1989-10-16 | 1991-06-04 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Production process of semiconductor device |
| US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
| JP4513973B2 (en) * | 1996-12-04 | 2010-07-28 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US7755192B2 (en) | 2008-03-25 | 2010-07-13 | Tohoku University | Copper interconnection structure, barrier layer including carbon and hydrogen |
| US8163649B2 (en) | 2008-03-25 | 2012-04-24 | Advanced Interconnect Materials, Llc | Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure |
| US10566255B2 (en) | 2008-03-31 | 2020-02-18 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
| US8912540B2 (en) | 2008-03-31 | 2014-12-16 | Renesas Electronics Corporations | Semiconductor device |
| US9165845B2 (en) | 2008-03-31 | 2015-10-20 | Renesas Electronics Corporation | Semiconductor device |
| US9646901B2 (en) | 2008-03-31 | 2017-05-09 | Renesas Electronics Corporation | Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area |
| US9911673B2 (en) | 2008-03-31 | 2018-03-06 | Renesas Electronics Corporation | Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area |
| US10134648B2 (en) | 2008-03-31 | 2018-11-20 | Renesas Electronics Corporation | Manufacturing method of semiconductor device |
| JP2013219385A (en) * | 2013-06-21 | 2013-10-24 | Renesas Electronics Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0624205B2 (en) | 1994-03-30 |
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