JPS5925238A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5925238A
JPS5925238A JP57135407A JP13540782A JPS5925238A JP S5925238 A JPS5925238 A JP S5925238A JP 57135407 A JP57135407 A JP 57135407A JP 13540782 A JP13540782 A JP 13540782A JP S5925238 A JPS5925238 A JP S5925238A
Authority
JP
Japan
Prior art keywords
bonding
pad
pads
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57135407A
Other languages
Japanese (ja)
Inventor
Hirohisa Abe
阿部　洋久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57135407A priority Critical patent/JPS5925238A/en
Publication of JPS5925238A publication Critical patent/JPS5925238A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the occupying areas of electrode wirings, and to improve the degree of integration by shortening the length of adjacent electrode wirings alternately so that bonding pads on every other electrode wiring are positioned in opposite arrangement in the side sections. CONSTITUTION:The electrode wirings 23, 23', the length of wiring sections thereof is shortened alternately so that adjacently positioned bonding pads 22, 22' are not mutually brought into contact, are formed. A lead pattern 25 is formed while pad sections 24, 24' are opposed to the pads 22, 22'. Accordingly, a bonding wire 26 is stretched between the pad 22 and the pad section 24 of a short opposite distance l1 through ultrasonic bonding, and sealed with a sealing body 27, and a bonding wire 28 can be stretched similarly between the pad 22' and the pad section 24' of a long opposing distance l2.

Description

【発明の詳細な説明】 〔発明の１′ξ術分野〕 本発明ｆ、ｚｔ半導体装置に関する。[Detailed description of the invention] [1'ξ technical field of invention] The present invention relates to semiconductor devices f and zt.

〔発明の技術的背景〕[Technical background of the invention]

半導体チップと夕（部リードとを′ｎｔ夙的に接続する
手段として、通常、７ビンデイング線が使用されている
。而しで、半導体装１べには、２本以上のリードが必要
であるが、そのうち１本は、半導体チップの裏面電極を
共晶マウント、導電性樹脂によるマウント等により基板
に装着することにより、その電気的接続が達成されてい
る。Normally, seven binding wires are used as a means to connect the semiconductor chip and the external leads.Therefore, one semiconductor device requires two or more leads. However, in one of these, electrical connection is achieved by mounting the back electrode of the semiconductor chip on the substrate using a eutectic mount, a mount made of conductive resin, or the like.

他の１本は、半導体チップの主面側に前述の一ソンディ
ング純の架設処理を施すことにより電気的接続が達成さ
れている。ボンディング線としては、通常、Ａｕ、Ａｌ
或はこれらに微爪の不純物を添加したものを使用してい
る。ボンディング処理に（弓２、熱圧着法や超音波法等
が採用されている。第１図は、ボンディング線１が架設
された従来の半導体チップの要部全庁し７ている。図中
３は、基板４上に共晶マウントにより装着された半導体
チップ３である。半導体チップ３上には、先端部に？ン
ディングノ？ッド５を有する電極配線６が複数本形成さ
れている。基板４上には、ポンディングパッド５にパッ
ド部７を対向するようにしてリードノやターフ８が形成
されている。ボンディング線１は、ポンディングパッド
５とパッド部７間に架設されている。ボンディング糾ｊ
ノの径は、約３０μｍ程である・〔背景技術の問題点〕 第１図に示ずような構造の半導体装置スでは、１１ｒ、
極配線６及びリード・Ｑターン８の間隔は約６０／Ｌｍ
であり、１チップ当りの集積ＩＷが増すどこの１１？、
極配線６等の間隔を小さくシ５．なりればならない。し
、かじながら、電極Ｍｉ＋、　＋悴６の間隔を６０　／
１１１１す、下に小さくすると、架設し７たボンディン
グ線１の相互間で接触不甑がイｌｊ　／：Ｌ　Ｌ　、不
良製品となる。寸た、ボンブイノブ処理不−行うγ１？
ンディングギャビラリーの径（＋ｔ　、ｉｉ’Ｑ常１　
（ｌ　［Ｊ　７．ｉｍ　ＪＪ。The other one is electrically connected by performing the above-mentioned single-sonding installation process on the main surface side of the semiconductor chip. Bonding wires are usually made of Au or Al.
Alternatively, these are used to which fine nail impurities are added. For the bonding process, thermocompression bonding, ultrasonic bonding, etc. are used. Figure 1 shows all the main parts of a conventional semiconductor chip on which bonding wires 1 are installed. 3 in the figure. 1 is a semiconductor chip 3 mounted on a substrate 4 by a eutectic mount.A plurality of electrode wirings 6 having a terminal node 5 at the tip are formed on the semiconductor chip 3.A substrate A lead wire or turf 8 is formed on the bonding pad 4 so that the pad portion 7 faces the bonding pad 5.The bonding wire 1 is installed between the bonding pad 5 and the pad portion 7.Bonding Detention
The diameter of the 11r,
The spacing between the pole wiring 6 and lead/Q turn 8 is approximately 60/Lm.
And which 11 increases the integrated IW per chip? ,
5. Reduce the spacing between the pole wiring 6, etc. Must be. While nudging, adjust the distance between electrodes Mi+ and +6 by 60/
If 1111 is made smaller downward, there will be no contact between the seven bonding wires 1 installed, resulting in a defective product. Is it true that γ1 is not treated with Bonbuinobob?
Diameter of the landing gear (+t, ii'Q always 1
(l [J 7.im JJ.

−１であ石ため、ボンディング処１甲が］枦めて困難Ｖ
′Ｃな２）欠点があった。-1 stone, bonding place 1A] Difficult V
'C2) There was a drawback.

〔発明の１−１的ｊ 本発明ｔ；ｊ　、ボンディング線による接触不良の発生
を［υｊ　１ｔ＝、　Ｌ、しかも高密度化を達成した半
導体装１バを提供することをその［ｉｍとするものであ
る。[Purpose 1-1 of the invention j The present invention t;j is to prevent the occurrence of contact failure due to bonding wires [υj 1t=, L, and to provide a semiconductor device 1 which has achieved high density. It is something.

〔発明の＋＋！１．要〕 不発明は、＋１４ンデイング・セット金イイする電極配
線の長さを一つ置きに短くして、一つ（（（１、きに隣
接するボンディングノヤツドがその側［３で対向する配
置としたことにより、電極配線の占有面積を小さくして
集積度を向上させ、かつ、ボンデ、イング線の接触不良
の発生を防止した半導体装Ｗｉである。[Invention ++! 1. [Required] The non-invention is to shorten the length of the electrode wiring for +14 bonding set gold every other wire, and to arrange the adjacent bonding wires on that side [3]. As a result, the semiconductor device Wi is capable of reducing the area occupied by the electrode wiring, improving the degree of integration, and preventing the occurrence of poor contact between bonding and bonding wires.

〔発明の実麿１ｆｌｌ） 以下、本発明の実施例について図面を参照して説明する
。第２図は、本発明の一実施例の要部を示す斜視図であ
る。図中２０は、基板２１上に装λ゛ｆされた半導体チ
ップである。半導体チップ２０ＫｉＩ′Ｊ、、例えヒｌ
：次のような構成からなる所謂発光ダイオードプレイが
形成されている。[Practice of the Invention] Examples of the present invention will be described below with reference to the drawings. FIG. 2 is a perspective view showing essential parts of an embodiment of the present invention. In the figure, reference numeral 20 denotes a semiconductor chip mounted on a substrate 21. As shown in FIG. Semiconductor chip 20KiI'J, for example Hill
: A so-called light emitting diode play is formed having the following configuration.

ｎ型ＧａＡｓ　Ｋ　ｎ型ＧａＡｌ！、　−ｘｐｘ層を気
相成長にて形成（７、これにＺｎの選択拡散全施し微小
発光部を形成する。この発光部以外のＧａＡｇｌＸＰＸ
層」二には、厚き約２０００Ｘの５１３Ｎ４からなる選
択波１ｉ（！膜を形成し、裏面側のＧａＡｓ基板面には
、ＡｕＳ　１層を形成する。ＧａＡ１１ｌ−ｘＰｘ層上
には、アルミニウム層を形成し、第２図に示す如くパタ
ーニングを施し、４５０　Ｔ：で」０分間Ｎ２雰囲気中
で熱処理に施ｉ−てオーミック接触を得ろ。つまり、先
端部に例えば８０　Ｘ　８０μ、ｎで、１！ンｊ゛イン
グツやラド２２　、２２’不・イコすると共に、−９１
６，きに隣接（１，たポンプイングツ・？ッ１°２２　
、２２’間の間隔Ｌ’、ｃ）　８　（１／４＋＋１とし
、ｌ！：’ｉに位置するポンディングパッド２２　、２
２’同志が接触しないように配線部分の長さ全一つｌｉ
／ｉきに短くした電極配線２３゜２３′ヲ形成している
。一方、基板２１上には、パッド部２４　、２４’を半
導体グー、プ２０上のポンディングパッド２２　、２２
’に交１向１−るようにしてリー　トノＳクー７２５が
形成さ）１．ている。リード・ヤターン２．夕は、配線
部分の長さの長い電］「′ｉ配糾１２３のポンディング
パッド２２とこれに対向する・Ｐ、、ビ郡２４間の間隔
２．を、配線部分の長さのＬ）、Ｘｊい雷、１（Ｉｉ配
線２３のボンディング／ｆ　ツ＋ｐ　２２’とこ、１］
に対向するパッドｆｔ１（２４間の間隔ｔ、２シりも短
く、設定している。n-type GaAs K n-type GaAl! , -xpx layer is formed by vapor phase growth (7, Zn is fully selectively diffused to form a minute light emitting part. GaAglXPX other than this light emitting part)
On layer 2, a selective wave 1i (! film) made of 513N4 with a thickness of about 2000X is formed, and on the GaAs substrate on the back side, one layer of AuS is formed.On the GaA11l-xPx layer, an aluminum layer is formed. 2, and then heat-treated at 450 T for 0 minutes in an N2 atmosphere to obtain ohmic contact. That is, for example, 80 x 80 μ, n, 1 !nj゛ingtsu and Rad 22, 22'Fu・Eco, -91
6, Adjacent to (1, Ta pumpings? 1°22
, 22' spacing L', c) 8 (1/4++1, l!:' i)
2' The entire length of the wiring part is 1 li so that the comrades do not touch each other.
/i shortened electrode wiring 23°23' is formed. On the other hand, pad portions 24 and 24' are formed on the substrate 21, and bonding pads 22 and 22' on the substrate 20 are formed of semiconductor pads 24 and 24'.
1. ing. Reed Yataan 2. The length of the wiring part is L). ,
The spacing t between the pads ft1 (24) facing the pads is set to be 2 degrees shorter.

このように構成された半導体装置−１！巧、によれげ、
第３図に示す如く、例えＵ、１″対向間隔ｔｌの煙いポ
ンディングパツド２２とパｙ　ｌ’部２４間に超箸波ボ
ンディングによりボンディング線２６イ：架設する。次
いで、このボンディング線２６、ｓｒンディングノやラ
ド２２、ノモッ１″部２４をシリコン樹脂からなる封止
体２７で封止した後、対向間隔ｔ２の長いボンディング
・々ラド２２′とパッド部２４′間に同様にしてボンデ
ィングｍ２８の架設を施すことができる。このようにポ
ンディングパッド２２　、２２’と）Ｆノド部２４　、
２４’（田の間隔ｔｌ＋　Ａ２　ｔＪ、　ｅｕｉ　＃７
２すものごとに長短に設定されており、しかも、一方の
ポンプイングツぐラド２２と）臂ッド丁１１Ｘ２４間に
ボンディング線２６ン：架設して領１脂封止した後に、
残る＋Ｉ？ンディングパッ１°２２′とパッド部２４′
間にボンディング線２８不二架設することができるので
、ボンディング線２６．２８の接触による不良品の発生
を回避することができる。しかも、半導体チップ２０上
のポンディングパッド２２゜２２′の位置が隣接するも
の同志で交互にずノｔでいるので、同一面積の半導体チ
ップ２０−ヒに形成できろ電極配線２．９　、２．９’
の噌を多くして、高密ｒＴ化不ｆ達成することができる
。Semiconductor device configured in this way-1! Takumi, Yorege,
As shown in FIG. 3, a bonding line 26 is constructed by super-wave bonding between the bonding pad 22 and the pin 24 with an opposing spacing of 1'' tl. , sr pad 22 and pad 1'' portion 24 are sealed with a sealing body 27 made of silicone resin, and then bonding is performed in the same manner between the bonding pad 22' and the pad portion 24' with a long facing distance t2. m28 construction can be carried out. In this way, the bonding pads 22, 22' and the F throat part 24,
24' (field spacing tl + A2 tJ, eui #7
The lengths are set for each of the two parts, and after installing the bonding wire 26 between the pumping rod 22 on one side and the armpit 11x24 and sealing the area 1,
Remain +I? Landing pad 1°22' and pad part 24'
Since the bonding wires 28 can be installed in between, it is possible to avoid the occurrence of defective products due to contact between the bonding wires 26 and 28. Furthermore, since the positions of the bonding pads 22 and 22' on the semiconductor chip 20 are alternately arranged between adjacent pads, the electrode wirings 2.9 and 2 can be formed on the semiconductor chip 20 with the same area. .9'
It is possible to achieve high-density rT by increasing the amount of irradiation.

尚、′）：施ｆ・１１でＱ１０、半ｉｊＪ体イｌ／ット
２０上のポンプ゛イングをッ１°２２　、２２’の西Ｉ
：、　ｌｉイをずらし、と７１．にマ・［応してリード
パターン２５のパラ＋裔ａｌ１２４　、２４’の配置も
同様にずらぜたものについてｈ（）、明したが、この他
にも、ポンディングパッド２２　、２２’の配ｆｌ”を
ずらせて高密度化を図り、こノ１に合ｄ、）せてり−）
゛パターン２５の・ｐ７ド）Ｘｌ（の配置を適宜設定す
ると共に、対向間（’ｆＡの異なるボンディング・ギソ
ドと・９ノド部間にポンプ′イング線を架ｎ＆してこれ
を％、ｌ脂封！１した後に、残イ）ボンディング・ζノ
ｌ°どバッド部間にボンディング線を架設−４にと（（
より、ｙＷ７デイング線に、しる接触不良丘回避しグξ
ものでろ〕］は、］リー１５やターフ２５の形状は如何
なるものてｔｔ′）っても良い。In addition, '): At the application f 11, Q10, the pumping on half ij
:, shift li, and 71. [Accordingly, the arrangement of the pads 124 and 24' of the lead pattern 25 was also shifted in the same way. fl'' was shifted to achieve higher density, and this was combined with d,)seteri-)
In addition to appropriately setting the arrangement of ``pattern 25's p7 do'' After sealing! 1), install the bonding wire between the bonding and ζ l° pad parts and proceed to (((
Therefore, to avoid the poor contact hill on the yW7 marking line,
The shape of the lee 15 and the turf 25 may be any shape.

才た、実、ｌｌｆｌｊ例でｔ、１、発光ダイオードアレ
イが形成さノまた半・、９体チップ２０に本発明を適用
したものについて説明したが、この他にも受光素子プレ
イ、ｆ（・債回路、薄膜回路等の形成された半導体チッ
プにも適用できることに勿論である。As an example, the present invention has been applied to a chip 20 with a light-emitting diode array formed on it, and a light-emitting diode array formed thereon. Of course, the present invention can also be applied to semiconductor chips formed with bonded circuits, thin film circuits, etc.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係る半導体装置の製造方法
によれば、Ｈ？ンディング線による接触不良の発生を防
止し、しかも面密度化を達成できる等顕著な効果を奏す
るものである。As explained above, according to the method for manufacturing a semiconductor device according to the present invention, H? This has remarkable effects such as preventing poor contact due to the binding wires and achieving increased surface density.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、従来の半導体装置の要部を示す斜視図、第２
図は、本発明の一実施例の要部を示す斜視図、第３図は
、同実施例の半導体装１６のボンディング線の架設状態
を示す断面図である。 ２０・・・半２ｎ体チップ、２１・・・基板、２２゜２
２′・・・ポンディングパッド、２３．２３′・・・１
１デ極配糺）、２４　、　２４’・・・パラ　ド部、２
５・・・リードパターン、２６．２８・・・７ビンデイ
ング線１．Ｊ　Ｏ−・・半導体装置。Figure 1 is a perspective view showing the main parts of a conventional semiconductor device;
FIG. 3 is a perspective view showing a main part of an embodiment of the present invention, and FIG. 3 is a sectional view showing a state in which bonding wires are installed in a semiconductor device 16 of the same embodiment. 20...Semi-2n body chip, 21...Substrate, 22゜2
2'...ponding pad, 23.23'...1
1 depolar arrangement), 24, 24'...parad part, 2
5... Lead pattern, 26.28...7 binding line 1. J O-...Semiconductor device.

Claims (1)

【特許請求の範囲】[Claims] ポンディングパッドを有する電極配線の？、１７　Ｆ、
ｆｆ本を所足間隔で並列して形成した半導体グ°ツブと
、該ヂッゾを装着し、た基板と、前記？ンデ（ング・や
ラドにパラ）°部全対向して前記基板上に形成さノ］７
たリード・ｐターンとを有する半導体装置に〕Ｙ・・い
て、少なくとも一つ置きのｆｌｕ極配線のビンディング
・Ｐ７ドがその側部で対向する配置になるようにｌ’ｒ
’ｒ　＋＞“２する゛ｔＩＬ極配線の−ｐさ全一つｌｉ
ｄきに短くしたことを特徴とする半導体装置。Of electrode wiring with bonding pads? , 17F,
A semiconductor block formed by arranging ff pieces in parallel at required intervals, a substrate to which the dizzies are attached, and the above-mentioned? 7. Formed on the substrate so that all the parts facing each other are opposite to each other]7
[In a semiconductor device having leads and p-turns] Y..., the bindings of at least every other flu pole wiring and P7 are arranged so that they face each other on their sides.
'r +>"2゛tIL pole wiring -p all one li
A semiconductor device characterized by being shortened to d.
JP57135407A 1982-08-03 1982-08-03 Semiconductor device Pending JPS5925238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57135407A JPS5925238A (en) 1982-08-03 1982-08-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57135407A JPS5925238A (en) 1982-08-03 1982-08-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5925238A true JPS5925238A (en) 1984-02-09

Family

ID=15150999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57135407A Pending JPS5925238A (en) 1982-08-03 1982-08-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5925238A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185833A (en) * 1984-10-03 1986-05-01 Toshiba Corp Wire-bonding
JPH0256942A (en) * 1988-08-23 1990-02-26 Fuji Xerox Co Ltd Semiconductor device
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185833A (en) * 1984-10-03 1986-05-01 Toshiba Corp Wire-bonding
JPH0564460B2 (en) * 1984-10-03 1993-09-14 Tokyo Shibaura Electric Co
JPH0256942A (en) * 1988-08-23 1990-02-26 Fuji Xerox Co Ltd Semiconductor device
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology

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