JPS6185833A - Wire-bonding - Google Patents

Wire-bonding

Info

Publication number
JPS6185833A
JPS6185833A JP59207784A JP20778484A JPS6185833A JP S6185833 A JPS6185833 A JP S6185833A JP 59207784 A JP59207784 A JP 59207784A JP 20778484 A JP20778484 A JP 20778484A JP S6185833 A JPS6185833 A JP S6185833A
Authority
JP
Japan
Prior art keywords
lead bonding
bonding pads
inner lead
bonding
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59207784A
Other languages
Japanese (ja)
Other versions
JPH0564460B2 (en
Inventor
Yoshitaka Fukuoka
義孝 福岡
Emiko Matsumoto
恵美子 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59207784A priority Critical patent/JPS6185833A/en
Publication of JPS6185833A publication Critical patent/JPS6185833A/en
Publication of JPH0564460B2 publication Critical patent/JPH0564460B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To contrive to improve the yield of bonding work by a method wherein the inner lead bonding pads and the outer lead bonding pads, which correspond to the inner lead bonding pads, are respectively connected sequentially holding the mutually opposed inner lead bonding pad and outer lead bonding pad between them, and after that, the remaining inner lead and outer lead bonding pads are connected in order with each other. CONSTITUTION:Plural inner lead bonding pads 1 arrayed on a semiconductor chip 3 in a zigzagged form and plural outer lead bonding pads 2 arrayed on a circuit substrate 5 in a zigzagged form in opposition to the inner lead bonding pads 1 are connected using bonding wires 4 in every other pair of the mutually opposed inner lead bonding pad 1 and outer lead bonding pad 2. Then, the remaining inner lead and outer lead bonding pads 1 and 2, which are respectively located between each inner lead bonding pad 1 being already connected and each outer lead bonding pad 2 being already connected, are connected in order using the bonding wires 4 in the same manner. When such crook as sagging is generated on one of the bonding wires 4, there is no possibility that a short-circuit trouble occurs between the bonding wire 4 and its adjacent bonding wire 4 if the correction is immediately carried out.

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は、回路基板上にダイボンドされた半導体チップ
のインナーリードボンディングパッドと同じ回路基板上
に設けられたアウターリードボンディングパッドとをボ
ンディングワイヤにより電気的に接続する方法に関する
。Detailed Description of the Invention [Technical Field of the Invention] The present invention provides electrical connection between inner lead bonding pads of a semiconductor chip die-bonded on a circuit board and outer lead bonding pads provided on the same circuit board using a bonding wire. related to how to connect.

［発明の技術的背景］ 近年、ＩＣモジュールにおいては、ゲートが高密度化さ
れる傾向にあり、これに伴って以下に示すレントの法則
により、ビン数が増加しボンデライングバッドの間隔も
狭くなってきている。[Technical Background of the Invention] In recent years, there has been a trend toward higher density gates in IC modules, and as a result, the number of bins has increased and the gap between bonder ring pads has become narrower due to Lent's law shown below. It has become to.

くレントの法則〉 Ｐ＝ＫＧ’ 但し　Ｋ：定数 ｒ：レントの常数 Ｇ：ゲート数 Ｐ：ビン数 このため、半導体チップのインナーリードボンディング
パッドと回路基板上のアウターリードボンディングパッ
ドとを直線的に配列した従来のモジュールに代り、最近
は第３図に示すように、インナーリードボンディングパ
ッド１およびアウターリードボンディングパッド２をい
ずれも千鳥状に配列することにより、隣接するボンディ
ングパッドの配列ピッチを狭めたり、半導体チップ３の
面積を増大させたすせずにビン数を増加させるようにし
たものが開発されている。Rent's law〉 P=KG' where K: constant r: constant of rent G: number of gates P: number of bins Therefore, the inner lead bonding pad of the semiconductor chip and the outer lead bonding pad on the circuit board can be connected in a straight line. Instead of the conventional arrayed modules, recently, as shown in FIG. 3, inner lead bonding pads 1 and outer lead bonding pads 2 are both arranged in a staggered manner, thereby narrowing the arrangement pitch of adjacent bonding pads. A device has been developed in which the number of bins is increased without increasing the area of the semiconductor chip 3.

しかして、これらのインナーリードボンディングパッド
１と、対応するアウターリードボンディングパッド２と
を、それぞれボンディングワイヤ４を用いて電気的に接
続するには、従来のモジュールにおけると同様に、配列
順通り接続していく方法がとられていた。Therefore, in order to electrically connect these inner lead bonding pads 1 and the corresponding outer lead bonding pads 2 using bonding wires 4, they must be connected in the order in which they are arranged, as in the conventional module. A method was taken to

なお第３図にＪ５いて、符号５は回路間（ｋを示してお
り、ボンディングワイヤ４の横に記載された■、■、■
・・・の連続番号はボンディング順序を示している。In addition, in FIG. 3, J5 indicates the bonding wire 4, and the code 5 indicates the circuit between the circuits (k).
The consecutive numbers . . . indicate the bonding order.

［背碩技術の問題点］ しかしながら、口のような従来のボンディング方法にお
いては、隣接するボンディングワイヤ４間の間隔が狭い
ため、不良事故が起こり易いという問題があった。[Problems with backsliding technology] However, in the conventional bonding method such as the bonding method, there is a problem that failures and accidents are likely to occur because the distance between adjacent bonding wires 4 is narrow.

すなわち、ボンディングワイヤ４の湾曲が生じた場合に
これと隣接するボンディングワイヤ４との間に短絡事故
を生じ易く、またボンディングの際にすでに接続された
隣りのボンディングワイヤ４のボンディング点にキャピ
ラリーの先端が接触して断線等を生じ易く、製品の歩留
りが低下するばかりでなく信頼性の高いボンディングを
行なうことができないという問題があった。In other words, when the bonding wire 4 is bent, a short circuit is likely to occur between it and the adjacent bonding wire 4, and the tip of the capillary is likely to contact the bonding point of the adjacent bonding wire 4 that has already been connected during bonding. There was a problem that not only did the yield of the product decrease, but also that highly reliable bonding could not be performed.

［発明の目的］ 本発明はこれらの問題を解決するためになされたもので
、接続作業が容易で、修正がし易く、ボンゲインクワイ
ヤ間のショートや断線等の不良事故が起こることが少な
いワイヤボンディング方法を提供する口とを目的とする
。[Object of the Invention] The present invention was made to solve these problems, and provides a wire that is easy to connect, easy to repair, and less prone to defective accidents such as short circuits and disconnections between bond wires. The purpose is to provide a bonding method.

［発明の概要］ りなわら本発明のワイヤボンディング方法は、回路基板
上にダイボンドされた半導体チップ上に千鳥状に配列さ
れた複数のインナーリードボンディングパッドと、前記
回路基板上にこれらのインナーリードボンディングパッ
ドと対向して千鳥状に設けられた複数のアウターリード
ボンディングパッドとを、ボンディングワイヤによりそ
れぞれ電気的に接続するにあたり、１つ以上のボンディ
ングパッドを隔ててインナーリードボンディングパッド
とこれに対応するアウターリードボンディングパッドと
を順に接続した後、接続された各ボンディングパッド間
に位置するインナーリードボンディングパッドとアウタ
ーリードボンディングパッドとを順に゛１気的に接続す
ることを順に接続している。[Summary of the Invention] The wire bonding method of the present invention includes a plurality of inner lead bonding pads arranged in a staggered manner on a semiconductor chip die-bonded on a circuit board, and these inner lead bonding pads on the circuit board. When electrically connecting the pads and a plurality of outer lead bonding pads provided in a staggered manner facing each other using bonding wires, one or more bonding pads are separated between the inner lead bonding pads and the corresponding outer lead bonding pads. After sequentially connecting the lead bonding pads, the inner lead bonding pads and the outer lead bonding pads located between the connected bonding pads are sequentially connected in order.

［発明の実施例１ 以下本発明の実施例を図面に基づいて説明する。[Embodiment 1 of the invention Embodiments of the present invention will be described below based on the drawings.

なお以下の図面においては、第３図と同じ部分には同一
符号を付し、またボンディング類を丸で囲んだ連続番号
で示している。In the following drawings, the same parts as in FIG. 3 are designated by the same reference numerals, and bondings are indicated by serial numbers in circles.

この実施例においては、まず第１図（ａ　＞に示すよう
に、回路基板５上にダイボンドされた半導体チップ３上
に千鳥状に配列された複数のインナーリードボンディン
グパッド１と、回路基板５．トの、これらのインナーリ
ードボンディングパッド１に対向して千鳥状に配設され
た複数のアウターリードボンディングパッド２とを１つ
おきにボンディングワイヤ４で接続した後、同図（ｂ　
）に示すように、接続された各ボンディングパッド間に
位置するインナーリードボンディングパッド１とアウタ
ーリードボンディングパッド２とを順に１ν続してボン
ディング作業が行なわれる。In this embodiment, first, as shown in FIG. 1(a), a plurality of inner lead bonding pads 1 are arranged in a staggered manner on a semiconductor chip 3 die-bonded on a circuit board 5, and a plurality of inner lead bonding pads 1 are arranged in a staggered manner on a semiconductor chip 3 die-bonded on a circuit board 5. After connecting every other outer lead bonding pad 2 facing the inner lead bonding pads 1 with bonding wires 4, as shown in FIG.
), a bonding operation is performed by successively connecting inner lead bonding pads 1 and outer lead bonding pads 2 located between the connected bonding pads for 1v.

この実施例によれば、例えばボンディングワイヤ４にた
るみ等の湾曲が生じた場合、直ちに昨正を行なえば隣接
するボンディングワイヤ４との間に短絡事故を起こすこ
とがない。According to this embodiment, for example, if the bonding wire 4 becomes bent such as slack, if the wire is corrected immediately, a short circuit between the bonding wires 4 and the adjacent bonding wires 4 will not occur.

また、最初の１つＪ５ぎのボンディングの際には、ボン
ディングワイヤ相互の間隔が広いのでワイレ形状の躇１
を容易に行なうことができる利点がある。In addition, when bonding the first J5 wire, the distance between the bonding wires is wide, so there is a wire-shaped
It has the advantage of being easy to carry out.

次に本発明の別の実施例を第２図を参照して説明する。Next, another embodiment of the present invention will be described with reference to FIG.

この実施例においては、第２図に示すように、まず１つ
おきに配列された半導体チップ３からの距離が近い方の
アウターリードボンディングパッド２とごれと対応する
インナーリードボンディングパッド１とを順に接続した
後、次に残りのインナーリードボンディングパッド１と
これに対応する半導体デツプ３からの距離が遠い方のア
ウターリードボンディングパッド２とを順に接続する。In this embodiment, as shown in FIG. 2, first, the outer lead bonding pads 2 that are closer to each other and the inner lead bonding pads 1 that are closer to the semiconductor chips 3 that are arranged every other place are After the connections are made in order, the remaining inner lead bonding pads 1 and the corresponding outer lead bonding pads 2 that are farther from the semiconductor depth 3 are connected in order.

この実施例においては、ボンディングの行ないガいアウ
ターリードボンディングパッド２へのボンディングワイ
ヤ４の接続を広いスペースで行なうことになるので、ボ
ンディング作業が容易であるばかりでなく、不良事故の
発生時の修正も容易に行なうことができる。In this embodiment, since the bonding wire 4 is connected to the outer lead bonding pad 2 in a large space during bonding, the bonding work is not only easy but also easy to correct when a defective accident occurs. can also be easily done.

［発明の効果１ 以上の記載から明らかなように本発明によれば、ボンデ
ィングワイヤ断線やショート等の不良事故が起こり難く
、ボンディング作業の歩留りが向上し、製品に対する信
頼性向上する。[Effect of the Invention 1] As is clear from the above description, according to the present invention, defects such as bonding wire breakage and short circuits are less likely to occur, the yield of bonding work is improved, and the reliability of the product is improved.

なお本発明の方法は、自動ボンディング機械による作業
と手作業のいずれにも有効に適用することができる。Note that the method of the present invention can be effectively applied to both work using an automatic bonding machine and manual work.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ　）、（ｂ）は本発明の一実施例を説明する
ための平面図、第２図は別の実施例を説明するための平
面図、第３図は従来のワイヤボンディング方法を示す平
面図である。 １・・・・・・・・・・・・インナーリードボンディン
グパッド ２・・・・・・・・・・・・アウターリードボンディン
グパッド ３・・・・・・・・・・・・半導体チップ４・・・・・
・・・・・・・ボンディングワイヤ５・・・・・・・・
・・・・回路基板 第１図 （ａ） （ｂ） 第２図 第３図FIGS. 1(a) and (b) are plan views for explaining one embodiment of the present invention, FIG. 2 is a plan view for explaining another embodiment, and FIG. 3 is a conventional wire bonding method. FIG. 1 Inner lead bonding pad 2 Outer lead bonding pad 3 Semiconductor chip 4・・・・・・
・・・・・・Bonding wire 5・・・・・・・・・
...Circuit board Figure 1 (a) (b) Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）回路基板上にダイボンドされた半導体チップ上に
千鳥状に配列された複数のインナーリードボンディング
パッドと、前記回路基板上にこれらのインナーリードボ
ンディングパッドと対向して、千鳥状に設けられた複数
のアウターリードボンディングパッドとを、ボンディン
グワイヤによりそれぞれ電気的に接続するにあたり、１
つ以上のボンディングパッドを隔ててインナーリードボ
ンディングパッドとこれに対応するアウターリードボン
ディングパッドとを順に接続した後、接続された各ボン
デッイングパッド間に位置するインナーリードボンディ
ングパッドとアウターリードボンディングパッドとを順
に電気的に接続することを特徴とするワイヤボンディン
グ方法。(1) A plurality of inner lead bonding pads arranged in a staggered manner on a semiconductor chip die-bonded on a circuit board, and a plurality of inner lead bonding pads provided in a staggered manner on the circuit board facing these inner lead bonding pads. When electrically connecting multiple outer lead bonding pads with bonding wires, 1
After sequentially connecting inner lead bonding pads and corresponding outer lead bonding pads across three or more bonding pads, the inner lead bonding pads and outer lead bonding pads located between the connected bonding pads are A wire bonding method characterized by sequentially electrically connecting. （２）半導体チップからの距離が近い方のアウターリー
ドボンディングパッドとこれに対向するインナーリード
ボンディングパッドとを順に接続した後、次に残された
インナーリードボンディングパッドとこれに対向する半
導体チップからの距離が離れた方のアウターリードボン
ディングパッドとを順に接続する特許請求の範囲第１項
記載のワイヤボンディング方法。(2) After sequentially connecting the outer lead bonding pad closest to the semiconductor chip and the opposing inner lead bonding pad, the next remaining inner lead bonding pad and the opposing semiconductor chip are connected. 2. The wire bonding method according to claim 1, wherein outer lead bonding pads that are separated by a distance are sequentially connected.
JP59207784A 1984-10-03 1984-10-03 Wire-bonding Granted JPS6185833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59207784A JPS6185833A (en) 1984-10-03 1984-10-03 Wire-bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59207784A JPS6185833A (en) 1984-10-03 1984-10-03 Wire-bonding

Publications (2)

Publication Number Publication Date
JPS6185833A true JPS6185833A (en) 1986-05-01
JPH0564460B2 JPH0564460B2 (en) 1993-09-14

Family

ID=16545445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59207784A Granted JPS6185833A (en) 1984-10-03 1984-10-03 Wire-bonding

Country Status (1)

Country Link
JP (1) JPS6185833A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647530A (en) * 1987-06-29 1989-01-11 Nec Corp Manufacture of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925238A (en) * 1982-08-03 1984-02-09 Toshiba Corp Semiconductor device
JPS59195856A (en) * 1983-04-20 1984-11-07 Fujitsu Ltd Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925238A (en) * 1982-08-03 1984-02-09 Toshiba Corp Semiconductor device
JPS59195856A (en) * 1983-04-20 1984-11-07 Fujitsu Ltd Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647530A (en) * 1987-06-29 1989-01-11 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0564460B2 (en) 1993-09-14

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