KR100402107B1 - Wire bonding method of sop - Google Patents
Wire bonding method of sop Download PDFInfo
- Publication number
- KR100402107B1 KR100402107B1 KR1019960077811A KR19960077811A KR100402107B1 KR 100402107 B1 KR100402107 B1 KR 100402107B1 KR 1019960077811 A KR1019960077811 A KR 1019960077811A KR 19960077811 A KR19960077811 A KR 19960077811A KR 100402107 B1 KR100402107 B1 KR 100402107B1
- Authority
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- South Korea
- Prior art keywords
- bonding
- wire
- wire bonding
- chip
- semiconductor chip
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 패키지의 와이어 본딩방법에 관한 것으로서, 특히 솝(SOP:Small Outline Package) 와이어 본딩방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding method of a semiconductor package, and more particularly, to a small outline package (SOP) wire bonding method.
일반적으로 반도체 소자의 칩 제조공정에서 설계된 단위셀을 배열하고 연결하기 위해 반도체 기판의 예정된 부분에 불순물의 선택적 도입공정, 절연층과 도전층을 적층하는 적층공정 및 패턴 마스크 공정등이 차례로 실행되어 웨이퍼에 집적회로가 형성된다.Generally, in order to arrange and connect unit cells designed in a chip manufacturing process of a semiconductor device, a selective introduction of impurities into a predetermined portion of a semiconductor substrate, a lamination process of laminating an insulating layer and a conductive layer, and a pattern mask process are sequentially performed. An integrated circuit is formed.
이와 같이 형성된 집적회로 칩은 조립공정으로 보내져서 칩절단, 칩부착, 와이어 본딩, 몰드, 트림 및 포밍공정 등의 순서로 진행하여 패키지화 된다.The integrated circuit chip thus formed is sent to an assembly process and packaged by proceeding in the order of chip cutting, chip attachment, wire bonding, mold, trimming and forming process.
도 1은 종래의 기술에 따른 것으로서, 와이어 본딩을 이용한 직접 칩 부착방법이 적용된 반도체 패키지의 단면도이다.1 is a cross-sectional view of a semiconductor package according to the related art, to which a direct chip attaching method using wire bonding is applied.
도 1을 참조하면, 기판(2)위에 접착제(3)에 의하여 부착된 반도체 칩(1)의 패드는 기판에 형성된 리드 배선과 와이어(4)를 이용하여 본딩하는 와이어 본딩법에 의하여 본딩된다. 그 후, 칩과 와이의 상부는 몰딩화합물을 이용하여 반구형으로 몰딩된다.Referring to FIG. 1, a pad of a semiconductor chip 1 attached to a substrate 2 by an adhesive 3 is bonded by a wire bonding method of bonding using a wire 4 and lead wires formed on the substrate. Thereafter, the top of the chip and the wire are molded in a hemispherical shape using a molding compound.
그러나, 상기한 반도체 칩의 패키지화 방법은 몰딩된 반구형의 지름과 높이가 패키지의 아웃라인을 결정하는 인자가 되므로, 패키지의 소형화에 한계를 가진다.However, the above-described method of packaging a semiconductor chip has a limitation in miniaturization of the package since the diameter and height of the molded hemispherical shape are factors that determine the outline of the package.
상기한 소형화의 문제를 해결하기 위하여 도 2에 도시한 것과 같이, 반도체 칩의 패드에 범프를 형성한 다음, 그 범프를 기판에 직접 본딩하는 플립 칩 본딩기술이 제시되었지만, 이 기술은 그 제조비용이 높다는 문제점이 존재한다.In order to solve the above-mentioned problem of miniaturization, as shown in FIG. 2, a flip chip bonding technique of forming a bump on a pad of a semiconductor chip and then bonding the bump directly to a substrate has been proposed. This high problem exists.
따라서, 본 발명은 상기한 문제점을 해결하기 위하여 안출된 것으로서, 저비용의 와이어 본딩방법을 이용하여 경박단소화를 달성할 수 있는 솝 와이어 본딩방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a thin wire bonding method capable of achieving light and thin shortening by using a low cost wire bonding method.
도 1은 종래의 실시예에 따른 것으로서, 직접 칩 부착방식에 따라 제작된 반도체 패키지의 단면도.1 is a cross-sectional view of a semiconductor package fabricated according to a conventional embodiment and manufactured according to a direct chip attaching method.
도 2는 종래의 다른 실시예에 따른 것으로서, 플립 칩 본딩된 반도체 패키지의 단면도.2 is a cross-sectional view of a flip chip bonded semiconductor package according to another conventional embodiment.
도 3A 내지 도 3C는 본 발명의 실시예에 따른 솝 와이어 본딩 방법을 보여주는 단면도.3A-3C are cross-sectional views illustrating a wire bonding method in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 반도체 칩 22 : 칩 캐리어21 semiconductor chip 22 chip carrier
23 : 와이어 24 : 기판23: wire 24: substrate
25 : 모세관25 capillary
본 발명에 따르면, 솝 반도체 패키지의 와이어 본딩방법은 패키지 대상용 반도체 칩이 안치되는 함몰부를 갖는 칩 캐리어의 함몰부에 반도체 칩을 부착하고, 반도체 칩의 패드와 칩 캐리어를 와이어 본딩하는 단계; 기판위에 상기 본딩된 상태의 칩 캐리어를 뒤집은 상태로 상기 와이어의 소정 부분을 상기 기판의 배선과 본딩하는 단계를 포함한다.According to the present invention, there is provided a wire bonding method of a semiconductor package, the method comprising: attaching a semiconductor chip to a recess of a chip carrier having a recess in which a semiconductor chip for packaging is placed, and wire bonding the pad and the chip carrier of the semiconductor chip; Bonding a predetermined portion of the wire to the wiring of the substrate while the chip carrier in the bonded state is turned over on the substrate.
[실시예]EXAMPLE
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 3A 내지 도 3C는 본 발명의 실시예에 따른 솝 와이어 본딩방법을 설명하는 도면이다.3A to 3C illustrate a wire bonding method according to an exemplary embodiment of the present invention.
도 3A를 참조하면, 솝 와이어 본딩을 위하여 패키지 대상용 반도체 칩이 안치되는 함몰부를 갖는 칩 캐리어(22)가 먼저 제공된다. 상기 함몰부에 반도체 칩의 패드부가 상부로 가도록 접착제를 이용하여 부착한 다음, 반도체 칩의 패드와 칩 캐리어를 1차 와이어 본딩한다.Referring to FIG. 3A, a chip carrier 22 having a recess in which a semiconductor chip for package object is placed is first provided for wire bonding. The recess is attached to the recess portion using an adhesive so that the pad portion of the semiconductor chip goes upward, and then the pad and the chip carrier of the semiconductor chip are first wire bonded.
도 3B를 참조하면, 1차 본딩된 상태의 칩 캐리어를 뒤집은 상태로 기판(24)에 접근시키고, 상기 와이어(23)의 소정 부분을 상기 기판상에 형성된 리드 배선과 모세관 웨지 단일점(Capilary wedge single point) 본딩방법에 의하여 2차 본딩한다.Referring to FIG. 3B, the chip carrier in the primary bonded state is inverted to approach the substrate 24, and a predetermined portion of the wire 23 is formed on the substrate by a lead wire and a capillary wedge formed on the substrate. single point) Secondary bonding by bonding method.
도 3C를 참조하면, 캐리어 기판(22)과 접착제를 반도체 칩(21)으로부터 분리하고, 캐리어 기판(22)과 기판(24) 사이에 연결된 와이어는 커팅하여 제거한다.Referring to FIG. 3C, the carrier substrate 22 and the adhesive are separated from the semiconductor chip 21, and the wires connected between the carrier substrate 22 and the substrate 24 are cut and removed.
상기의 실시예에서는 기판(24)에 와이어를 2차 본딩하기 위하여 모세관 웨지 단일점 본딩방법을 사용하였지만, 이 방법은 생산성의 향상을 위하여 바(Bar)본딩 또는 강(Gang) 본딩으로 대체될 수 있다.In the above embodiment, the capillary wedge single point bonding method is used to secondary bond the wire to the substrate 24. However, this method can be replaced by bar bonding or steel bonding to improve productivity. have.
또한, 상기에서 언급된 방법들에서, 본딩 와이어로서 사용되는 물질로는 금, 구리, 알루미늄중에서 하나가 선택되거나, 금/구리/알루미늄이 코팅된 와이어가 사용될 수 있다.Further, in the above-mentioned methods, the material used as the bonding wire may be one selected from gold, copper, aluminum, or a wire coated with gold / copper / aluminum.
이상에서 설명한 바와 같이, 본 발명의 솝 와이어 본딩방법은 캐리어 기판에 1차 와이어 본딩한 반도체 칩을 뒤집은 상태로 본딩된 와이어의 소정 부분을 기판과 2차 와이어 본딩하는 방법을 이용하므로써, 저비용으로 플립칩과 같은 경박단소화를 이룰 수 있다.As described above, the thin wire bonding method of the present invention flips at a low cost by using a method of bonding a predetermined portion of the bonded wire to the substrate with a secondary wire bonding in a state of inverting the primary chip bonded to the carrier substrate. It is possible to achieve light and thin shortening like a chip.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시 하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960077811A KR100402107B1 (en) | 1996-12-30 | 1996-12-30 | Wire bonding method of sop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960077811A KR100402107B1 (en) | 1996-12-30 | 1996-12-30 | Wire bonding method of sop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980058486A KR19980058486A (en) | 1998-10-07 |
| KR100402107B1 true KR100402107B1 (en) | 2004-02-05 |
Family
ID=37422443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960077811A KR100402107B1 (en) | 1996-12-30 | 1996-12-30 | Wire bonding method of sop |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100402107B1 (en) |
-
1996
- 1996-12-30 KR KR1019960077811A patent/KR100402107B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980058486A (en) | 1998-10-07 |
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