JPS60160134A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS60160134A
JPS60160134A JP59016611A JP1661184A JPS60160134A JP S60160134 A JPS60160134 A JP S60160134A JP 59016611 A JP59016611 A JP 59016611A JP 1661184 A JP1661184 A JP 1661184A JP S60160134 A JPS60160134 A JP S60160134A
Authority
JP
Japan
Prior art keywords
pellets
relay
semiconductor
land
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59016611A
Other languages
Japanese (ja)
Inventor
Yukitaka Tokumoto
幸孝 徳本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP59016611A priority Critical patent/JPS60160134A/en
Publication of JPS60160134A publication Critical patent/JPS60160134A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/481—Disposition
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    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the respondency to any type alteration of pellets by a method wherein, when multiple semiconductor pellets are mounted on a land comprising a leadframe to compose a hybrid integrated circuit device, the land is additionally provided with multiple relay pellets with relay conductive patterns for electric connection. CONSTITUTION:Multiple leads 9 respectively connected using tiebars are located around a land 8 comprising a lead-frame 7 while semiconductor pellets 11 such as multiple IC etc. bonded on the land 8 are connected to specified leads 9 by means of bonding wires 13 made of metal wires or aluminium wires. In such a constitution, the other insulating pellets 12 with relay conductive patterns 14 are mounted on the same land 8 by means of soldering process keeping away from the pellets 11 to be utilized in case of any type alteration of the pellets 11. The cost of pellets 12 may be saved since any defective semiconductors produced in ordinary semiconductor manufacturing process may be utilized for the pellets 12.

Description

【発明の詳細な説明】 イ、産業上の利用分野 この発明はリードフレームの１つのランド部上に複数の
半導体ペレットをマウントし配線したＨＩＣ（混成集積
回路装置）に利用される。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is applied to an HIC (hybrid integrated circuit device) in which a plurality of semiconductor pellets are mounted and wired on one land portion of a lead frame.

口、従来技術 一般にモノリシックＩＣはシグナル用、パワー用などの
単一機能の１個のモノリシックＩＣペレットをリードフ
レームのランド部にマウントし配線したもので、１個の
ＩＣの機能はそのＩＣペレットの機能に限定される。そ
こで１個のパッケージ内に多機能を持たせたものとして
、リードフレームの１つのランド部上にトランジスタ等
同一機能の複数の半導体ペレットをマウントし配線した
ＨＩＣが開発され実用化されている。Conventional technology In general, a monolithic IC is a monolithic IC pellet with a single function such as signal or power, mounted on the land of a lead frame and wired.The function of one IC depends on the IC pellet. Limited to functionality. Therefore, as a package with multiple functions, an HIC has been developed and put into practical use, in which a plurality of semiconductor pellets having the same function, such as transistors, are mounted and wired on one land portion of a lead frame.

又、多機能、異機能を持たせたものとしてＩＣ、トラン
ジスタ等異種機能の半導体ペレ・ントをマウントし配線
したＨＩＣも考案されている。Furthermore, HICs have been devised to provide multi-functions and different functions, in which semiconductor pellets with different functions such as ICs and transistors are mounted and wired.

例えば第１図に示すように１枚のリードフレーム（１）
のランド部（２）上に複数（図面では４１！＞の半導体
ペレット（３）（３）−をマウントして、半導体ペレッ
ト間及び半導体ペレッ）　（３）（３）、−ｍ−と対応
するリード（４）（４）−・−間とにワイヤ（５）（５
）、−・をボンディングして電気的に接続したものがあ
る。尚、（６）（６）−・・は各リード（４）（４）・
−を連結一体化してリードフレーム（１）を構成するタ
イバーで、ワイヤボンディング後第１図鎖線部分をパッ
ケージ化した後タイバー（６）（６）・−・はり一ド（
４）（４）−・−・−から切断分離される。このような
ＨＩＣは１つで多機能を持つが、次の（ａ）〜（ｃ）の
問題を含んでいた。For example, as shown in Figure 1, one lead frame (1)
A plurality of semiconductor pellets (3) (3) - (41 in the drawing) are mounted on the land part (2) of (3) (3), which corresponds to -m-. Connect the wires (5) (5) between the leads (4) (4) and -.
), - and are electrically connected by bonding. In addition, (6) (6) -... is each lead (4) (4).
- is the tie bar that connects and integrates the lead frame (1). After wire bonding, the chain line part in Figure 1 is packaged, and then the tie bar (6) (6)...
4) It is cut and separated from (4)--. Although such a HIC has multiple functions, it has the following problems (a) to (c).

（ａ）ペレット間及びバレント−リード間の配線上の都
合からリードフレーム（１）の設計力複雑となり、且つ
マウントされる半導体ペレ７）　（３）（３）・−・・
−に種類変更があるとその変更に応じリードフレーム（
１）を設計し直す必要があり、リードフレーム（１）の
標準化が難しかった。(a) The design of the lead frame (1) becomes complicated due to the wiring between the pellets and between the valent and the lead, and the semiconductor pellet to be mounted 7) (3) (3)...
− If there is a change in type, the lead frame (
1) had to be redesigned, making it difficult to standardize the lead frame (1).

（ｂ）ベレット間及びベレット−リード間の配線を全て
最良にすることは事実上無理で、どうしてもワイヤ（５
）（５）・・−に長過ぎるもの、短か過ぎるものが発生
し、長過ぎるものは製造途中で垂れ下って半導体ベレッ
ト（３）（３）−・やランド部（２）上にショートした
り、短か過ぎるものは製造の途中の外的シｍｙり等で断
線したり、特に半導体ベレット（３）（３）・−とのコ
ンタクト部が不良（ルーズコンタクト）になることがあ
り、製品の信頼性を悪（していた。(b) It is virtually impossible to optimize the wiring between the bellets and between the bellets and the leads;
)(5)...- are too long or too short, and those that are too long will hang down during manufacturing and short-circuit onto the semiconductor pellet (3) (3)-... or land (2). If it is too short or too short, it may break due to external shimmering during manufacturing, and the contact part with the semiconductor bullet (3) (3) - may become defective (loose contact), which may cause the product to deteriorate. The reliability of (was) bad.

（ｅ）ペレット間のワイヤボンディングが非常に難しく
て信頼性が悪かった。即ち、半導体ベレット（３）のボ
ンディングバンドサイズはワイヤ（５）の線径の３〜４
倍（金線使用の設計の場合、７５〜１５０１１ｍ　／口
）が一般的であり、ペレット間のワイヤボンディングは
キャピラリ方式で先ずキャピラリ先端でワイヤ先端の金
球を１つの半導体ベレット（３）のポンディングパッド
に熱圧着して接続しく１ｓｔボンデイング）、次にキャ
ピラリからワイヤ（５）を繰り出して他の半導体ベレッ
ト〈３）のポンディングパッドに熱圧着又は熱圧着と超
音波パワーとを印加して接続（２ｎｄボンディング）し
てワイヤ切断する工程で行っている。この１ｓｔボンデ
イングはワイヤ金球を使用するため比較的良好に行える
が、２ｎｄボンデイングはワイヤ金球を使用しない、い
わゆるステッチボンディングで而も半導体ベレット（３
）のポンディングパッドが小面積のため難しくて使用ワ
イヤー径の３〜６倍となり、金球はみ出しが発生し、所
定の′ポンディングパッド部への融着面積が少なし）た
め、その強度が弱くルーズコンタクトになる可能性が大
きく、精度良く行うには特殊機能を持つ高価なワイヤボ
ンダーを使用しなければならなかうた。(e) Wire bonding between pellets was extremely difficult and unreliable. That is, the bonding band size of the semiconductor pellet (3) is 3 to 4 times the wire diameter of the wire (5).
wire bonding between the pellets is done using the capillary method. First, the gold ball at the tip of the wire is bonded to one semiconductor pellet (3) using the capillary tip. (1st bonding) to connect by thermocompression bonding to the bonding pad (1st bonding), then feed out the wire (5) from the capillary and apply thermocompression bonding or thermocompression bonding and ultrasonic power to the bonding pad of the other semiconductor bullet (3). This is done in the process of connecting (2nd bonding) and cutting the wire. This 1st bonding uses a wire gold ball and can be performed relatively well, but the 2nd bonding does not use a wire gold ball, it is so-called stitch bonding, and it is a semiconductor bullet (3
) is difficult due to the small area of the bonding pad, which is 3 to 6 times the diameter of the wire used, causing the gold balls to protrude, and the area to be fused to the specified 'ponding pad part is small), so its strength is There is a high possibility that the contact will be weak and loose, and an expensive wire bonder with special features must be used to achieve accurate bonding.

ハ６発明の目的 本発明の目的は上記問題点を解決することであり、半導
体−ル、２トの種類変更に対する対応性に優れ、生産設
備的に有利で且つ信頼性に優れた）（ＩＣを提供するに
ある。C6 Purpose of the Invention The purpose of the present invention is to solve the above-mentioned problems. is to provide.

二９発明の構成 本Ｑ明はリードフレームの１つのランド部上に複数の半
導体ベレットと共に半導体ベレット間や半導体ベレット
とリード間の電気的接続用中継ベレットをマウントした
構造を特徴とする。前記中継ベレットは、その上面に中
継用の導電パターンが形成される。このような中継ベレ
ット使用により半導体ベレットとリード番よ無理の無い
配線が実行でき、上記目的が達成される。29 Structure of the Invention The present invention is characterized by a structure in which a plurality of semiconductor pellets and a relay pellet for electrical connection between the semiconductor pellets or between the semiconductor pellets and the leads are mounted on one land portion of the lead frame. A conductive pattern for relaying is formed on the upper surface of the relay pellet. By using such a relay pellet, wiring can be carried out easily between the semiconductor pellet and the lead number, and the above object is achieved.

ホ、実施例 第２図及び第３図において、（７）はリードフレームで
、ランド部（８）とその近傍から延びる複数のリード（
９）（９）−・−をタイバー（１０）（１０）　−で一
連に一体化したものｔある。（１１）（１１）”−−・
−はランド部（８）上にマウントされたＩＣ等の複数の
半導体ベレット、（１２）はランド部（８）上に少くと
も１個がマウントされた中継ベレットで、図面では３Ｉ
Ｉ＆Ｉを示す。（１３）（１３）−・−は金線やアルミ
ニウム線等のボンディングワイヤである。E. Example In FIGS. 2 and 3, (7) is a lead frame, and a plurality of leads (7) extending from the land portion (8) and its vicinity are shown in FIG.
9) (9) - - are integrated in series with tie bars (10) (10) -. (11) (11)”---・
- is a plurality of semiconductor pellets such as ICs mounted on the land part (8), (12) is a relay pellet with at least one mounted on the land part (8), and in the drawing, 3I
Indicates I&I. (13) (13) -- is a bonding wire such as a gold wire or an aluminum wire.

上記中継ベレット（１２）　（１２）−・−・は第４図
に示すように上面に中継用導電パターン（１４）（１４
）　−・が形成された絶縁ベレットで、ランド部（８）
上の後述中継に通した所望の部分にＡｇペーストや半田
などを介しマウントされる。中継ベレット（１２）　（
１２）・−・は半導体ベレット（１１）　（１１）−・
・と同材質の例えばシリコンで形成され、これをランド
部（８）への半導体装置ット（１１）　（１１）・−の
マウントに供されるロー材と同じＡ、ｇペーストや半田
でマウントするようにすれば、半導体ペレット（１１）
　（１１）−のマウンターで中継ペレット（１２）　（
１２）−・のマウントが連続的に実行でき、而も半導体
ペレッ）　（１１）　（１１）・−・と同じ様に位置ず
れの少ない高精度のマウントが実行できる。また中継ペ
レット（１２）　（１２）・−をシリコン製にすること
により中継ペレット（１２＞　（１２）−・は一般的半
導体製造工程中でできる外観や特性の不良シリコンウェ
ーハを利用して製作することができ、材料コスト的に有
利であり、又中継ペレット（１２）（１２）　−・への
ワイヤボンディングも半導体ペレッ）　（１１）　（１
１）・−と同一条件で高精度に行える。The relay bellets (12) (12) --- have relay conductive patterns (14) (14
) -・ is formed on the insulating pellet, and the land part (8)
It is mounted on the desired portion passed through the above-described relay using Ag paste, solder, or the like. Relay bellet (12) (
12) --- is a semiconductor pellet (11) (11)--
・For example, it is made of the same material as silicon, and is mounted using the same A, G paste or solder as the brazing material used to mount the semiconductor device (11) (11)・- to the land portion (8). If you do this, semiconductor pellets (11)
(11) - Relay pellets (12) (
12) Mounting of semiconductor pellets) (11) and (11) can be carried out continuously, and high precision mounting with little positional deviation can be carried out in the same manner as (11). In addition, by making the relay pellets (12) (12) - made of silicon, the relay pellets (12 > (12) -) can be manufactured using silicon wafers with defective appearance and characteristics that are produced during the general semiconductor manufacturing process. It is advantageous in terms of material cost, and wire bonding to relay pellets (12) (12) -. is also possible with semiconductor pellets) (11) (1
1) Can be performed with high accuracy under the same conditions as -.

中継ペレット（１２）　（１２）・−・は半導体ペレッ
）　（１１）　（１１）・−・とり一部　（９）　（９
）−・の間、２つの半導体ペレット＜ｏ）（１１）の間
などに配置され、所定の半導体ペレット（１１）とリー
ド（９）　、２つの半導体ペレット（１１）　（１１）
の電気的接続の中継を行う０例えば第３図に示すように
２つの半導体ペレッ）　（１１）　（１１）間に配置さ
れた中継ペレット（１２）には２つの半導体ペレット（
１１）　（１１’　）の対応するポンディングパッド＜
１５）　（１５’　”）から延びるワイヤ（１３）　（
１３°）の一端が１つの導電パターン（１４）にボンデ
ィングされて、両ポンディングパッド（１５）　（１５
”））（導電パターン（１４）で中継接続される。この
場合のワイヤボンディングは導電パターン（１４）を例
えば３００μ−７口など十分広面積に形成して１ｓｔボ
ンデイングを半導体ペレット側で、２ｎｄボンデイング
を中継ペレット側で行えばよく、このようにすれば２ｎ
ｄボンデイング側の導電パターン（１４）が広面積のた
め２ｎｄボンデイングが通常の安価なワイヤボンダでも
十分良好に行え、半導体ペレット間のワイヤボンディン
グ上の従来問題点が難無（解決される。又、特に作業性
、信頼性の面ではこれらのワイヤ長は同一である事が望
ましい。Relay pellet (12) (12) --- is semiconductor pellet) (11) (11) --- Part of it (9) (9
)--, between two semiconductor pellets <o) (11), etc., a predetermined semiconductor pellet (11) and a lead (9), two semiconductor pellets (11)
For example, as shown in Figure 3, the relay pellet (12) placed between two semiconductor pellets (11) relays the electrical connection between the
11) Corresponding bonding pad of (11')<
15) (15''') Wire extending from (13) (
13°) is bonded to one conductive pattern (14) and both bonding pads (15) (15
”)) (Relay connection is made using the conductive pattern (14). In this case, the wire bonding is performed by forming the conductive pattern (14) with a sufficiently wide area, for example, 300μ-7 holes, and performing the first bonding on the semiconductor pellet side and the second bonding. It is sufficient to perform this on the relay pellet side, and in this way, 2n
Because the conductive pattern (14) on the d-bonding side has a large area, 2nd bonding can be performed satisfactorily with a normal inexpensive wire bonder, and the conventional problems in wire bonding between semiconductor pellets are easily solved. In terms of workability and reliability, it is desirable that these wire lengths be the same.

これに対しては、中継ペレット（１２）　（１２）・−
を上記ペレット間の中継と共に半導体ペレッ）　（１１
＞　（１１）・−・とり一部（９）　（９）・−の中継
に利用することにより、ワイヤ（１３）　（１３）−・
の配線パターンが無理なく設計できてワイヤ（１３）　
（１３）・−が長過ぎたり短か過ぎたりすることが無く
なり、ワイヤシッートやルーズコンタクト等の配線上の
トラブルが減少する。また半導体ペレット（１１）　（
１０−・に種類変更があっても、この変更に応じ中継ペ
レット（１２）（１２）・−の数や種類、配置位置を変
更させるだけで同一のリードフレーム（７）を使用する
こができ、リードフレーム（７）の標準化を容易にする
。In contrast, relay pellets (12) (12)・−
(semiconductor pellet) (11
> By using (11)... to relay part (9) (9)..., wire (13) (13)-...
The wiring pattern can be designed easily and the wire (13)
(13) - will not be too long or too short, and wiring problems such as wire seats and loose contacts will be reduced. Also, semiconductor pellets (11) (
Even if there is a change in the type of 10-., the same lead frame (7) can be used by simply changing the number, type, and arrangement position of the relay pellets (12) (12).- according to this change. , facilitating standardization of lead frames (7).

尚、中継ペレット（１２）　（１２）・−・の外部や導
電パターン（１４）　（１４）−・の形状は上記例に限
らず、例えば第５図に示す中継ペレット（１２’　）に
示すようにその上面の１つの導電パターン（１４°）の
中間に抵抗阻止パターン（１４”　）を形成して、２つ
のワイヤ（１３）　（１３）を抵抗Ｒを介し中継するよ
うにしてもよい。Note that the shapes of the outside of the relay pellets (12) (12)... and the conductive patterns (14) (14)-- are not limited to the above example, but may be shaped as shown in the relay pellet (12') shown in Fig. 5, for example. A resistive blocking pattern (14'') may be formed in the middle of one conductive pattern (14°) on the upper surface thereof, and the two wires (13) (13) may be relayed through the resistor R.

へ０発明の詳細 な説明したように、本発明によれば中継ペレットにより
リードフレームの標準化、半導体ペレット間のワイヤボ
ンディング、ボンディングワイヤの配線上のトラブル等
の問題が解決でき、信頼性の高いＨＩＣの提供が可能で
あり、また生産設備を大きく変更すること無く生産でき
、而も品種変更のニーズに対する対応性が良くて多品種
少量生産にも通したＨＩＣが提供できる。As described in detail, according to the present invention, problems such as standardization of lead frames, wire bonding between semiconductor pellets, wiring problems of bonding wires, etc. can be solved by relay pellets, and highly reliable HIC can be achieved. In addition, it is possible to provide an HIC that can be produced without major changes to production equipment, has good responsiveness to needs for changing product types, and can be used for high-mix, low-volume production.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＨＩＧの要部平面図、第２図は本発明の
一実施例を示す要部平面図、第３図は第２図の一部拡大
断面図、第４図は第２図の一部拡大斜視図、第５図は中
継ペレットの変形例を示す斜視図である。 （７）　・・リードフレーム、（８）・・ランド部、　
（９）・　・リード、　（１１）　（１１″　）　・　
・半導体ペレット、（１２）　（１２’　）　・・中継
ペレット、（１４）　（１４’　）　・・導電パターン
。 手続補正書 昭和５９年　５月　９日 １、事件の表示 昭和５９年特許願第１６６１１号 ２、発明の名称 ＩＣ ３、補正をする者 事件との関係　特許出願人 名称関西日本電気株式会社 ４、代理人 住　所　大阪府大阪市西区江戸ｇｉＡ１丁目１５番２６
号大阪商エビルア階 氏　名　（６４５Ｂ）弁理士　江　原　省　吾（ほか１
名） ５、補正の対象 明細書中 １０発明の名称を下記の通り補正する。 「混成集積回路装置、Ｉ ■、特許請求の範囲を下記の通り補正する。 「（１）　リードフレームの１つのランド部上に複数の
半導体ベレットをマウントした混成集積回路装置におい
て、前記ランド部上に上面に前記半導体ベレット間や前
記半導体ベレットと前記リードフレームのリード間の電
気的接続用中継導電パターンを有する中継ベレットをマ
ウントしたことを特徴とする混成集積回路装置、」■、
第１頁第１６行 ｒＨＴＣ（混成集積回路装置）」を ｒ’　Ｊ色補正する。 ■、第２頁第６行、第１０行、第３頁第３行、第５頁第
１２行、第１０頁第６行、第９行、ＩＪ１２行 ｒＨＩ　ＣＪを 「、混、成！］ｕＬｉ！ｌ韮」と補正する。FIG. 1 is a plan view of the main part of a conventional HIG, FIG. 2 is a plan view of the main part showing an embodiment of the present invention, FIG. 3 is a partially enlarged sectional view of FIG. FIG. 5 is a partially enlarged perspective view of the figure, and FIG. 5 is a perspective view showing a modification of the relay pellet. (7)...Lead frame, (8)...Land part,
(9)・・Lead, (11) (11″)・
- Semiconductor pellet, (12) (12') ... Relay pellet, (14) (14') ... Conductive pattern. Procedural amendment May 9, 1981 1. Indication of the case Patent Application No. 16611 of 1988 2. Name of the invention IC 3. Person making the amendment Relationship to the case Patent applicant name Kansai NEC Co., Ltd. 4. Agent address: 1-15-26 EdogiA, Nishi-ku, Osaka-shi, Osaka
No. Osaka Commercial Evil Aki Name (645B) Patent Attorney Shogo Ehara (and 1 others)
5. The titles of 10 inventions in the specification to be amended are amended as follows. ``Hybrid integrated circuit device, I ■'', the claims are amended as follows: ``(1) In a hybrid integrated circuit device in which a plurality of semiconductor pellets are mounted on one land portion of a lead frame, A hybrid integrated circuit device, characterized in that a relay pellet having a relay conductive pattern for electrical connection between the semiconductor pellets or between the semiconductor pellets and the leads of the lead frame is mounted on the top surface of the hybrid integrated circuit device,
1st page, 16th line, r'J color correction for ``rHTC (hybrid integrated circuit device)''. ■, page 2, line 6, line 10, page 3, line 3, page 5, line 12, page 10, line 6, line 9, IJ line 12 rHI CJ as ", mixed, formed!" uLi!l韮” he corrected.

Claims (1)

【特許請求の範囲】[Claims] （１１１Ｊ−’Ｆフレームの１つのランド部上に複数の
半導体ペレットをマウントしたＨＩＣにおいて、前記ラ
ンド部上に上面に前記半導体ペレット間や前記半導体ペ
レットと前記リードフレームのリード間の電気的接続用
中継導電パターンを有する中継ペレットをマウントした
ことを特徴とするＩ（Ｉ　Ｃ。(In a HIC in which a plurality of semiconductor pellets are mounted on one land part of a 111J-'F frame, an upper surface on the land part is used for electrical connection between the semiconductor pellets or between the semiconductor pellets and the leads of the lead frame. I (IC) characterized by mounting a relay pellet having a relay conductive pattern.
JP59016611A 1984-01-30 1984-01-30 Hybrid integrated circuit Pending JPS60160134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59016611A JPS60160134A (en) 1984-01-30 1984-01-30 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59016611A JPS60160134A (en) 1984-01-30 1984-01-30 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60160134A true JPS60160134A (en) 1985-08-21

Family

ID=11921112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59016611A Pending JPS60160134A (en) 1984-01-30 1984-01-30 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60160134A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5096852A (en) * 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
JP2009164653A (en) * 2009-04-27 2009-07-23 Renesas Technology Corp Multi-chip module
US8951847B2 (en) 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598837A (en) * 1979-01-19 1980-07-28 Mitsubishi Electric Corp Semiconductor device
JPS55127032A (en) * 1979-03-24 1980-10-01 Mitsubishi Electric Corp Plastic molded type semiconductor device
JPS56100436A (en) * 1980-01-17 1981-08-12 Toshiba Corp Manufacture of semiconductor element
JPS58192335A (en) * 1982-05-07 1983-11-09 Hitachi Ltd Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598837A (en) * 1979-01-19 1980-07-28 Mitsubishi Electric Corp Semiconductor device
JPS55127032A (en) * 1979-03-24 1980-10-01 Mitsubishi Electric Corp Plastic molded type semiconductor device
JPS56100436A (en) * 1980-01-17 1981-08-12 Toshiba Corp Manufacture of semiconductor element
JPS58192335A (en) * 1982-05-07 1983-11-09 Hitachi Ltd Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5096852A (en) * 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
JP2009164653A (en) * 2009-04-27 2009-07-23 Renesas Technology Corp Multi-chip module
US8951847B2 (en) 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly

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