JPH0546271Y2 - - Google Patents

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Publication number
JPH0546271Y2
JPH0546271Y2 JP1987099366U JP9936687U JPH0546271Y2 JP H0546271 Y2 JPH0546271 Y2 JP H0546271Y2 JP 1987099366 U JP1987099366 U JP 1987099366U JP 9936687 U JP9936687 U JP 9936687U JP H0546271 Y2 JPH0546271 Y2 JP H0546271Y2
Authority
JP
Japan
Prior art keywords
electrode body
chip
lead wire
thin lead
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987099366U
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Japanese (ja)
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JPS646041U (en
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Priority to JP1987099366U priority Critical patent/JPH0546271Y2/ja
Publication of JPS646041U publication Critical patent/JPS646041U/ja
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Publication of JPH0546271Y2 publication Critical patent/JPH0546271Y2/ja
Anticipated expiration legal-status Critical
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳现な説明】 産業䞊の利甚分野 本考案は、぀の電極䜓をリヌド现線にお接続
した構造を有する絶瞁物封止型半導䜓装眮に関連
する。
[Detailed Description of the Invention] Industrial Application Field The present invention relates to an insulator-sealed semiconductor device having a structure in which two electrode bodies are connected by a thin lead wire.

埓来の技術 第図は、埓来の暹脂封止型耇合ICの䞀郚を
瀺す斜芖図である。この暹脂封止型耇合ICはリ
ヌドフレヌムから圢成された支持電極䜓及び配
線電極䜓を有し、支持電極䜓䞊にはパワ
ヌトランゞスタチツプが半田図瀺せずにお
固着されおいる。パワヌトランゞスタチツプの
䞊面には耇数の電極ボンデむングパツドが圢
成されおいるが図瀺は省略する。ボンデむングパ
ツドには本のリヌド现線が接続されおおり、
リヌド现線は、図瀺の劂く配線電極䜓を跚い
で配線電極䜓に接続されおいる。これにより配
線電極䜓ずリヌド现線が倚重配線ずな぀おい
る。次に、リヌド现線の接続方法を第図に぀い
お説明する。
Prior Art FIG. 4 is a perspective view showing a part of a conventional resin-sealed composite IC. This resin-sealed composite IC has a supporting electrode body 1 formed from a lead frame and wiring electrode bodies 2 and 3, and a power transistor chip 4 is fixed on the supporting electrode body 1 with solder (not shown). has been done. A plurality of electrodes (bonding pads) are formed on the upper surface of the power transistor chip 4, but are not shown. Two thin lead wires 5 are connected to the bonding pad.
The thin lead wire 5 is connected to the wiring electrode body 2 across the wiring electrode body 3 as shown in the figure. As a result, the wiring electrode body 3 and the thin lead wire 5 form multiple wirings. Next, a method for connecting thin lead wires will be explained with reference to FIG.

たず、第図に瀺すように、ワむダボンダの
パむプ状のキダピラリの䞭心孔からリヌ
ド现線を送り出し、電気スパヌク又は氎玠炎
等でリヌド现線の先端郚にボヌルを圢成
する。ボヌルの盎埄は、リヌド现線の盎
埄の〜倍皋床である。
First, as shown in FIG. 5A, a thin lead wire 52 is sent out from the center hole 51 of a pipe-shaped capillary 50 of a wire bonder, and a ball 53 is formed at the tip of the thin lead wire 52 using an electric spark, a hydrogen flame, or the like. The diameter of the ball 53 is about 2 to 3 times the diameter of the thin lead wire 52.

次に、第図に瀺すように、第䞀の電極䜓
にボヌルをキダピラリの先端で抌し付
け第䞀のボンデむングを行う。この際、第䞀の電
極䜓は200〜250℃に予め加熱されおいる。た
た、キダピラリには、リヌド现線の接続
方向ず盎角な矢印で瀺す方向ぞの超音波振動
が加えられおいる。これにより、第䞀の電極䜓
にリヌド现線が釘頭状に接続された第䞀の
ボンデむング郚が圢成される。
Next, as shown in FIG. 5B, the first electrode body 5
First bonding is performed by pressing the ball 53 onto the capillary 4 with the tip of the capillary 50. At this time, the first electrode body 54 is preheated to 200 to 250°C. Further, ultrasonic vibration is applied to the capillary 50 in the direction indicated by an arrow 55 perpendicular to the connection direction of the thin lead wire 52. As a result, the first electrode body 5
4 is formed with a first bonding portion 52a to which a thin lead wire 52 is connected like a nail head.

続いお、第図に瀺すように、キダピラリ
を䞊昇しお倧きく匕き回すようにしお、リヌド
现線を繰り出しながら第二の電極䜓に向
か぀おキダピラリを移動する。
Next, as shown in FIG. 5C, the capillary 5
The capillary 50 is moved toward the second electrode body 56 while letting out the thin lead wire 52 by raising the capillary 50 and drawing it widely.

その埌、第図に瀺すように、第二の電極䜓
に第二のボンデむングを行う。即ち、第二の
電極䜓は前述ず同様に200〜250℃に予め加熱
され、キダピラリには前述ず同様の超音波振
動が加えられおいる。この状態で、第二の電極䜓
に察し埄方向にリヌド现線を抌圧するこ
ずにより、リヌド现線ず第二の電極䜓ず
が接続され、第二のボンデむング郚が圢成
される。なお、第図の工皋を電極䜓の加
熱のみによる熱圧着法又は超音波振動による加熱
のみの超音波法等で行぀おもよい。
Thereafter, as shown in FIG. 5D, second bonding is performed on the second electrode body 56. That is, the second electrode body 56 is preheated to 200 to 250° C. as described above, and the same ultrasonic vibration as described above is applied to the capillary 50. In this state, by pressing the thin lead wire 52 against the second electrode body 56 in the radial direction, the thin lead wire 52 and the second electrode body 56 are connected, and a second bonding portion 52b is formed. Note that the steps shown in FIGS. 5B and 5D may be performed by a thermocompression bonding method using only heating of the electrode body or an ultrasonic method using only heating using ultrasonic vibration.

最終的には、第図のように、キダピラリ
を䞀定の高さたで䞊昇した埌、クランプでリヌ
ド现線を抌さえ぀぀曎にキダピラリを䞊
昇させおリヌド现線を切断する。狭矩には、
第䞀のボンデむングをネむルヘツドボンデむン
グ、第二のボンデむングをステむツチボンデむン
グず呌称するが、ここではそれら぀を総称しお
ネむルヘツドボンデむング法ずする。第図に
瀺すように、第䞀のボンデむング偎では、第䞀の
電極䜓に察するリヌド现線の角床αはほが盎
角ずなり、䞊を跚るリヌド现線ず第䞀の電極
䜓ずの距離は長くなる。䞀方、第二のボンデむン
グ偎では、リヌド现線の第二の電極䜓に察す
る角床Ξは鋭角ずなり、䞊を跚るリヌド现線
ず第二の電極䜓ずの距離は短くなる。
Finally, connect the capillary 5 as shown in Figure 5E.
0 to a certain height, the capillary 50 is further raised while holding the thin lead wire 52 with a clamp, and the thin lead wire 52 is cut. In a narrow sense,
The first bonding method is called nail head bonding, and the second bonding method is called static bonding, but here they are collectively referred to as the nail head bonding method. As shown in FIG. 5D, on the first bonding side, the angle α of the thin lead wire 52 with respect to the first electrode body is almost a right angle, and the distance between the thin lead wire 52 that straddles above and the first electrode body is long. Become. On the other hand, on the second bonding side, the angle Ξ of the thin lead wire 52 with respect to the second electrode body is an acute angle, and the thin lead wire 52 spanning over
The distance between the electrode body and the second electrode body becomes shorter.

考案が解決しようずする問題点 埓来ではリヌド现線の垂䞋により配線電極䜓に
リヌド现線が接觊し、短絡䞍良の原因ずな぀おい
た。即ち、第図に瀺すように、配線電極䜓を
跚いでリヌド现線が接続されおいる。半導䜓装
眮の高集積化の芁求により配線が䞀局耇雑化する
傟向にある。このため配線電極䜓を跚ぐ接続を行
わなければならないこずが倚い。
Problems to be Solved by the Invention In the past, the thin lead wires came into contact with the wiring electrode body due to the thin lead wires hanging down, causing short-circuit failures. That is, as shown in FIG. 4, a thin lead wire 5 is connected across the wiring electrode body 3. Due to the demand for higher integration of semiconductor devices, wiring tends to become more complex. For this reason, it is often necessary to make a connection across the wiring electrode body.

ずころで、第䞀の電極䜓であるパワヌトランゞ
スタチツプ䞊の電極ず第二の電極䜓である配線
電極䜓ずの間に第䞉の電極䜓ずしお圢成された
配線電極䜓は、リヌド现線に察しおは非接続
配線䜓ずな぀おいる。このため、リヌド现線は
ワむダボンデむングの際に倧きく孀を描くように
接続しお、リヌド现線ず配線電極䜓ずの間の
距離をできるだけ取るようにしおいる。リヌド现
線は、前述のネむルヘツドボンデむング法によ
り、第䞀のボンデむング郚ではパワヌトランゞス
タチツプに接続され、第二のボンデむング郚で
は配線電極䜓に接続されおいる。たた、第䞀の
ボンデむング郚は第二のボンデむング郚よりおよ
そパワヌトランゞスタチツプの厚さ分だけ高い
䜍眮ずな぀おいる。このため、配線電極䜓は、
支持電極䜓偎ではリヌド现線ずの距離が長く
なるが、配線電極䜓偎ではリヌド现線ずの距
離が短くなる。
By the way, the wiring electrode body 3 formed as a third electrode body between the electrode on the power transistor chip 4 which is the first electrode body and the wiring electrode body 2 which is the second electrode body is connected to the thin lead wire 5. It is a non-connected wiring body. For this reason, the thin lead wires 5 are connected in a large arc during wire bonding, so that the distance between the thin lead wires 5 and the wiring electrode body 3 is maintained as much as possible. The thin lead wire 5 is connected to the power transistor chip 4 at the first bonding part and to the wiring electrode body 2 at the second bonding part by the above-mentioned nail head bonding method. Further, the first bonding portion is located at a position higher than the second bonding portion by approximately the thickness of the power transistor chip 4. Therefore, the wiring electrode body 3 is
On the supporting electrode body 1 side, the distance to the thin lead wire 5 becomes long, but on the wiring electrode body 2 side, the distance to the thin lead wire 5 becomes short.

通垞䜿甚される盎埄玄30ÎŒmの金補のリヌド现
線は现くか぀柔らかいため、十分な匷床を期埅で
きないのが実情である。䟋えば、第䞀の電極䜓ず
第二の電極䜓ずを接続する金補のリヌド现線は、
トランスフアモヌルド時の暹脂泚入圧力を自重等
により懞垂状に垂䞋するルヌプタレを発生するこ
ずがあ぀た。通垞、盎埄が25〜30ÎŒmの金補のリ
ヌド现線では、接続距離はmmが限界ずされ
る。接続距離がmmを越えるず、自重によりル
ヌプタレが発生する。実際には、トランスフアモ
ヌルド時の暹脂泚入圧力を考慮しなければならな
いから、実甚的な接続距離の長さは曎に短くな
る。接続距離を短くするには非接続配線䜓の幅
を现くするこずが考えられる。しかし、リヌドフ
レヌムの機械的匷床が匱たる等の制玄により、あ
たり现くするこずはできない。よ぀お、第図の
䟋では接続距離3.3mmず長くなり、ルヌプタ
レが問題になり易い状態にある。
The reality is that the normally used fine gold lead wire with a diameter of about 30 ÎŒm is thin and soft, so it cannot be expected to have sufficient strength. For example, the thin gold lead wire connecting the first electrode body and the second electrode body is
During transfer molding, resin injection pressure sometimes caused loop sagging due to its own weight. Normally, for a thin gold lead wire with a diameter of 25 to 30 ÎŒm, the connection distance L is limited to 3 mm. If the connection distance L exceeds 3 mm, loop sag will occur due to its own weight. In reality, since the resin injection pressure during transfer molding must be taken into account, the practical length of the connection distance L becomes even shorter. In order to shorten the connection distance L, it is conceivable to reduce the width of the unconnected wiring body. However, due to restrictions such as weakening of the lead frame's mechanical strength, it is not possible to make it very thin. Therefore, in the example shown in FIG. 4, the connection distance L is long, 3.3 mm, and loop sagging is likely to become a problem.

たた、リヌド现線の第二のボンデむング郚で
ある配線電極䜓が暹脂封止䜓の偎面に䜍眮し、
前蚘偎面に蚭けられた暹脂泚入孔から封止暹脂が
泚入される堎合、リヌド现線は暹脂の泚入圧力
の圱響を受けお特にルヌプタレが生じ易い。埓぀
お、これらの芁因が重な぀お配線電極䜓の配線
電極䜓偎でリヌド现線が接続する事故が発生
し、補造歩留を䜎䞋させる䞀因ずな぀おいた。
Further, the wiring electrode body 2, which is the second bonding portion of the thin lead wire 5, is located on the side surface of the resin sealing body,
When the sealing resin is injected from the resin injection hole provided on the side surface, the thin lead wire 5 is particularly susceptible to loop sag due to the influence of the injection pressure of the resin. Therefore, due to the combination of these factors, an accident occurs in which the thin lead wire 5 is connected to the wiring electrode body 2 side of the wiring electrode body 3, which is one of the causes of lowering the manufacturing yield.

ルヌプタレによる短絡䞍良を防止する策ずしお
は、䟋えば、リヌド现線の盎埄を倧きくしお匷床
を増加するこずによりルヌプタレを防止する方法
も考えられるが、金が高䟡であるこず等から、実
甚に適さない。たた、第䞀の電極䜓又は第二の電
極䜓のうち少なくずも䞀方を䞀定の高さだけ高く
する段差加工を行う方法も考えられる。しかし、
段差のあるリヌドフレヌムであるがためにリヌド
フレヌムの取扱いが煩雑化しお生産性が䜎䞋し、
特にボンデむング時のリヌドフレヌムの支持構造
が非平面構造ずな぀お耇雑化する欠点がある。
One possible way to prevent short-circuit failures caused by loop sagging is, for example, by increasing the diameter of the thin lead wire to increase its strength, but this is not suitable for practical use because gold is expensive. . Another possible method is to perform a step process in which at least one of the first electrode body and the second electrode body is raised by a certain height. but,
Because the lead frame has steps, handling of the lead frame becomes complicated and productivity decreases.
In particular, there is a drawback that the supporting structure of the lead frame during bonding becomes a non-planar structure and becomes complicated.

䞊蚘の問題を解決するための手段ずしお、䟋え
ば第䞀の電極䜓ず第二の電極䜓ずの間隔を短く
し、リヌド现線の接続距離を短くする方法が考え
られる。しかし、半導䜓装眮の高集積化に䌎い配
線は耇雑化する傟向にあり、䟋えば、第䞀の電極
䜓ず第二の電極䜓ずの間に配線電極䜓等の第䞉の
電極䜓を蚭ける必芁があ぀た。このような堎合、
第䞀の電極䜓ず第二の電極䜓ずの間隔を短くする
にも限界があ぀た。
As a means for solving the above problem, for example, a method of shortening the distance between the first electrode body and the second electrode body and shortening the connection distance of the thin lead wire can be considered. However, as semiconductor devices become more highly integrated, wiring tends to become more complex. For example, it is necessary to provide a third electrode body such as a wiring electrode body between the first electrode body and the second electrode body. It was hot. In such a case,
There is also a limit to shortening the distance between the first electrode body and the second electrode body.

本考案は、䞊蚘欠点を解消し、リヌド现線の垂
䞋による電気的短絡を防止した絶瞁物封止型半導
䜓装眮を提䟛するこずを目的ずする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an insulator-sealed semiconductor device that eliminates the above-mentioned drawbacks and prevents electrical short circuits due to drooping of thin lead wires.

問題点を解決するための手段 本考案の絶瞁物封止型半導䜓装眮は、第䞀の電
極䜓ず、第二の電極䜓ず、第䞀の電極䜓ず第二の
電極䜓ずの間にリヌドフレヌムの䞀郚ずしお配眮
された第䞉の電極䜓ず、第䞉の電極䜓を跚いで第
䞀の電極䜓ず第二の電極䜓ずを接続するリヌド现
線ず、第䞉の電極䜓の䞀方の䞻面に固着されたチ
ツプ状郚材ずを備えおいる。リヌド现線ず第䞉の
電極䜓が亀差する䜍眮においお、チツプ状郚材の
䞻面がリヌド现線ず第䞉の電極䜓の間に䜍眮す
る。
Means for Solving the Problems The insulator-sealed semiconductor device of the present invention includes a first electrode body, a second electrode body, and a lead between the first electrode body and the second electrode body. A third electrode body disposed as part of the frame, a thin lead wire connecting the first electrode body and the second electrode body across the third electrode body, and a thin lead wire connecting the first electrode body and the second electrode body across the third electrode body; and a chip-like member fixed to the main surface. At the position where the thin lead wire and the third electrode body intersect, the main surface of the chip-like member is located between the thin lead wire and the third electrode body.

チツプ状郚材は、シリコン局ず、シリコン局に
圢成され䞔぀シリコン酞化膜ずしお䞻面を圢成す
る絶瞁局ず、シリコン局に付着され䞔぀第䞉の電
極䜓に固着された金属局ずを有する。
The chip-shaped member includes a silicon layer, an insulating layer formed on the silicon layer and forming a main surface as a silicon oxide film, and a metal layer attached to the silicon layer and fixed to the third electrode body.

䜜 甹 チツプ状郚材はシリコンチツプの酞化及びニツ
ケルメツキ又は半田付けにより圢成できか぀リヌ
ドフレヌムに半導䜓チツプを固着する工皋ず同䞀
の工皋ず内でリヌド现線の盎䞋で第䞉の電極䜓に
固着するこずができるので、チツプ状郚材が増え
おも既存の工皋をそのたた䜿甚できるので、絶瞁
物封止型半導䜓装眮の補造は容易である。
Function: The chip-like member can be formed by oxidizing and nickel plating or soldering a silicon chip, and can be fixed to the third electrode body immediately below the thin lead wire in the same process as the process of fixing the semiconductor chip to the lead frame. Therefore, even if the number of chip-like members increases, the existing process can be used as is, making it easy to manufacture an insulator-sealed semiconductor device.

実斜䟋 以䞋、本考案の実斜䟋を第図〜第図に぀い
お説明する。なお、第図に瀺す埓来䟋ず同様な
郚分は同䞀番号を付し説明を省略する。
Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 3. Incidentally, the same parts as those in the conventional example shown in FIG. 4 are given the same numbers, and the explanation will be omitted.

たず、第図から明らかなように、本考案の実
斜䟋が埓来䟋ず異なる点は配線電極䜓にチツプ
状郚材が茉眮されおいるこず、及びチツプ状郚
材の䞊方においおリヌド现線がパワヌトラン
ゞスタチツプず配線電極䜓ずを接続しおいる
こずである。この堎合、パワヌトランゞスタチツ
プの゚ミツタ電極は第䞀の電極䜓であり、配線
電極䜓は第二の電極䜓であり、配線電極䜓は
第䞉の電極䜓である。第図に瀺すチツプ状郚材
は、シリコンチツプであり、このシリコンチツ
プは、シリコン局ず、シリコン局の䞊面
にシリコン酞化膜ずしお圢成された絶瞁局
ず、シリコン局の䞋面に圢成された金属局
ニツケル局ずを有する。このニツケル局は
配線電極䜓に半田第図等で固着されお
いる。
First, as is clear from FIG. 1, the difference between the embodiment of the present invention and the conventional example is that a chip-like member 6 is placed on the wiring electrode body 3, and a thin lead wire is placed above the chip-like member 6. 5 connects the power transistor chip 4 and the wiring electrode body 2. In this case, the emitter electrode of the power transistor chip 4 is the first electrode body, the wiring electrode body 2 is the second electrode body, and the wiring electrode body 3 is the third electrode body. The chip-like member 6 shown in FIG. 1 is a silicon chip, and this silicon chip consists of a silicon layer 6a and an insulating layer 6b formed as a silicon oxide film on the upper surface of the silicon layer 6a.
and a metal layer 6 formed on the lower surface of the silicon layer 6a.
c (nickel layer). This nickel layer is fixed to the wiring electrode body 3 with solder 7 (FIG. 2) or the like.

絶瞁局を圢成するシリコン酞化膜は他の半
導䜓チツプのシリコン酞化膜の圢成工皋を共甚し
おシリコンり゚ハの熱酞化により容易に圢成する
こずができる。よ぀お異皮の新たな工皋を増加す
るこずなく絶瞁局を圢成するこずができる。
酞化膜は6000Å〜1ÎŒmの厚さで十分な絶瞁耐圧を
埗るこずができる。同様に、前蚘ニツケル局も他
の半導䜓チツプの電極圢成工皋を共甚しおニツケ
ルメツキにより容易に圢成するこずができる。埓
぀お、パワヌトランゞスタチツプを支持電極䜓ぞ
固着する䞀連のダむボンデむング工皋内におい
お、配線電極䜓にチツプ状郚材を半田図瀺せ
ずにお固着できるので、パワヌトランゞスタチ
ツプ等の半導䜓チツプず同等に取扱うこずができ
る。
The silicon oxide film forming the insulating layer 6b can be easily formed by thermal oxidation of a silicon wafer by sharing the process of forming silicon oxide films for other semiconductor chips. Therefore, the insulating layer 6b can be formed without increasing new and different processes.
An oxide film with a thickness of 6000 Å to 1 ÎŒm can provide sufficient dielectric strength. Similarly, the nickel layer can be easily formed by nickel plating by sharing the electrode forming process of other semiconductor chips. Therefore, in a series of die bonding processes for fixing the power transistor chip to the support electrode body, the chip-like member 6 can be fixed to the wiring electrode body with solder (not shown), so that it is possible to bond the chip-like member 6 to the wiring electrode body with solder (not shown). They can be treated equally.

本考案による絶瞁物封止型半導䜓装眮は皮々の
半導䜓装眮に応甚可胜である。䟋えば第図に瀺
す実斜䟋は第図に瀺す暹脂封止型耇合ICに適
甚できる。この暹脂封止型耇合ICはリヌドフレ
ヌムから圢成された電極䜓及び電極䜓を
被芆する暹脂封止䜓ずから成る。電極䜓
は、15本の倖郚リヌドず、倖郚リヌドの
各々に続く配線電極䜓ず、特定の配線電極䜓
の倧面積郚である支持電極䜓ずを有す
る。電極䜓䞭の支持電極䜓の䞀぀には図
瀺の劂くモノリシツクICチツプが固着され、
他の支持電極䜓にはパワヌトランゞスタチツ
プが固着されおいる。぀の配線電極䜓䞊
にはチツプ状郚材が固着されおいる。第図で
は、明確に図瀺するため、チツプ状郚材に斜線
を付す。チツプ状郚材の䞊方に懞架されたリヌ
ド现線はパワヌトランゞスタチツプの゚ミツ
タ電極ず配線電極䜓ずの間を接続しおいる。
この際リヌド现線は非接続である配線電極䜓
を本跚いで接続されおいる。しかしリヌド现
線の盎䞋郚分の非接続配線電極䜓にはチツ
プ状郚材が固着されおおり、これにより非接続
配線電極䜓ずリヌド现線ずの接觊を防止で
きるず共に、非接続配線電極䜓ずリヌド现線
ずの倚重配線を良奜に実珟するこずができる。
The insulator-sealed semiconductor device according to the present invention can be applied to various semiconductor devices. For example, the embodiment shown in FIG. 1 can be applied to the resin-sealed composite IC shown in FIG. This resin-sealed composite IC consists of an electrode body 10 formed from a lead frame and a resin seal 14 that covers the electrode body 10. Electrode body 10
has 15 external leads 11, wiring electrode bodies 12 following each of the external leads 11, and a supporting electrode body 13 which is a large area portion of a particular wiring electrode body 12. As shown in the figure, a monolithic IC chip 15 is fixed to one of the supporting electrode bodies 13 in the electrode body 10.
A power transistor chip 4 is fixed to the other support electrode body 13. A chip-shaped member 6 is fixed onto the two wiring electrode bodies 12. In FIG. 3, the chip-like member 6 is shaded for clarity. A thin lead wire 5 suspended above the chip-like member 6 connects the emitter electrode of the power transistor chip 4 and the wiring electrode body 12.
At this time, the lead thin wire 5 is not connected to the wiring electrode body 1.
2 is connected across one line. However, a chip-like member 6 is fixed to the unconnected wiring electrode body 12 directly below the lead thin wire 5, which prevents contact between the unconnected wiring electrode body 12 and the lead thin wire 5, and Multiple wiring between the body 12 and the thin lead wire 5 can be realized satisfactorily.

本のリヌド现線の各々は䞊方から芋たずき
チツプ状郚材の端郚ずほが盎亀しか぀チツプ状
郚材の䞊面のほが䞭心線近傍を通぀おいる。実
際の絶瞁物封止型耇合ICでは、リヌド现線は
チツプ状郚材に接觊せずこれより䞊方に浮いお
いる堎合もあるが、チツプ状郚材に接觊しおい
るこずもある。以䞊のように本実斜䟋では、第
図に瀺すようにチツプ状郚材を配線電極䜓䞊
に茉眮するこずにより、リヌド现線ず配線電極
䜓間の電気的短絡事故を完党に防止するこずが
できる。換蚀すれば、リヌド现線が自重又は暹
脂泚入圧力によ぀お倧きく垂䞋しおも、チツプ状
郚材がリヌド现線を支持し、配線電極䜓ずの
接觊を防止する。特に第図のように第のボン
デむング郚が暹脂泚入孔の近傍に䜍眮するず
き有効である。たた、チツプ状郚材の絶瞁局
は、十分な絶瞁耐圧を有するシリコン酞化膜で
圢成されるため、絶瞁局の䞊面ず配線電極䜓
間は完党な絶瞁状態にある。埓぀お、リヌド现
線が䜕等かの原因で倧きく垂䞋しおチツプ状郚
材の絶瞁局ず接觊しおも、リヌド现線ず
配線電極䜓間は絶瞁状態に維持されるため、電
気的短絡事故を回避するこずができる。たた、チ
ツプ状郚材は塗垃しお圢成された絶瞁物ずは異
なり配線電極䜓ずの接觊を防止するのに十分な高
さを有するので、リヌド现線の配線電極䜓ぞ
の接觊を有効に防止できるず共に、支持電極䜓
ずの接觊防止効果も同時に埗るこずができる。
Each of the two thin lead wires 5 is substantially orthogonal to the end of the chip-like member 6 when viewed from above, and passes approximately near the center line of the upper surface of the chip-like member 6. In an actual insulator-sealed composite IC, the thin lead wire 5 may float above the chip-like member 6 without contacting it, but it may also come into contact with the chip-like member 6. As described above, in this embodiment, the first
By placing the chip-like member 6 on the wiring electrode body 3 as shown in the figure, it is possible to completely prevent an electrical short circuit accident between the thin lead wire 5 and the wiring electrode body 3. In other words, even if the thin lead wire 5 hangs down significantly due to its own weight or resin injection pressure, the chip-like member 6 supports the thin lead wire 5 and prevents it from coming into contact with the wiring electrode body. This is particularly effective when the second bonding part is located near the resin injection hole 16 as shown in FIG. In addition, the insulating layer 6 of the chip-shaped member 6
Since layer b is formed of a silicon oxide film having sufficient dielectric strength, the upper surface of insulating layer 6b and wiring electrode body 3 are completely insulated. Therefore, even if the thin lead wire 5 hangs down significantly for some reason and comes into contact with the insulating layer 6b of the chip-shaped member 6, the thin lead wire 5 and the wiring electrode body 3 are maintained in an insulated state, so that electrical Short circuit accidents can be avoided. Moreover, unlike an insulator formed by coating, the chip-like member 6 has a height sufficient to prevent contact with the wiring electrode body 3, so that the contact of the thin lead wire 5 with the wiring electrode body 3 is effectively prevented. It is possible to prevent the supporting electrode body 1 from
At the same time, the effect of preventing contact with other objects can also be obtained.

チツプ状郚材はパワヌトランゞスタチツプ
及びモノリシツクICチツプず同䞀のダむボ
ンデむング工皋にお配線電極䜓に固着するこ
ずができるから、チツプ状郚材をリヌドフレヌ
ム䞊に固定するために新たな異皮の工皋を増加す
る必芁はない。なお、第図ではチツプ状郚材
、パワヌトランゞスタチツプ及びモノリシツ
クICチツプを固着する郚分の配線電極䜓
及び支持電極䜓には、予めクリヌム半田
ペヌスト状の半田を印刷によ぀お圢成しおお
き、チツプ状郚材、パワヌトランゞスタチツプ
及びモノリシツクICチツプをクリヌム半
田の粘着力で仮固定し、埌に加熱しお半田を溶融
させる工皋リフロヌ工皋を通しおこれらを固
定する。因に、チツプ状郚材の倧きさの䞀䟋
は、瞊2.3mm×暪1.5mm×厚さ0.3〜0.5mmであり、
パワヌトランゞスタチツプは、瞊1.6mm×暪1.6
mm×厚さ0.3mmであるから、チツプ状郚材を半
導䜓チツプず同等に取扱えるこずが理解されよ
う。
Chip-like member 6 is power transistor chip 4
And since it can be fixed to the wiring electrode body 12 in the same die bonding process as the monolithic IC chip 15, there is no need to add a new and different process to fix the chip-shaped member 6 on the lead frame. In addition, in FIG. 3, the wiring electrode body 1 is shown in the portion where the chip-shaped member 6, the power transistor chip 4, and the monolithic IC chip 15 are fixed.
2 and the supporting electrode body 13 by printing cream solder (paste-like solder) in advance, and temporarily bond the chip-shaped member 6, power transistor chip 4, and monolithic IC chip 15 with the adhesive force of the cream solder. These are then fixed through a process of heating and melting the solder (reflow process). Incidentally, an example of the size of the chip-like member 6 is 2.3 mm long x 1.5 mm wide x 0.3 to 0.5 mm thick.
Power transistor chip 4 is 1.6mm long x 1.6mm wide
It will be understood that since the size is 0.3 mm x 0.3 mm, the chip-shaped member 6 can be handled in the same manner as a semiconductor chip.

ここでチツプの偎面をガラス膜で被芆しおもよ
い。これにより、より完党な絶瞁を埗るこずがで
きる。
Here, the side surfaces of the chip may be covered with a glass film. This allows more complete insulation to be obtained.

本考案の䞊蚘実斜䟋は皮々の倉曎が可胜であ
る。䟋えば、䞊蚘実斜䟋ではシリコンり゚ハずし
おチツプ状郚材の構造を䟋瀺したが、本考案の
チツプ状郚材はこの構造に限定されない。しか
し、前蚘実斜䟋のようにシリコンり゚ハを䜿甚す
るず、別工皋を増加するこずなくチツプ状郚材を
圢成できるので、生産効率の点で有利である。
The above-described embodiments of the present invention can be modified in various ways. For example, in the above embodiment, the structure of the chip-like member 6 is illustrated as a silicon wafer, but the chip-like member 6 of the present invention is not limited to this structure. However, if a silicon wafer is used as in the above embodiment, the chip-like member can be formed without adding another process, which is advantageous in terms of production efficiency.

たた、リヌド现線がパワヌトランゞスタチツプ
等の半導䜓チツプず配線電極䜓ずを接続しおいる
堎合に限られない。即ち、第䞀の電極䜓ず第二の
電極䜓は、リヌドフレヌム、リヌドフレヌムに固
着された回路基板䞊に圢成された電極、リヌドフ
レヌムやプリント基板䞊に固着された半導䜓チツ
プ等の電子玠子の電極等、皮々の電極が察象ずな
る。曎に、チツプ状郚材を固着する䜍眮は配線
電極䜓に限られない。
Further, the present invention is not limited to the case where the thin lead wire connects a semiconductor chip such as a power transistor chip and a wiring electrode body. That is, the first electrode body and the second electrode body are electrodes formed on a lead frame, a circuit board fixed to the lead frame, and an electronic element such as a semiconductor chip fixed on a lead frame or printed circuit board. Various electrodes such as electrodes are targeted. Furthermore, the location where the chip-like member 6 is fixed is not limited to the wiring electrode body.

考案の効果 本考案の絶瞁物封止型半導䜓装眮では、リヌド
现線盎䞋の第䞉の電極䜓にチツプ状郚材が茉眮さ
れおいるため、リヌド现線が倧幅に垂䞋しおもチ
ツプ状郚材がリヌド现線を支持するので、リヌド
现線ず第䞉の電極䜓ずの接觊による電気的短絡事
故を完党に回避するこずができる。たた、チツプ
状郚材は半導䜓チツプの固着ず同䞀の工皋にお第
䞉の電極䜓䞊に茉眮するこずも可胜であり、この
堎合生産効率を実質的に䜎䞋するこずなく、電気
的短絡事故を防止するこずができる。
Effects of the invention In the insulator-sealed semiconductor device of the present invention, the chip-like member is mounted on the third electrode body directly below the thin lead wire, so even if the thin lead wire droops considerably, the chip-like member remains a lead. Since the thin wire is supported, electrical short circuit accidents caused by contact between the thin lead wire and the third electrode body can be completely avoided. In addition, the chip-like member can be placed on the third electrode body in the same process as the fixing of the semiconductor chip, and in this case, electrical short circuit accidents can be avoided without substantially reducing production efficiency. It can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第図は本考案による絶瞁物封止型半導䜓装眮
の実斜䟋を瀺す斜芖図、第図はチツプ状郚材の
拡倧断面図、第図は第図の実斜䟋を応甚した
暹脂封止型耇合ICを瀺す平面図、第図は埓来
䟋を瀺す斜芖図、第図はネむルヘツドボンデむ
ング法によるリヌド现線の接続方法を瀺す工皋図
であり、第図はリヌド现線の先端郚にボヌル
を圢成する状態、第図は第䞀の電極䜓に第䞀
のボンデむング郚を圢成する状態、第図はキ
ダピラリを移動する状態、第図は第二の電極
䜓に第二のボンデむング郚を圢成する状態、第
図はリヌド现線を切断する状態を瀺す。   支持電極䜓、  配線電極䜓第䞀の
電極䜓、  配線電極䜓第䞉の電極䜓、
  パワヌトランゞスタチツプ゚ミツタ電極は
第䞀の電極䜓、  チツプ状郚材、  
シリコン局、  絶瞁局、  金属局。
FIG. 1 is a perspective view showing an embodiment of an insulator-sealed semiconductor device according to the present invention, FIG. 2 is an enlarged cross-sectional view of a chip-like member, and FIG. 3 is a resin-sealed semiconductor device using the embodiment of FIG. FIG. 4 is a perspective view showing a conventional example, FIG. 5 is a process diagram showing a method for connecting thin lead wires using the nail head bonding method, and FIG. 5A is a diagram showing the tip of the thin lead wire. Figure 5B is a state where the first bonding part is formed on the first electrode body, Figure 5C is a state where the capillary is moved, and Figure 5D is a state where the ball is formed on the second electrode body. state of forming the second bonding part, fifth
Figure E shows the state in which the thin lead wire is cut. 1... Supporting electrode body, 2... Wiring electrode body (first electrode body), 3... Wiring electrode body (third electrode body), 4
...Power transistor chip (emitter electrode is the first electrode body), 6... Chip-shaped member, 6a...
Silicon layer, 6b...insulating layer, 6c...metal layer.

Claims (1)

【実甚新案登録請求の範囲】 第䞀の電極䜓ず、第二の電極䜓ず、前蚘第䞀の
電極䜓ず第二の電極䜓ずの間にリヌドフレヌムの
䞀郚ずしお配眮された第䞉の電極䜓ず、該第䞉の
電極䜓を跚いで前蚘第䞀の電極䜓ず第二の電極䜓
ずを接続するリヌド现線ず、前蚘第䞉の電極䜓の
䞀方の䞻面に固着されたチツプ状郚材ずを備え、 前蚘リヌド现線ず前蚘第䞉の電極䜓が亀差する
䜍眮においお、前蚘チツプ状郚材の前蚘䞻面が前
蚘リヌド现線ず前蚘第䞉の電極䜓の間に䜍眮する
絶瞁物封止型半導䜓装眮においお、 前蚘チツプ状郚材は、シリコン局ず、前蚘シリ
コン局に圢成され䞔぀シリコン酞化膜ずしお䞻面
を圢成する絶瞁局ず、前蚘シリコン局に付着され
䞔぀前蚘第䞉の電極䜓に固着された金属局ずを有
するこずを特城ずする絶瞁物封止型半導䜓装眮。
[Claims for Utility Model Registration] A first electrode body, a second electrode body, and a third electrode body disposed as part of a lead frame between the first electrode body and the second electrode body. an electrode body, a thin lead wire connecting the first electrode body and the second electrode body across the third electrode body, and a chip-shaped wire fixed to one main surface of the third electrode body. an insulator-sealed type member, wherein the main surface of the chip-like member is located between the thin lead wire and the third electrode body at a position where the thin lead wire and the third electrode body intersect. In the semiconductor device, the chip-shaped member includes a silicon layer, an insulating layer formed on the silicon layer and forming a main surface as a silicon oxide film, and attached to the silicon layer and fixed to the third electrode body. What is claimed is: 1. An insulator-sealed semiconductor device comprising: a metal layer;
JP1987099366U 1987-06-30 1987-06-30 Expired - Lifetime JPH0546271Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987099366U JPH0546271Y2 (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987099366U JPH0546271Y2 (en) 1987-06-30 1987-06-30

Publications (2)

Publication Number Publication Date
JPS646041U JPS646041U (en) 1989-01-13
JPH0546271Y2 true JPH0546271Y2 (en) 1993-12-03

Family

ID=31326458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987099366U Expired - Lifetime JPH0546271Y2 (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPH0546271Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4618941B2 (en) * 2001-07-24 2011-01-26 䞉掋電機株匏䌚瀟 Semiconductor device
WO2021060161A1 (en) * 2019-09-27 2021-04-01 株匏䌚瀟村田補䜜所 Module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210845A (en) * 1984-04-05 1985-10-23 Toshiba Corp Resin sealed type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210845A (en) * 1984-04-05 1985-10-23 Toshiba Corp Resin sealed type semiconductor device

Also Published As

Publication number Publication date
JPS646041U (en) 1989-01-13

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