JPH0546271Y2 - - Google Patents

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Publication number
JPH0546271Y2
JPH0546271Y2 JP1987099366U JP9936687U JPH0546271Y2 JP H0546271 Y2 JPH0546271 Y2 JP H0546271Y2 JP 1987099366 U JP1987099366 U JP 1987099366U JP 9936687 U JP9936687 U JP 9936687U JP H0546271 Y2 JPH0546271 Y2 JP H0546271Y2
Authority
JP
Japan
Prior art keywords
electrode body
chip
lead wire
thin lead
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987099366U
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Japanese (ja)
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JPS646041U (en
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Priority to JP1987099366U priority Critical patent/JPH0546271Y2/ja
Publication of JPS646041U publication Critical patent/JPS646041U/ja
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Publication of JPH0546271Y2 publication Critical patent/JPH0546271Y2/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案は、2つの電極体をリード細線にて接続
した構造を有する絶縁物封止型半導体装置に関連
する。
[Detailed Description of the Invention] Industrial Application Field The present invention relates to an insulator-sealed semiconductor device having a structure in which two electrode bodies are connected by a thin lead wire.

従来の技術 第4図は、従来の樹脂封止型複合ICの一部を
示す斜視図である。この樹脂封止型複合ICはリ
ードフレームから形成された支持電極体1及び配
線電極体2,3を有し、支持電極体1上にはパワ
ートランジスタチツプ4が半田(図示せず)にて
固着されている。パワートランジスタチツプ4の
上面には複数の電極(ボンデイングパツド)が形
成されているが図示は省略する。ボンデイングパ
ツドには2本のリード細線5が接続されており、
リード細線5は、図示の如く配線電極体3を跨い
で配線電極体2に接続されている。これにより配
線電極体3とリード細線5が多重配線となつてい
る。次に、リード細線の接続方法を第5図につい
て説明する。
Prior Art FIG. 4 is a perspective view showing a part of a conventional resin-sealed composite IC. This resin-sealed composite IC has a supporting electrode body 1 formed from a lead frame and wiring electrode bodies 2 and 3, and a power transistor chip 4 is fixed on the supporting electrode body 1 with solder (not shown). has been done. A plurality of electrodes (bonding pads) are formed on the upper surface of the power transistor chip 4, but are not shown. Two thin lead wires 5 are connected to the bonding pad.
The thin lead wire 5 is connected to the wiring electrode body 2 across the wiring electrode body 3 as shown in the figure. As a result, the wiring electrode body 3 and the thin lead wire 5 form multiple wirings. Next, a method for connecting thin lead wires will be explained with reference to FIG.

まず、第5図Aに示すように、ワイヤボンダの
パイプ状のキヤピラリ50の中心孔51からリー
ド細線52を送り出し、電気スパーク又は水素炎
等でリード細線52の先端部にボール53を形成
する。ボール53の直径は、リード細線52の直
径の2〜3倍程度である。
First, as shown in FIG. 5A, a thin lead wire 52 is sent out from the center hole 51 of a pipe-shaped capillary 50 of a wire bonder, and a ball 53 is formed at the tip of the thin lead wire 52 using an electric spark, a hydrogen flame, or the like. The diameter of the ball 53 is about 2 to 3 times the diameter of the thin lead wire 52.

次に、第5図Bに示すように、第一の電極体5
4にボール53をキヤピラリ50の先端で押し付
け第一のボンデイングを行う。この際、第一の電
極体54は200〜250℃に予め加熱されている。ま
た、キヤピラリ50には、リード細線52の接続
方向と直角な矢印55で示す方向への超音波振動
が加えられている。これにより、第一の電極体5
4にリード細線52が釘頭状に接続された第一の
ボンデイング部52aが形成される。
Next, as shown in FIG. 5B, the first electrode body 5
First bonding is performed by pressing the ball 53 onto the capillary 4 with the tip of the capillary 50. At this time, the first electrode body 54 is preheated to 200 to 250°C. Further, ultrasonic vibration is applied to the capillary 50 in the direction indicated by an arrow 55 perpendicular to the connection direction of the thin lead wire 52. As a result, the first electrode body 5
4 is formed with a first bonding portion 52a to which a thin lead wire 52 is connected like a nail head.

続いて、第5図Cに示すように、キヤピラリ5
0を上昇して大きく引き回すようにして、リード
細線52を繰り出しながら第二の電極体56に向
かつてキヤピラリ50を移動する。
Next, as shown in FIG. 5C, the capillary 5
The capillary 50 is moved toward the second electrode body 56 while letting out the thin lead wire 52 by raising the capillary 50 and drawing it widely.

その後、第5図Dに示すように、第二の電極体
56に第二のボンデイングを行う。即ち、第二の
電極体56は前述と同様に200〜250℃に予め加熱
され、キヤピラリ50には前述と同様の超音波振
動が加えられている。この状態で、第二の電極体
56に対し径方向にリード細線52を押圧するこ
とにより、リード細線52と第二の電極体56と
が接続され、第二のボンデイング部52bが形成
される。なお、第5図B,Dの工程を電極体の加
熱のみによる熱圧着法又は超音波振動による加熱
のみの超音波法等で行つてもよい。
Thereafter, as shown in FIG. 5D, second bonding is performed on the second electrode body 56. That is, the second electrode body 56 is preheated to 200 to 250° C. as described above, and the same ultrasonic vibration as described above is applied to the capillary 50. In this state, by pressing the thin lead wire 52 against the second electrode body 56 in the radial direction, the thin lead wire 52 and the second electrode body 56 are connected, and a second bonding portion 52b is formed. Note that the steps shown in FIGS. 5B and 5D may be performed by a thermocompression bonding method using only heating of the electrode body or an ultrasonic method using only heating using ultrasonic vibration.

最終的には、第5図Eのように、キヤピラリ5
0を一定の高さまで上昇した後、クランプでリー
ド細線52を押さえつつ更にキヤピラリ50を上
昇させてリード細線52を切断する。狭義には、
第一のボンデイングをネイルヘツドボンデイン
グ、第二のボンデイングをステイツチボンデイン
グと呼称するが、ここではそれら2つを総称して
ネイルヘツドボンデイング法とする。第5図Dに
示すように、第一のボンデイング側では、第一の
電極体に対するリード細線52の角度αはほぼ直
角となり、上を跨るリード細線52と第一の電極
体との距離は長くなる。一方、第二のボンデイン
グ側では、リード細線52の第二の電極体に対す
る角度θは鋭角となり、上を跨るリード細線52
と第二の電極体との距離は短くなる。
Finally, connect the capillary 5 as shown in Figure 5E.
0 to a certain height, the capillary 50 is further raised while holding the thin lead wire 52 with a clamp, and the thin lead wire 52 is cut. In a narrow sense,
The first bonding method is called nail head bonding, and the second bonding method is called static bonding, but here they are collectively referred to as the nail head bonding method. As shown in FIG. 5D, on the first bonding side, the angle α of the thin lead wire 52 with respect to the first electrode body is almost a right angle, and the distance between the thin lead wire 52 that straddles above and the first electrode body is long. Become. On the other hand, on the second bonding side, the angle θ of the thin lead wire 52 with respect to the second electrode body is an acute angle, and the thin lead wire 52 spanning over
The distance between the electrode body and the second electrode body becomes shorter.

考案が解決しようとする問題点 従来ではリード細線の垂下により配線電極体に
リード細線が接触し、短絡不良の原因となつてい
た。即ち、第4図に示すように、配線電極体3を
跨いでリード細線5が接続されている。半導体装
置の高集積化の要求により配線が一層複雑化する
傾向にある。このため配線電極体を跨ぐ接続を行
わなければならないことが多い。
Problems to be Solved by the Invention In the past, the thin lead wires came into contact with the wiring electrode body due to the thin lead wires hanging down, causing short-circuit failures. That is, as shown in FIG. 4, a thin lead wire 5 is connected across the wiring electrode body 3. Due to the demand for higher integration of semiconductor devices, wiring tends to become more complex. For this reason, it is often necessary to make a connection across the wiring electrode body.

ところで、第一の電極体であるパワートランジ
スタチツプ4上の電極と第二の電極体である配線
電極体2との間に第三の電極体として形成された
配線電極体3は、リード細線5に対しては非接続
配線体となつている。このため、リード細線5は
ワイヤボンデイングの際に大きく孤を描くように
接続して、リード細線5と配線電極体3との間の
距離をできるだけ取るようにしている。リード細
線5は、前述のネイルヘツドボンデイング法によ
り、第一のボンデイング部ではパワートランジス
タチツプ4に接続され、第二のボンデイング部で
は配線電極体2に接続されている。また、第一の
ボンデイング部は第二のボンデイング部よりおよ
そパワートランジスタチツプ4の厚さ分だけ高い
位置となつている。このため、配線電極体3は、
支持電極体1側ではリード細線5との距離が長く
なるが、配線電極体2側ではリード細線5との距
離が短くなる。
By the way, the wiring electrode body 3 formed as a third electrode body between the electrode on the power transistor chip 4 which is the first electrode body and the wiring electrode body 2 which is the second electrode body is connected to the thin lead wire 5. It is a non-connected wiring body. For this reason, the thin lead wires 5 are connected in a large arc during wire bonding, so that the distance between the thin lead wires 5 and the wiring electrode body 3 is maintained as much as possible. The thin lead wire 5 is connected to the power transistor chip 4 at the first bonding part and to the wiring electrode body 2 at the second bonding part by the above-mentioned nail head bonding method. Further, the first bonding portion is located at a position higher than the second bonding portion by approximately the thickness of the power transistor chip 4. Therefore, the wiring electrode body 3 is
On the supporting electrode body 1 side, the distance to the thin lead wire 5 becomes long, but on the wiring electrode body 2 side, the distance to the thin lead wire 5 becomes short.

通常使用される直径約30μmの金製のリード細
線は細くかつ柔らかいため、十分な強度を期待で
きないのが実情である。例えば、第一の電極体と
第二の電極体とを接続する金製のリード細線は、
トランスフアモールド時の樹脂注入圧力を自重等
により懸垂状に垂下するループタレを発生するこ
とがあつた。通常、直径が25〜30μmの金製のリ
ード細線では、接続距離Lは3mmが限界とされ
る。接続距離Lが3mmを越えると、自重によりル
ープタレが発生する。実際には、トランスフアモ
ールド時の樹脂注入圧力を考慮しなければならな
いから、実用的な接続距離Lの長さは更に短くな
る。接続距離Lを短くするには非接続配線体の幅
を細くすることが考えられる。しかし、リードフ
レームの機械的強度が弱まる等の制約により、あ
まり細くすることはできない。よつて、第4図の
例では接続距離L=3.3mmと長くなり、ループタ
レが問題になり易い状態にある。
The reality is that the normally used fine gold lead wire with a diameter of about 30 μm is thin and soft, so it cannot be expected to have sufficient strength. For example, the thin gold lead wire connecting the first electrode body and the second electrode body is
During transfer molding, resin injection pressure sometimes caused loop sagging due to its own weight. Normally, for a thin gold lead wire with a diameter of 25 to 30 μm, the connection distance L is limited to 3 mm. If the connection distance L exceeds 3 mm, loop sag will occur due to its own weight. In reality, since the resin injection pressure during transfer molding must be taken into account, the practical length of the connection distance L becomes even shorter. In order to shorten the connection distance L, it is conceivable to reduce the width of the unconnected wiring body. However, due to restrictions such as weakening of the lead frame's mechanical strength, it is not possible to make it very thin. Therefore, in the example shown in FIG. 4, the connection distance L is long, 3.3 mm, and loop sagging is likely to become a problem.

また、リード細線5の第二のボンデイング部で
ある配線電極体2が樹脂封止体の側面に位置し、
前記側面に設けられた樹脂注入孔から封止樹脂が
注入される場合、リード細線5は樹脂の注入圧力
の影響を受けて特にループタレが生じ易い。従つ
て、これらの要因が重なつて配線電極体3の配線
電極体2側でリード細線5が接続する事故が発生
し、製造歩留を低下させる一因となつていた。
Further, the wiring electrode body 2, which is the second bonding portion of the thin lead wire 5, is located on the side surface of the resin sealing body,
When the sealing resin is injected from the resin injection hole provided on the side surface, the thin lead wire 5 is particularly susceptible to loop sag due to the influence of the injection pressure of the resin. Therefore, due to the combination of these factors, an accident occurs in which the thin lead wire 5 is connected to the wiring electrode body 2 side of the wiring electrode body 3, which is one of the causes of lowering the manufacturing yield.

ループタレによる短絡不良を防止する策として
は、例えば、リード細線の直径を大きくして強度
を増加することによりループタレを防止する方法
も考えられるが、金が高価であること等から、実
用に適さない。また、第一の電極体又は第二の電
極体のうち少なくとも一方を一定の高さだけ高く
する段差加工を行う方法も考えられる。しかし、
段差のあるリードフレームであるがためにリード
フレームの取扱いが煩雑化して生産性が低下し、
特にボンデイング時のリードフレームの支持構造
が非平面構造となつて複雑化する欠点がある。
One possible way to prevent short-circuit failures caused by loop sagging is, for example, by increasing the diameter of the thin lead wire to increase its strength, but this is not suitable for practical use because gold is expensive. . Another possible method is to perform a step process in which at least one of the first electrode body and the second electrode body is raised by a certain height. but,
Because the lead frame has steps, handling of the lead frame becomes complicated and productivity decreases.
In particular, there is a drawback that the supporting structure of the lead frame during bonding becomes a non-planar structure and becomes complicated.

上記の問題を解決するための手段として、例え
ば第一の電極体と第二の電極体との間隔を短く
し、リード細線の接続距離を短くする方法が考え
られる。しかし、半導体装置の高集積化に伴い配
線は複雑化する傾向にあり、例えば、第一の電極
体と第二の電極体との間に配線電極体等の第三の
電極体を設ける必要があつた。このような場合、
第一の電極体と第二の電極体との間隔を短くする
にも限界があつた。
As a means for solving the above problem, for example, a method of shortening the distance between the first electrode body and the second electrode body and shortening the connection distance of the thin lead wire can be considered. However, as semiconductor devices become more highly integrated, wiring tends to become more complex. For example, it is necessary to provide a third electrode body such as a wiring electrode body between the first electrode body and the second electrode body. It was hot. In such a case,
There is also a limit to shortening the distance between the first electrode body and the second electrode body.

本考案は、上記欠点を解消し、リード細線の垂
下による電気的短絡を防止した絶縁物封止型半導
体装置を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an insulator-sealed semiconductor device that eliminates the above-mentioned drawbacks and prevents electrical short circuits due to drooping of thin lead wires.

問題点を解決するための手段 本考案の絶縁物封止型半導体装置は、第一の電
極体と、第二の電極体と、第一の電極体と第二の
電極体との間にリードフレームの一部として配置
された第三の電極体と、第三の電極体を跨いで第
一の電極体と第二の電極体とを接続するリード細
線と、第三の電極体の一方の主面に固着されたチ
ツプ状部材とを備えている。リード細線と第三の
電極体が交差する位置において、チツプ状部材の
主面がリード細線と第三の電極体の間に位置す
る。
Means for Solving the Problems The insulator-sealed semiconductor device of the present invention includes a first electrode body, a second electrode body, and a lead between the first electrode body and the second electrode body. A third electrode body disposed as part of the frame, a thin lead wire connecting the first electrode body and the second electrode body across the third electrode body, and a thin lead wire connecting the first electrode body and the second electrode body across the third electrode body; and a chip-like member fixed to the main surface. At the position where the thin lead wire and the third electrode body intersect, the main surface of the chip-like member is located between the thin lead wire and the third electrode body.

チツプ状部材は、シリコン層と、シリコン層に
形成され且つシリコン酸化膜として主面を形成す
る絶縁層と、シリコン層に付着され且つ第三の電
極体に固着された金属層とを有する。
The chip-shaped member includes a silicon layer, an insulating layer formed on the silicon layer and forming a main surface as a silicon oxide film, and a metal layer attached to the silicon layer and fixed to the third electrode body.

作 用 チツプ状部材はシリコンチツプの酸化及びニツ
ケルメツキ又は半田付けにより形成できかつリー
ドフレームに半導体チツプを固着する工程と同一
の工程と内でリード細線の直下で第三の電極体に
固着することができるので、チツプ状部材が増え
ても既存の工程をそのまま使用できるので、絶縁
物封止型半導体装置の製造は容易である。
Function: The chip-like member can be formed by oxidizing and nickel plating or soldering a silicon chip, and can be fixed to the third electrode body immediately below the thin lead wire in the same process as the process of fixing the semiconductor chip to the lead frame. Therefore, even if the number of chip-like members increases, the existing process can be used as is, making it easy to manufacture an insulator-sealed semiconductor device.

実施例 以下、本考案の実施例を第1図〜第3図につい
て説明する。なお、第4図に示す従来例と同様な
部分は同一番号を付し説明を省略する。
Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 3. Incidentally, the same parts as those in the conventional example shown in FIG. 4 are given the same numbers, and the explanation will be omitted.

まず、第1図から明らかなように、本考案の実
施例が従来例と異なる点は配線電極体3にチツプ
状部材6が載置されていること、及びチツプ状部
材6の上方においてリード細線5がパワートラン
ジスタチツプ4と配線電極体2とを接続している
ことである。この場合、パワートランジスタチツ
プ4のエミツタ電極は第一の電極体であり、配線
電極体2は第二の電極体であり、配線電極体3は
第三の電極体である。第1図に示すチツプ状部材
6は、シリコンチツプであり、このシリコンチツ
プは、シリコン層6aと、シリコン層6aの上面
にシリコン酸化膜として形成された絶縁層6b
と、シリコン層6aの下面に形成された金属層6
c(ニツケル層)とを有する。このニツケル層は
配線電極体3に半田7(第2図)等で固着されて
いる。
First, as is clear from FIG. 1, the difference between the embodiment of the present invention and the conventional example is that a chip-like member 6 is placed on the wiring electrode body 3, and a thin lead wire is placed above the chip-like member 6. 5 connects the power transistor chip 4 and the wiring electrode body 2. In this case, the emitter electrode of the power transistor chip 4 is the first electrode body, the wiring electrode body 2 is the second electrode body, and the wiring electrode body 3 is the third electrode body. The chip-like member 6 shown in FIG. 1 is a silicon chip, and this silicon chip consists of a silicon layer 6a and an insulating layer 6b formed as a silicon oxide film on the upper surface of the silicon layer 6a.
and a metal layer 6 formed on the lower surface of the silicon layer 6a.
c (nickel layer). This nickel layer is fixed to the wiring electrode body 3 with solder 7 (FIG. 2) or the like.

絶縁層6bを形成するシリコン酸化膜は他の半
導体チツプのシリコン酸化膜の形成工程を共用し
てシリコンウエハの熱酸化により容易に形成する
ことができる。よつて異種の新たな工程を増加す
ることなく絶縁層6bを形成することができる。
酸化膜は6000Å〜1μmの厚さで十分な絶縁耐圧を
得ることができる。同様に、前記ニツケル層も他
の半導体チツプの電極形成工程を共用してニツケ
ルメツキにより容易に形成することができる。従
つて、パワートランジスタチツプを支持電極体へ
固着する一連のダイボンデイング工程内におい
て、配線電極体にチツプ状部材6を半田(図示せ
ず)にて固着できるので、パワートランジスタチ
ツプ等の半導体チツプと同等に取扱うことができ
る。
The silicon oxide film forming the insulating layer 6b can be easily formed by thermal oxidation of a silicon wafer by sharing the process of forming silicon oxide films for other semiconductor chips. Therefore, the insulating layer 6b can be formed without increasing new and different processes.
An oxide film with a thickness of 6000 Å to 1 μm can provide sufficient dielectric strength. Similarly, the nickel layer can be easily formed by nickel plating by sharing the electrode forming process of other semiconductor chips. Therefore, in a series of die bonding processes for fixing the power transistor chip to the support electrode body, the chip-like member 6 can be fixed to the wiring electrode body with solder (not shown), so that it is possible to bond the chip-like member 6 to the wiring electrode body with solder (not shown). They can be treated equally.

本考案による絶縁物封止型半導体装置は種々の
半導体装置に応用可能である。例えば第1図に示
す実施例は第3図に示す樹脂封止型複合ICに適
用できる。この樹脂封止型複合ICはリードフレ
ームから形成された電極体10及び電極体10を
被覆する樹脂封止体14とから成る。電極体10
は、15本の外部リード11と、外部リード11の
各々に続く配線電極体12と、特定の配線電極体
12の大面積部である支持電極体13とを有す
る。電極体10中の支持電極体13の一つには図
示の如くモノリシツクICチツプ15が固着され、
他の支持電極体13にはパワートランジスタチツ
プ4が固着されている。2つの配線電極体12上
にはチツプ状部材6が固着されている。第3図で
は、明確に図示するため、チツプ状部材6に斜線
を付す。チツプ状部材6の上方に懸架されたリー
ド細線5はパワートランジスタチツプ4のエミツ
タ電極と配線電極体12との間を接続している。
この際リード細線5は非接続である配線電極体1
2を1本跨いで接続されている。しかしリード細
線5の直下部分の非接続配線電極体12にはチツ
プ状部材6が固着されており、これにより非接続
配線電極体12とリード細線5との接触を防止で
きると共に、非接続配線電極体12とリード細線
5との多重配線を良好に実現することができる。
The insulator-sealed semiconductor device according to the present invention can be applied to various semiconductor devices. For example, the embodiment shown in FIG. 1 can be applied to the resin-sealed composite IC shown in FIG. This resin-sealed composite IC consists of an electrode body 10 formed from a lead frame and a resin seal 14 that covers the electrode body 10. Electrode body 10
has 15 external leads 11, wiring electrode bodies 12 following each of the external leads 11, and a supporting electrode body 13 which is a large area portion of a particular wiring electrode body 12. As shown in the figure, a monolithic IC chip 15 is fixed to one of the supporting electrode bodies 13 in the electrode body 10.
A power transistor chip 4 is fixed to the other support electrode body 13. A chip-shaped member 6 is fixed onto the two wiring electrode bodies 12. In FIG. 3, the chip-like member 6 is shaded for clarity. A thin lead wire 5 suspended above the chip-like member 6 connects the emitter electrode of the power transistor chip 4 and the wiring electrode body 12.
At this time, the lead thin wire 5 is not connected to the wiring electrode body 1.
2 is connected across one line. However, a chip-like member 6 is fixed to the unconnected wiring electrode body 12 directly below the lead thin wire 5, which prevents contact between the unconnected wiring electrode body 12 and the lead thin wire 5, and Multiple wiring between the body 12 and the thin lead wire 5 can be realized satisfactorily.

2本のリード細線5の各々は上方から見たとき
チツプ状部材6の端部とほぼ直交しかつチツプ状
部材6の上面のほぼ中心線近傍を通つている。実
際の絶縁物封止型複合ICでは、リード細線5は
チツプ状部材6に接触せずこれより上方に浮いて
いる場合もあるが、チツプ状部材6に接触してい
ることもある。以上のように本実施例では、第1
図に示すようにチツプ状部材6を配線電極体3上
に載置することにより、リード細線5と配線電極
体3間の電気的短絡事故を完全に防止することが
できる。換言すれば、リード細線5が自重又は樹
脂注入圧力によつて大きく垂下しても、チツプ状
部材6がリード細線5を支持し、配線電極体との
接触を防止する。特に第3図のように第2のボン
デイング部が樹脂注入孔16の近傍に位置すると
き有効である。また、チツプ状部材6の絶縁層6
bは、十分な絶縁耐圧を有するシリコン酸化膜で
形成されるため、絶縁層6bの上面と配線電極体
3間は完全な絶縁状態にある。従つて、リード細
線5が何等かの原因で大きく垂下してチツプ状部
材6の絶縁層6bと接触しても、リード細線5と
配線電極体3間は絶縁状態に維持されるため、電
気的短絡事故を回避することができる。また、チ
ツプ状部材6は塗布して形成された絶縁物とは異
なり配線電極体との接触を防止するのに十分な高
さを有するので、リード細線5の配線電極体3へ
の接触を有効に防止できると共に、支持電極体1
との接触防止効果も同時に得ることができる。
Each of the two thin lead wires 5 is substantially orthogonal to the end of the chip-like member 6 when viewed from above, and passes approximately near the center line of the upper surface of the chip-like member 6. In an actual insulator-sealed composite IC, the thin lead wire 5 may float above the chip-like member 6 without contacting it, but it may also come into contact with the chip-like member 6. As described above, in this embodiment, the first
By placing the chip-like member 6 on the wiring electrode body 3 as shown in the figure, it is possible to completely prevent an electrical short circuit accident between the thin lead wire 5 and the wiring electrode body 3. In other words, even if the thin lead wire 5 hangs down significantly due to its own weight or resin injection pressure, the chip-like member 6 supports the thin lead wire 5 and prevents it from coming into contact with the wiring electrode body. This is particularly effective when the second bonding part is located near the resin injection hole 16 as shown in FIG. In addition, the insulating layer 6 of the chip-shaped member 6
Since layer b is formed of a silicon oxide film having sufficient dielectric strength, the upper surface of insulating layer 6b and wiring electrode body 3 are completely insulated. Therefore, even if the thin lead wire 5 hangs down significantly for some reason and comes into contact with the insulating layer 6b of the chip-shaped member 6, the thin lead wire 5 and the wiring electrode body 3 are maintained in an insulated state, so that electrical Short circuit accidents can be avoided. Moreover, unlike an insulator formed by coating, the chip-like member 6 has a height sufficient to prevent contact with the wiring electrode body 3, so that the contact of the thin lead wire 5 with the wiring electrode body 3 is effectively prevented. It is possible to prevent the supporting electrode body 1 from
At the same time, the effect of preventing contact with other objects can also be obtained.

チツプ状部材6はパワートランジスタチツプ4
及びモノリシツクICチツプ15と同一のダイボ
ンデイング工程にて配線電極体12に固着するこ
とができるから、チツプ状部材6をリードフレー
ム上に固定するために新たな異種の工程を増加す
る必要はない。なお、第3図ではチツプ状部材
6、パワートランジスタチツプ4及びモノリシツ
クICチツプ15を固着する部分の配線電極体1
2及び支持電極体13には、予めクリーム半田
(ペースト状の半田)を印刷によつて形成してお
き、チツプ状部材6、パワートランジスタチツプ
4及びモノリシツクICチツプ15をクリーム半
田の粘着力で仮固定し、後に加熱して半田を溶融
させる工程(リフロー工程)を通してこれらを固
定する。因に、チツプ状部材6の大きさの一例
は、縦2.3mm×横1.5mm×厚さ0.3〜0.5mmであり、
パワートランジスタチツプ4は、縦1.6mm×横1.6
mm×厚さ0.3mmであるから、チツプ状部材6を半
導体チツプと同等に取扱えることが理解されよ
う。
Chip-like member 6 is power transistor chip 4
And since it can be fixed to the wiring electrode body 12 in the same die bonding process as the monolithic IC chip 15, there is no need to add a new and different process to fix the chip-shaped member 6 on the lead frame. In addition, in FIG. 3, the wiring electrode body 1 is shown in the portion where the chip-shaped member 6, the power transistor chip 4, and the monolithic IC chip 15 are fixed.
2 and the supporting electrode body 13 by printing cream solder (paste-like solder) in advance, and temporarily bond the chip-shaped member 6, power transistor chip 4, and monolithic IC chip 15 with the adhesive force of the cream solder. These are then fixed through a process of heating and melting the solder (reflow process). Incidentally, an example of the size of the chip-like member 6 is 2.3 mm long x 1.5 mm wide x 0.3 to 0.5 mm thick.
Power transistor chip 4 is 1.6mm long x 1.6mm wide
It will be understood that since the size is 0.3 mm x 0.3 mm, the chip-shaped member 6 can be handled in the same manner as a semiconductor chip.

ここでチツプの側面をガラス膜で被覆してもよ
い。これにより、より完全な絶縁を得ることがで
きる。
Here, the side surfaces of the chip may be covered with a glass film. This allows more complete insulation to be obtained.

本考案の上記実施例は種々の変更が可能であ
る。例えば、上記実施例ではシリコンウエハとし
てチツプ状部材6の構造を例示したが、本考案の
チツプ状部材6はこの構造に限定されない。しか
し、前記実施例のようにシリコンウエハを使用す
ると、別工程を増加することなくチツプ状部材を
形成できるので、生産効率の点で有利である。
The above-described embodiments of the present invention can be modified in various ways. For example, in the above embodiment, the structure of the chip-like member 6 is illustrated as a silicon wafer, but the chip-like member 6 of the present invention is not limited to this structure. However, if a silicon wafer is used as in the above embodiment, the chip-like member can be formed without adding another process, which is advantageous in terms of production efficiency.

また、リード細線がパワートランジスタチツプ
等の半導体チツプと配線電極体とを接続している
場合に限られない。即ち、第一の電極体と第二の
電極体は、リードフレーム、リードフレームに固
着された回路基板上に形成された電極、リードフ
レームやプリント基板上に固着された半導体チツ
プ等の電子素子の電極等、種々の電極が対象とな
る。更に、チツプ状部材6を固着する位置は配線
電極体に限られない。
Further, the present invention is not limited to the case where the thin lead wire connects a semiconductor chip such as a power transistor chip and a wiring electrode body. That is, the first electrode body and the second electrode body are electrodes formed on a lead frame, a circuit board fixed to the lead frame, and an electronic element such as a semiconductor chip fixed on a lead frame or printed circuit board. Various electrodes such as electrodes are targeted. Furthermore, the location where the chip-like member 6 is fixed is not limited to the wiring electrode body.

考案の効果 本考案の絶縁物封止型半導体装置では、リード
細線直下の第三の電極体にチツプ状部材が載置さ
れているため、リード細線が大幅に垂下してもチ
ツプ状部材がリード細線を支持するので、リード
細線と第三の電極体との接触による電気的短絡事
故を完全に回避することができる。また、チツプ
状部材は半導体チツプの固着と同一の工程にて第
三の電極体上に載置することも可能であり、この
場合生産効率を実質的に低下することなく、電気
的短絡事故を防止することができる。
Effects of the invention In the insulator-sealed semiconductor device of the present invention, the chip-like member is mounted on the third electrode body directly below the thin lead wire, so even if the thin lead wire droops considerably, the chip-like member remains a lead. Since the thin wire is supported, electrical short circuit accidents caused by contact between the thin lead wire and the third electrode body can be completely avoided. In addition, the chip-like member can be placed on the third electrode body in the same process as the fixing of the semiconductor chip, and in this case, electrical short circuit accidents can be avoided without substantially reducing production efficiency. It can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による絶縁物封止型半導体装置
の実施例を示す斜視図、第2図はチツプ状部材の
拡大断面図、第3図は第1図の実施例を応用した
樹脂封止型複合ICを示す平面図、第4図は従来
例を示す斜視図、第5図はネイルヘツドボンデイ
ング法によるリード細線の接続方法を示す工程図
であり、第5図Aはリード細線の先端部にボール
を形成する状態、第5図Bは第一の電極体に第一
のボンデイング部を形成する状態、第5図Cはキ
ヤピラリを移動する状態、第5図Dは第二の電極
体に第二のボンデイング部を形成する状態、第5
図Eはリード細線を切断する状態を示す。 1……支持電極体、2……配線電極体(第一の
電極体)、3……配線電極体(第三の電極体)、4
……パワートランジスタチツプ(エミツタ電極は
第一の電極体)、6……チツプ状部材、6a……
シリコン層、6b……絶縁層、6c……金属層。
FIG. 1 is a perspective view showing an embodiment of an insulator-sealed semiconductor device according to the present invention, FIG. 2 is an enlarged cross-sectional view of a chip-like member, and FIG. 3 is a resin-sealed semiconductor device using the embodiment of FIG. FIG. 4 is a perspective view showing a conventional example, FIG. 5 is a process diagram showing a method for connecting thin lead wires using the nail head bonding method, and FIG. 5A is a diagram showing the tip of the thin lead wire. Figure 5B is a state where the first bonding part is formed on the first electrode body, Figure 5C is a state where the capillary is moved, and Figure 5D is a state where the ball is formed on the second electrode body. state of forming the second bonding part, fifth
Figure E shows the state in which the thin lead wire is cut. 1... Supporting electrode body, 2... Wiring electrode body (first electrode body), 3... Wiring electrode body (third electrode body), 4
...Power transistor chip (emitter electrode is the first electrode body), 6... Chip-shaped member, 6a...
Silicon layer, 6b...insulating layer, 6c...metal layer.

Claims (1)

【実用新案登録請求の範囲】 第一の電極体と、第二の電極体と、前記第一の
電極体と第二の電極体との間にリードフレームの
一部として配置された第三の電極体と、該第三の
電極体を跨いで前記第一の電極体と第二の電極体
とを接続するリード細線と、前記第三の電極体の
一方の主面に固着されたチツプ状部材とを備え、 前記リード細線と前記第三の電極体が交差する
位置において、前記チツプ状部材の前記主面が前
記リード細線と前記第三の電極体の間に位置する
絶縁物封止型半導体装置において、 前記チツプ状部材は、シリコン層と、前記シリ
コン層に形成され且つシリコン酸化膜として主面
を形成する絶縁層と、前記シリコン層に付着され
且つ前記第三の電極体に固着された金属層とを有
することを特徴とする絶縁物封止型半導体装置。
[Claims for Utility Model Registration] A first electrode body, a second electrode body, and a third electrode body disposed as part of a lead frame between the first electrode body and the second electrode body. an electrode body, a thin lead wire connecting the first electrode body and the second electrode body across the third electrode body, and a chip-shaped wire fixed to one main surface of the third electrode body. an insulator-sealed type member, wherein the main surface of the chip-like member is located between the thin lead wire and the third electrode body at a position where the thin lead wire and the third electrode body intersect. In the semiconductor device, the chip-shaped member includes a silicon layer, an insulating layer formed on the silicon layer and forming a main surface as a silicon oxide film, and attached to the silicon layer and fixed to the third electrode body. What is claimed is: 1. An insulator-sealed semiconductor device comprising: a metal layer;
JP1987099366U 1987-06-30 1987-06-30 Expired - Lifetime JPH0546271Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987099366U JPH0546271Y2 (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987099366U JPH0546271Y2 (en) 1987-06-30 1987-06-30

Publications (2)

Publication Number Publication Date
JPS646041U JPS646041U (en) 1989-01-13
JPH0546271Y2 true JPH0546271Y2 (en) 1993-12-03

Family

ID=31326458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987099366U Expired - Lifetime JPH0546271Y2 (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPH0546271Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4618941B2 (en) * 2001-07-24 2011-01-26 三洋電機株式会社 Semiconductor device
CN114521290A (en) * 2019-09-27 2022-05-20 株式会社村田制作所 Module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210845A (en) * 1984-04-05 1985-10-23 Toshiba Corp Resin sealed type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60210845A (en) * 1984-04-05 1985-10-23 Toshiba Corp Resin sealed type semiconductor device

Also Published As

Publication number Publication date
JPS646041U (en) 1989-01-13

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