JPS6153738A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6153738A
JPS6153738A JP59174978A JP17497884A JPS6153738A JP S6153738 A JPS6153738 A JP S6153738A JP 59174978 A JP59174978 A JP 59174978A JP 17497884 A JP17497884 A JP 17497884A JP S6153738 A JPS6153738 A JP S6153738A
Authority
JP
Japan
Prior art keywords
wire
lead
semiconductor chip
bonding
capillary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59174978A
Other languages
Japanese (ja)
Inventor
Kenichi Kaburagi
鏑木　健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP59174978A priority Critical patent/JPS6153738A/en
Publication of JPS6153738A publication Critical patent/JPS6153738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

PURPOSE:To prevent undesired contact with flow of wire and eliminate restriction on layout by connecting a semiconductor chip and inner lead with a wire material coated with insulator. CONSTITUTION:An Au lead 2 coated with resin 3 is held to a capillary 1 of a bonding apparatus. This capillary 1 is moved donward to the position of terminal 6 of semiconductor chip 5 attached on the tab 4 and a gold ball 2a and terminal 6 are bonded. Next, the capillary 1 is moved to the specified position on the inner lead 11 and is then moved downward. The coating at the contact surface with Au lead 2 is fused by thermal bonding and application of ultrasonic wave and thereby a part of Au lead 2 and the specified position of lead 11 are bonded by a hydrogen torch. When the wire is bonded to many terminals 6 of semiconductor chip 5, unwanted contact due to flow of wire can be prevented by the coating 3 and restriction on layout can be eliminated.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体集積回路の如き多数の外部接続端子を有
する半導体装置に関し、特にクロスボンディングを必要
とする際に用いて好適なものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device having a large number of external connection terminals, such as a semiconductor integrated circuit, and is particularly suitable for use when cross bonding is required.

〔背景技術〕[Background technology]

特開昭５７−１９４５６０号「リードフレーム」には、
半導体装置において任意のリードにボンディングされた
ボンディング鋼線が樹脂封止の際ワイヤー流れを起こし
、その隣りの内部リード先端部に接触し、短絡不良を引
き起こ−ｒことが開示されている。JP-A No. 57-194560 "Lead frame"
It is disclosed that a bonding steel wire bonded to an arbitrary lead in a semiconductor device causes the wire to flow during resin sealing and comes into contact with the tip of an adjacent internal lead, causing a short circuit failure.

一方、近年に至り、半導体集積回路の集積度が著しく向
上し、半導体チップとリードとの接続が必らずしも最短
距離で行えるとは限らず、ワイヤーを重ねて配線しなけ
ればならない事態も増えつつある。しかし、本発明者の
検討によると、現状の如くはだか線を用いた半導体装置
では上記ワイヤー流れによってワイヤーとタブとの接触
も多発し、ワイヤーを重ねて配線するといった、いわゆ
るクロスボンディングは各ワイヤー間の接触事故が多く
好ましくないことが明らかになった。On the other hand, in recent years, the degree of integration of semiconductor integrated circuits has improved significantly, and it is not always possible to connect semiconductor chips and leads over the shortest distance, and sometimes wires must be overlapped. It is increasing. However, according to the inventor's study, in the current semiconductor device using bare wires, contact between wires and tabs occurs frequently due to the wire flow, and so-called cross bonding, in which wires are overlapped, is difficult to connect between each wire. It has become clear that there are many contact accidents, which is not desirable.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、半導体チップとインナーリードとを例
えば樹脂コーティングしたＡｕ線を用いて行ない、ワイ
ヤー流れによる不所望な接触を防止するとともに、クロ
スボンディングをも可能し、レイアウト上の制約を除去
し得る半導体装置を提供することにある。An object of the present invention is to connect the semiconductor chip and the inner leads using, for example, resin-coated Au wire, thereby preventing undesired contact due to wire flow, and also enabling cross bonding, thereby eliminating layout constraints. The object of the present invention is to provide a semiconductor device that can be obtained.

本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明を簡単に述べれば、下記の
とおりである。A brief description of the invention disclosed in this application is as follows.

すなわち、半導体チップとインナーリードとを樹脂コー
ティングしたＡｕ線で接続し、ワイヤー流れによる不測
の接触事故の防止、クロスボンディングを容易にして、
半導体装置のレイアウト上の制約を除去する、という本
発明の目的を達成するものである。In other words, the semiconductor chip and the inner leads are connected with a resin-coated Au wire to prevent accidental contact due to wire flow and to facilitate cross bonding.
This achieves the object of the present invention, which is to remove restrictions on the layout of semiconductor devices.

〔実施例〕〔Example〕

次に、第１図〜第３図を参照して本発明を適用した半導
体装置の一実施例を述べる。Next, an embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. 1 to 3.

本実施例の特徴は、樹脂コーティングが施こされたＡｕ
線を用いて半導体チップとインナーリードとの間のボン
ディングを行うことにある。The feature of this example is that the resin-coated Au
The purpose is to perform bonding between a semiconductor chip and inner leads using wires.

第１図（イ）〜［Ｆ］はボンディング工程を示すもので
あり、１はキャピラリー、２はＡｕ線でありその周囲は
絶縁材３、例えば合成樹脂忙よってコーティングされて
いる。また、タブ４上には半導体チップ５が取付けられ
、キャピラリー１が第１図囚に示す矢印の如（下降して
、金ボール２ａと端子６とのボンディングが行われろ。FIGS. 1A to 1F show the bonding process, in which 1 is a capillary, 2 is an Au wire, and the periphery thereof is coated with an insulating material 3, such as a synthetic resin. Further, a semiconductor chip 5 is mounted on the tab 4, and the capillary 1 is lowered as shown by the arrow in FIG. 1 to bond the gold ball 2a and the terminal 6.

次いで、キャピラリー１は第１図０３１の如く左方に移
動し、インナーリード１１上の所定位置て下降する。そ
して、熱圧着とスクラブ（超音波印加）とが行われ、イ
ンナーリード１１との接触面の樹脂３が溶けてＡｕ線２
の一部がインナーリード１１の所定位置に直接接触する
ようになる。この状態で、水素トーチ（図示せず）等に
より加熱すると、Ａｕ線が溶けて接断され第１図の）の
如くインナーリード１１とＡｕ線２とのボンディングが
行われる。Next, the capillary 1 moves to the left as shown in FIG. 1, 031, and descends to a predetermined position above the inner lead 11. Then, thermocompression bonding and scrubbing (ultrasonic application) are performed, and the resin 3 on the contact surface with the inner lead 11 is melted and the Au wire 2
A portion of the inner lead 11 comes into direct contact with a predetermined position of the inner lead 11. In this state, when heated with a hydrogen torch (not shown) or the like, the Au wire is melted and disconnected, and bonding between the inner lead 11 and the Au wire 2 is performed as shown in FIG. 1).

この結果、半導体チップ５の各端子６とインナーリード
１１の先端とは、第２図に示す如＜　Ａ　ｕ線によって
ボンディングされることになる。なお、４ａはタブ吊り
リードである。半導体集積回路の製造にあたっては、上
記ボンディング動作が終了した後、レジン或いはセラミ
ンクによってモール　　　　　　１ドが行われるが、Ａ
ｕ線２が流れてＡｕ線とＡｕ線、或いはタブ４に接触し
てもその表面が樹脂コーティングされているので上述し
た短絡不良は発生しない。As a result, each terminal 6 of the semiconductor chip 5 and the tip of the inner lead 11 are bonded by the Au wire as shown in FIG. Note that 4a is a tab suspension lead. In manufacturing semiconductor integrated circuits, after the above bonding operation is completed, molding is performed using resin or ceramic.
Even if the U-wire 2 flows and comes into contact with the Au wires or the tab 4, the above-mentioned short-circuit failure will not occur because the surface is coated with resin.

ところで、上記短絡不良の防止は、集積回路のレイアウ
トを行う際に回路パターン設計上の自由度を向上させる
ことができる。By the way, prevention of the short-circuit failure described above can improve the degree of freedom in circuit pattern design when designing the layout of an integrated circuit.

すなわち、第３図の矢印Ｂに示す如く回路パターンを形
成する際に端子６とインナーリード１１とを最短距離で
接続できない場合がある。従来は、このような事態を極
力さけるようにレイアウトするか、Ａｕ線２の高さを変
えてボンディングしていたのであるが、本発明を適用す
ることにより上記レイアウト上の制約と高さを変えると
いう面倒な工程が不要忙なる。That is, when forming a circuit pattern as shown by arrow B in FIG. 3, it may not be possible to connect the terminal 6 and the inner lead 11 at the shortest distance. Conventionally, the layout was designed to avoid such a situation as much as possible, or the height of the Au wire 2 was changed for bonding, but by applying the present invention, the above layout constraints and height can be changed. This troublesome process is unnecessary and busy.

〔効果〕〔effect〕

（１）　　樹脂コーティングの施こされたワイヤーによ
り、半導体チンプとインナーリード間のボンディングを
行うことにより、ワイヤー間、ワイヤーとタブ等との短
絡を防止することができ、半導体装置の信頼性が著しく
向上する。(1) By bonding between the semiconductor chip and the inner leads using resin-coated wires, short circuits between wires and between wires and tabs, etc. can be prevented, significantly improving the reliability of semiconductor devices. improves.

（２）上記ｆｉ＋により、クロスボンディングが容易に
なるので、半導体装置をレイアウトする際の制約が低減
され、高集積度の半導体集積回路を得ろことができろ。(2) Since cross bonding is facilitated by the above-mentioned fi+, restrictions on layout of a semiconductor device are reduced, making it possible to obtain a highly integrated semiconductor integrated circuit.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは（・５までもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Not even 5.

例えば、ボンディングワイヤーはＡｕ線に限定されず、
ＡＡ’線であってもよい。また、樹脂コーティングの厚
さは数μ程度でよく、その材質は水素トーチ、或いはへ
リュウムトーチ、放電アーク等による加熱温度に対応し
て自由に選択することができる。For example, the bonding wire is not limited to Au wire,
It may be the AA' line. Further, the thickness of the resin coating may be approximately several μm, and the material thereof can be freely selected depending on the heating temperature by a hydrogen torch, a helium torch, a discharge arc, or the like.

〔利用分野〕 以上の説明では、主とし、て本発明者によってなされた
発明をその背景となった利用分野である半導体集積回路
について説明したが、それに限定されろものではない。[Field of Application] In the above description, the invention made by the present inventor has mainly been described with respect to the semiconductor integrated circuit, which is the field of application that forms the background of the invention, but the present invention is not limited thereto.

本発明は、ボンディングワイヤを使用するすべてのＩＣ
に利用することができる。This invention applies to all ICs that use bonding wires.
It can be used for.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａｌ　（Ｂｌ　（Ｃ１■）は本発明の一実施例
を示すボンディング工程の説明図を示し、 第２図はボンデング後の状況を示す半導体装置の要部の
斜視図を示し、 第３図はクロスボンディングの状況を示す半導体装置の
要部の平面図を示す。 １・・・キャピラリ、２・・・Ａｕ線、３・・・樹脂コ
ーティング、４・・・タブ、５・・・半導体チップ、６
・・・端子、１１・・・インナーリード、Ｂ・・・クロ
スボンディング位置。 代理人　弁理士　　　高　橋　明　夫　　ゝ２″第　　
　１　　　図 （ＡＩ （Ｄ）FIG. 1 (Al (Bl (C1)) shows an explanatory view of the bonding process showing one embodiment of the present invention, FIG. 2 shows a perspective view of the main parts of the semiconductor device showing the situation after bonding, and FIG. Figure 3 shows a plan view of the main parts of the semiconductor device showing the state of cross bonding. 1... Capillary, 2... Au wire, 3... Resin coating, 4... Tab, 5... semiconductor chip, 6
...Terminal, 11...Inner lead, B...Cross bonding position. Agent Patent Attorney Akio Takahashi ゝ2″
1 Figure (AI (D)

Claims (1)

【特許請求の範囲】[Claims] １、半導体チップとインナーリードとを絶縁材にてコー
ティングした線材を用いて接続したことを特徴とする半
導体装置。1. A semiconductor device characterized in that a semiconductor chip and an inner lead are connected using a wire coated with an insulating material.
JP59174978A 1984-08-24 1984-08-24 Semiconductor device Pending JPS6153738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59174978A JPS6153738A (en) 1984-08-24 1984-08-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59174978A JPS6153738A (en) 1984-08-24 1984-08-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6153738A true JPS6153738A (en) 1986-03-17

Family

ID=15988073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59174978A Pending JPS6153738A (en) 1984-08-24 1984-08-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6153738A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5971251A (en) * 1997-10-27 1999-10-26 Lear Automotive Dearborn, Inc. Method of welding a terminal to a flat flexible cable
JP2018096982A (en) * 2016-12-08 2018-06-21 清華大学Ｔｓｉｎｇｈｕａ Ｕｎｉｖｅｒｓｉｔｙ Wiping sample collection apparatus, card reader and gate apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5971251A (en) * 1997-10-27 1999-10-26 Lear Automotive Dearborn, Inc. Method of welding a terminal to a flat flexible cable
JP2018096982A (en) * 2016-12-08 2018-06-21 清華大学Ｔｓｉｎｇｈｕａ Ｕｎｉｖｅｒｓｉｔｙ Wiping sample collection apparatus, card reader and gate apparatus

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