JPH0525237Y2 - - Google Patents

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Publication number
JPH0525237Y2
JPH0525237Y2 JP1987114582U JP11458287U JPH0525237Y2 JP H0525237 Y2 JPH0525237 Y2 JP H0525237Y2 JP 1987114582 U JP1987114582 U JP 1987114582U JP 11458287 U JP11458287 U JP 11458287U JP H0525237 Y2 JPH0525237 Y2 JP H0525237Y2
Authority
JP
Japan
Prior art keywords
electrode body
semiconductor element
lead wire
thin lead
relay member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987114582U
Other languages
Japanese (ja)
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JPH0165134U (en
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Filing date
Publication date
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Priority to JP1987114582U priority Critical patent/JPH0525237Y2/ja
Publication of JPH0165134U publication Critical patent/JPH0165134U/ja
Application granted granted Critical
Publication of JPH0525237Y2 publication Critical patent/JPH0525237Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案は、複数の半導体素子間がリード細線を
介して電気的に接続された構造の樹脂封止型半導
体装置に関する。
[Detailed Description of the Invention] Industrial Application Field The present invention relates to a resin-sealed semiconductor device having a structure in which a plurality of semiconductor elements are electrically connected via thin lead wires.

従来の技術及び解決すべき課題 今日、電力用半導体装置においても高密度実装
化の要求が高まつており、複数の半導体素子を1
つの絶縁物封止体でパツケージした構造の電力用
半導体装置の実現が望まれている。そこで、本考
案者は複数の支持板とこれに対応する多数の外部
リードとを有するリードフレームを使用して上記
の構造の電力用半導体装置の製作を試みた。しか
しながら、半導体素子の数が3個を越えると配線
が極めて複雑になるし、半導体素子間を接続する
リード細線の長さが増大して短絡事故等が生じ易
いという問題が生じた。
Conventional technology and issues to be solved Today, there is an increasing demand for high-density packaging in power semiconductor devices, and multiple semiconductor elements are integrated into one.
It is desired to realize a power semiconductor device having a structure packaged with two insulator sealing bodies. Therefore, the present inventor attempted to manufacture a power semiconductor device having the above structure using a lead frame having a plurality of support plates and a corresponding number of external leads. However, when the number of semiconductor elements exceeds three, the wiring becomes extremely complicated, and the length of thin lead wires connecting the semiconductor elements increases, resulting in problems such as short-circuit accidents and the like.

そこで、本考案は上記の問題を解決できる複数
の半導体素子を有する新規な構造の樹脂封止型半
導体装置を提供することを目的とする。
Therefore, an object of the present invention is to provide a resin-sealed semiconductor device having a novel structure and having a plurality of semiconductor elements that can solve the above-mentioned problems.

課題を解決するための手段 本考案の樹脂封止型半導体装置は、第1の半導
体装置が載置された第1の支持板と第2の半導体
素子が載置された第2の支持板とを有する。第1
の支持板と第2の支持板との間には中継部材が載
置された配線電極体が介在する。中継部材は配線
電極体と電気的に絶縁された電極体を有する。中
継部材の電極体と第1の半導体素子に形成された
電極体とが第1のリード細線を介して電気的に接
続される。中継部材の電極体と第2の半導体素子
に形成された電極体とは第2のリード細線を介し
て電気的に接続されている。配線電極体は第1の
半導体素子に形成された他の電極体と第3のリー
ド細線を介して電気的に接続され且つ第2の半導
体素子よりも第1の半導体素子から離間して配置
された第3の半導体素子の近傍まで延在する。ま
た、配線電極体は、第3の半導体素子に形成され
た電極体と第4のリード細線を介して電気的に接
続されている。
Means for Solving the Problems The resin-sealed semiconductor device of the present invention includes a first support plate on which a first semiconductor device is placed, and a second support plate on which a second semiconductor element is placed. has. 1st
A wiring electrode body on which a relay member is placed is interposed between the support plate and the second support plate. The relay member has an electrode body electrically insulated from the wiring electrode body. The electrode body of the relay member and the electrode body formed on the first semiconductor element are electrically connected via the first thin lead wire. The electrode body of the relay member and the electrode body formed on the second semiconductor element are electrically connected via a second thin lead wire. The wiring electrode body is electrically connected to another electrode body formed on the first semiconductor element via a third thin lead wire, and is arranged further away from the first semiconductor element than the second semiconductor element. and extends to the vicinity of the third semiconductor element. Furthermore, the wiring electrode body is electrically connected to the electrode body formed on the third semiconductor element via a fourth thin lead wire.

第1の半導体素子と第2の半導体素子は一方が
モノリシツクICチツプであり他方がパワートラ
ンジスタチツプである。
One of the first semiconductor device and the second semiconductor device is a monolithic IC chip, and the other is a power transistor chip.

中継部材は、樹脂片から成る絶縁層と、絶縁層
の一方の主面に形成された第1の金属層と、絶縁
層の他方の主面に形成された第2の金属層とを有
し、第1の金属層が電極体となり、第2の金属層
が配線電極体の一方の主面に半田を介して固着さ
れる。
The relay member includes an insulating layer made of a resin piece, a first metal layer formed on one main surface of the insulating layer, and a second metal layer formed on the other main surface of the insulating layer. , the first metal layer serves as an electrode body, and the second metal layer is fixed to one main surface of the wiring electrode body via solder.

中継部材は、シリコン片と、シリコン片の一方
の主面に形成された酸化膜から成る絶縁層と、絶
縁層の表面に形成された第1の金属層と、シリコ
ン片の他方の主面に形成された第2の金属層とを
有する。
The relay member includes a silicon piece, an insulating layer made of an oxide film formed on one main surface of the silicon piece, a first metal layer formed on the surface of the insulating layer, and a first metal layer formed on the other main surface of the silicon piece. a second metal layer formed thereon.

作 用 本考案によれば、第1の半導体素子の電極体と
第2の半導体素子の電極体とを接続するリード細
線は第1のリード細線と第2のリード細線に分割
され、第1及び第2のリード細線の各他端は中継
部材に接続される。この中継部材は第1及び第2
の半導体素子が載置された第1及び第2の支持板
の間に配置された配線電極体に装着される。従つ
て、第1及び第2のリード細線の接続距離を短く
でき、リード細線の垂下を抑制できる。また、第
2の半導体素子よりも第1の半導体素子から離間
して配置された第3の半導体素子は第4のリード
細線、配線電極体及び第3のリード細線を介して
第1の半導体素子と電気的に接続されている。配
線電極体は第1及び第2のリード細線と電気的に
絶縁されて第1及び第2のリードと多重配線され
ている。したがつて、複雑な立体的配線が可能と
なる。
Effect According to the present invention, the thin lead wire connecting the electrode body of the first semiconductor element and the electrode body of the second semiconductor element is divided into the first thin lead wire and the second thin lead wire. Each other end of the second thin lead wire is connected to the relay member. This relay member is the first and second relay member.
The semiconductor device is attached to a wiring electrode body disposed between the first and second support plates on which the semiconductor device is mounted. Therefore, the connection distance between the first and second thin lead wires can be shortened, and drooping of the thin lead wires can be suppressed. Further, the third semiconductor element, which is disposed further away from the first semiconductor element than the second semiconductor element, is connected to the first semiconductor element via the fourth thin lead wire, the wiring electrode body, and the third thin lead wire. electrically connected to. The wiring electrode body is electrically insulated from the first and second thin lead wires and is multi-wired with the first and second leads. Therefore, complex three-dimensional wiring becomes possible.

実施例 以下、本考案の一実施例として電力用樹脂封止
型複合ICについて第1図〜第3図を参照して説
明する。
Embodiment Hereinafter, as an embodiment of the present invention, a resin-sealed composite IC for electric power will be described with reference to FIGS. 1 to 3.

本実施例の電力用樹脂封止型複合ICは、リー
ドフレーム1と、パワートランジスタチツプ2a
〜2dと、モノリシツクICチツプ3と、多数の
リード細線4と、中継部材10,20と、樹脂封
止体6とから構成される。リードフレーム1は複
数の外部リード部7a〜7pとこれに続く配線電
極体部8a〜8pとこれに続く支持板9a,9
c,9h,9m,9pを有する。なお、外部リー
ド部7a〜7pと配線電極体部8a〜8pと支持
板9a,9c,9h,9m,9pの下面は同一平
面上にある。
The power resin-sealed composite IC of this embodiment includes a lead frame 1 and a power transistor chip 2a.
2d, a monolithic IC chip 3, a large number of thin lead wires 4, relay members 10 and 20, and a resin molding body 6. The lead frame 1 includes a plurality of external lead parts 7a to 7p, wiring electrode body parts 8a to 8p that follow these, and support plates 9a and 9 that follow these.
It has c, 9h, 9m, and 9p. Note that the lower surfaces of the external lead portions 7a to 7p, the wiring electrode body portions 8a to 8p, and the support plates 9a, 9c, 9h, 9m, and 9p are on the same plane.

支持板9a,9c,9m,9pの上面にはそれ
ぞれパワートランジスタチツプ2a,2b,2
c,2dが載置されており、支持板9hの上面に
はモノリシツクICチツプ3が載置されている。
パワートランジスタチツプ2a,2b,2c,2
dの上面には複数の電極(ボンデイングパツド)
が形成されており、モノリシツクICチツプ3の
上面にも多数のボンデイングパツドが形成されて
いる。
On the upper surfaces of the support plates 9a, 9c, 9m, 9p are power transistor chips 2a, 2b, 2, respectively.
A monolithic IC chip 3 is placed on the upper surface of the support plate 9h.
Power transistor chips 2a, 2b, 2c, 2
There are multiple electrodes (bonding pads) on the top surface of d.
A large number of bonding pads are also formed on the upper surface of the monolithic IC chip 3.

配線電極体部8d,8lの上面にはそれぞれ中
継部材10,20が載置されている。中継部材1
0は第2図に示すように、絶縁層11と絶縁層1
1の一方の主面に形成された第1の導体層12と
絶縁層11の他方の主面に形成された第2の導体
層13を有する。また、中継部材20も絶縁層と
絶縁層の一方の主面に形成された第1の導体層と
絶縁層の他方の主面に形成された第2の導体層と
を有する。絶縁層はポリイミド又はエポキシ樹脂
板(骨材としてガラス繊維の織布を封入した樹脂
板)で形成される。第1及び第2の導体層は絶縁
層側から順番に銅層−ニツケル層−銀層の3層構
造となつている。銅層は絶縁層を形成する樹脂板
との密着性に優れ、銀層はリード細線との良好な
接続を可能とする。また、ニツケル層は固く形成
されるため、ワイヤボンデイング時の超音波振動
を吸収しないので、良好なワイヤボンデイングを
行うのに有効である。中継部材10,20は第2
の導体層が半田(図示せず)を介して配線電極体
部8d,8lに固着されている。なお、中継部材
10,20は支持板9hにモノリシツクICチツ
プ3を固着する工程内の同一の工程(ダイボンデ
イング)によつて配線電極体8d,8l上に固着
される。リード細線4は、約30μmの直径を有す
る金(Au)又は金合金から成る細線である。リ
ード細線4はパワートランジスタチツプ2a〜2
dの電極及びモノリシツクICチツプの電極に対
してはネイルヘツドボンデイング、中継部材1
0,20及び配線電極体部8b,8d,8e,8
f,8g,8j,8k,8l,8nに対してはス
テイツチボンデイングされる。
Relay members 10 and 20 are placed on the upper surfaces of the wiring electrode body parts 8d and 8l, respectively. Relay member 1
0 is an insulating layer 11 and an insulating layer 1 as shown in FIG.
1 and a second conductor layer 13 formed on the other main surface of the insulating layer 11. Further, the relay member 20 also includes an insulating layer, a first conductor layer formed on one main surface of the insulating layer, and a second conductor layer formed on the other main surface of the insulating layer. The insulating layer is formed of a polyimide or epoxy resin plate (a resin plate in which a woven glass fiber cloth is enclosed as an aggregate). The first and second conductor layers have a three-layer structure consisting of a copper layer, a nickel layer, and a silver layer in order from the insulating layer side. The copper layer has excellent adhesion to the resin plate forming the insulating layer, and the silver layer enables good connection with the thin lead wire. Furthermore, since the nickel layer is formed hard, it does not absorb ultrasonic vibrations during wire bonding, and is therefore effective in performing good wire bonding. The relay members 10 and 20 are the second
The conductor layers are fixed to the wiring electrode body portions 8d and 8l via solder (not shown). The relay members 10, 20 are fixed onto the wiring electrode bodies 8d, 8l by the same process (die bonding) within the process of fixing the monolithic IC chip 3 to the support plate 9h. The lead thin wire 4 is a thin wire made of gold (Au) or a gold alloy and has a diameter of about 30 μm. The thin lead wire 4 connects the power transistor chips 2a to 2.
Nail head bonding and relay member 1 are used for electrodes d and monolithic IC chip electrodes.
0, 20 and wiring electrode body parts 8b, 8d, 8e, 8
Static bonding is applied to f, 8g, 8j, 8k, 8l, and 8n.

次に、リード細線4の接続方法についてモノリ
シツクICチツプ3と中継部材10とのリード細
線を接続する方法を例にとつて第3図について説
明する。
Next, a method for connecting the thin lead wires 4 will be described with reference to FIG. 3, taking as an example a method for connecting the thin lead wires between the monolithic IC chip 3 and the relay member 10.

まず、第3図Aに示すように、ワイヤボンダの
パイプ状のキヤピラリ50の中心孔51からリー
ド細線4を送り出し、電気スパーク又は水素炎等
でリード細線4の先端部にボールを形成する。ボ
ールの直径は、リード細線4の直径の2〜3倍程
度である。
First, as shown in FIG. 3A, the thin lead wire 4 is sent out from the center hole 51 of the pipe-shaped capillary 50 of the wire bonder, and a ball is formed at the tip of the thin lead wire 4 using an electric spark, hydrogen flame, or the like. The diameter of the ball is about 2 to 3 times the diameter of the thin lead wire 4.

次に、第3図Bに示すように、モノリシツク
ICチツプ3の電極にボールをキヤピラリ50の
先端で押し付け第一のボンデイングを行う。この
際、モノリシツクICチツプの電極は200〜250℃
に予め加熱されている。また、キヤピラリ50に
は、リード細線4の接続方向と直角な矢印52で
示す方向への超音波振動が加えられている。これ
により、モノリシツクICチツプの電極にリード
細線4が釘頭状に接続された第一のボンデイング
部(ネイルヘツドボンデイング部)4aが形成さ
れる。
Next, as shown in Figure 3B, the monolithic
First bonding is performed by pressing the ball against the electrode of the IC chip 3 with the tip of the capillary 50. At this time, the electrodes of the monolithic IC chip should be kept at a temperature of 200 to 250℃.
pre-heated. Furthermore, ultrasonic vibration is applied to the capillary 50 in the direction indicated by an arrow 52 perpendicular to the connecting direction of the thin lead wire 4 . As a result, a first bonding portion (nail head bonding portion) 4a is formed in which the thin lead wire 4 is connected to the electrode of the monolithic IC chip in the shape of a nail head.

続いて、第3図Cに示すように、キヤピラリ5
0を上昇して大きく引き回すようにして、リード
細線4を繰り出しながら中継部材10に向かつて
キヤピラリ50を移動する。
Next, as shown in Figure 3C, the capillary 5
The capillary 50 is moved toward the relay member 10 while letting out the thin lead wire 4 by raising the wire 0 and drawing it around widely.

その後、第3図Dに示すように、中継部材10
の第1の導体層12に第二のボンデイングを行
う。即ち、第1の導体層12は前述と同様に200
〜250℃に予め加熱され、キヤピラリ50には前
述と同様の超音波振動が加えられている。この状
態で、第1の導体層12に対し径方向にリード細
線4を押圧することにより、リード細線4と第1
の導体層12とが接続され、第二のボンデイング
部(ステイツチボンデイング部)4bが形成され
る。なお、第3図B,Dの工程を電極体の加熱の
みによる熱圧着法又は超音波振動による加熱のみ
の超音波法等で行つてもよい。
Thereafter, as shown in FIG. 3D, the relay member 10
A second bonding is performed on the first conductor layer 12 of. That is, the first conductor layer 12 has a thickness of 200
The capillary 50 is preheated to ~250°C, and the same ultrasonic vibrations as described above are applied to the capillary 50. In this state, by pressing the lead thin wire 4 in the radial direction against the first conductor layer 12, the lead thin wire 4 and the first
is connected to the conductor layer 12 to form a second bonding section (stanch bonding section) 4b. Note that the steps shown in FIGS. 3B and 3D may be performed by a thermocompression bonding method using only heating of the electrode body, or an ultrasonic method using only heating using ultrasonic vibration.

最終的には、第3図Eのように、キヤピラリ5
0を一定の高さまで上昇した後、クランプでリー
ド細線4を押さえつつ更にキヤピラリ50を上昇
させてリード細線4を切断する。第3図Dに示す
ように、第一のボンデイング側では、モノリシツ
クICチツプ3の電極に対するリード細線4の角
度αはほぼ直角となり、上を跨るリード細線4と
の距離は長くなる。一方、第二のボンデイング側
では、リード細線4の第1の導体層12に対する
角度θは鋭角となり、上を跨るリード細線4との
距離は短くなる。
Finally, as shown in Figure 3E, connect capillary 5.
0 to a certain height, the capillary 50 is further raised while holding the thin lead wire 4 with a clamp, and the thin lead wire 4 is cut. As shown in FIG. 3D, on the first bonding side, the angle α of the thin lead wire 4 with respect to the electrode of the monolithic IC chip 3 is approximately a right angle, and the distance between the thin lead wire 4 and the thin lead wire 4 that straddles the top becomes long. On the other hand, on the second bonding side, the angle θ of the thin lead wire 4 with respect to the first conductor layer 12 is an acute angle, and the distance between the thin lead wire 4 and the thin lead wire 4 spanning over the thin lead wire 4 is shortened.

本実施例の電力用樹脂封止型複合ICは、中継
部材10,20及びパワートランジスタチツプ2
a〜2dがモノリシツクICチツプ3を基準にし
て左右対象に配置されているので、第1図のモノ
リシツクICチツプ3の左側についてのみ説明す
る。
The power resin-sealed composite IC of this embodiment includes relay members 10 and 20 and a power transistor chip 2.
Since elements a to 2d are arranged symmetrically with respect to the monolithic IC chip 3, only the left side of the monolithic IC chip 3 in FIG. 1 will be described.

第1図において、モノリシツクICチツプ3は
本考案の第1の半導体素子に相当し、パワートラ
ンジスタチツプ2aと2bはそれぞれ本考案の第
3と第2の半導体素子に相当する。また、モノリ
シツクICチツプ3と中継部材10とを接続する
リード細線4は本考案の第1のリード細線に相当
する。中継部材10とパワートランジスタチツプ
2bとを接続するリード細線5は本考案の第2の
リード細線に相当する。モノリシツクICチツプ
3と配線電極体部8dとを接続するリード細線1
4は本考案の第3のリード細線に相当する。配線
電極体部8dとパワートランジスタチツプ2aと
を接続するリード細線15は本考案の第4のリー
ド細線に相当する。中継部材10を介して接続す
ることにより第一のリード細線及び第二のリード
細線の各接続距離を短くできる。このためリード
細線の大幅な垂下を防止することができる。従つ
て、封止樹脂の成形時にリード細線が垂下せず、
電気的短絡が発生しない。また、中継部材10は
第一の導体層12と第二の導体層13とが絶縁層
11によつて電気的に絶縁されているから、中継
部材10を固着した配線電極体8dと第1及び第
2のリード細線とで多重配線(クロスオーバー配
線)が可能となる。これにより配線の自由度が拡
大され、複雑な配線要求に応えることができる。
In FIG. 1, a monolithic IC chip 3 corresponds to the first semiconductor device of the present invention, and power transistor chips 2a and 2b correspond to the third and second semiconductor devices of the present invention, respectively. Further, the thin lead wire 4 connecting the monolithic IC chip 3 and the relay member 10 corresponds to the first thin lead wire of the present invention. The thin lead wire 5 connecting the relay member 10 and the power transistor chip 2b corresponds to the second thin lead wire of the present invention. Thin lead wire 1 connecting monolithic IC chip 3 and wiring electrode body 8d
4 corresponds to the third thin lead wire of the present invention. The thin lead wire 15 connecting the wiring electrode body portion 8d and the power transistor chip 2a corresponds to the fourth thin lead wire of the present invention. By connecting via the relay member 10, each connection distance between the first thin lead wire and the second thin lead wire can be shortened. Therefore, drastic drooping of the thin lead wire can be prevented. Therefore, the thin lead wires do not droop during molding of the sealing resin.
No electrical short circuits occur. Furthermore, since the first conductor layer 12 and the second conductor layer 13 of the relay member 10 are electrically insulated by the insulating layer 11, the wiring electrode body 8d to which the relay member 10 is fixed is connected to the first and second conductor layers 13 and 13. Multiple wiring (crossover wiring) is possible with the second thin lead wire. This expands the degree of freedom in wiring, making it possible to meet complex wiring requirements.

また、中継部材10はパワートランジスタチツ
プ2a,2b又はモノリシツクICチツプ3と同
一のダイボンデイング工程にて配線電極体8dに
固着できるから、中継部材10を配置するために
新たな異種の工程を行う必要はない。なお、中継
部材10、パワートランジスタチツプ2a,2b
及びモノリシツクICチツプ3の固着される部分
の配線電極体及び支持電極体には、予めクリーム
半田(ペースト状の半田)を印刷によつて形成し
ておき、中継部材10、パワートランジスタチツ
プ2a,2b及びモノリシツクICチツプ3をク
リーム半田の粘着力で仮固定し、後に加熱して半
田を溶融させる工程(リフロー工程)を通してこ
れらを固定する。
Further, since the relay member 10 can be fixed to the wiring electrode body 8d in the same die bonding process as the power transistor chips 2a, 2b or the monolithic IC chip 3, it is necessary to perform a new and different process to arrange the relay member 10. There isn't. Note that the relay member 10, power transistor chips 2a, 2b
Cream solder (paste-like solder) is printed in advance on the wiring electrode body and supporting electrode body of the portion to which the monolithic IC chip 3 is fixed, and then the relay member 10 and the power transistor chips 2a, 2b are attached. The monolithic IC chip 3 is temporarily fixed using the adhesive force of the cream solder, and is then fixed through a process of heating to melt the solder (reflow process).

なお、一例として中継部材10の大きさは、縦
2.3×横1.5mm×厚さ0.3〜0.5mmであり、モノリシ
ツクICチツプ3は、縦1.6mm×横1.6mm×厚さ0.3mm
であるから、中継部材10を半導体チツプと同等
に取扱えることが理解されよう。また、中継部材
10を介してリード細線の接続を行うので、パワ
ートランジスタチツプ2bの電極とモノリシツク
ICチツプ3の電極の両方に第一のボンデイング
部を形成することができる。モノリシツクICチ
ツプ3の電極やパワートランジスタチツプ2bの
電極に第二のボンデイング部を形成することは従
来では実用上困難であつた。つまり、第二のボン
デイング部の形状は第一のボンデイング部に比べ
て接続方向に長くなるので、ボンデイングパツド
をボンデイング部の形状に合せて長く形成しなけ
ればならない。従つて、チツプ上の面積のボンデ
イングパツドから受ける制約が大きくなる欠点が
あつた。このように、半導体チツプの電極に第二
のボンデイング部を形成することは実用上不可能
であり、半導体チツプ同志のリード細線での接続
は困難であつた。しかし、本実施例では両方の電
極に第一のボンデイング部を形成することができ
るので、半導体チツプ同志の接続が可能となつ
た。
In addition, as an example, the size of the relay member 10 is
2.3mm x width 1.5mm x thickness 0.3 to 0.5mm, and monolithic IC chip 3 is 1.6mm long x 1.6mm wide x 0.3mm thick.
Therefore, it will be understood that the relay member 10 can be handled in the same manner as a semiconductor chip. In addition, since the thin lead wire is connected via the relay member 10, the electrode of the power transistor chip 2b and the monolithic wire are connected via the relay member 10.
A first bonding portion can be formed on both electrodes of the IC chip 3. Conventionally, it has been practically difficult to form a second bonding portion on the electrode of the monolithic IC chip 3 or the electrode of the power transistor chip 2b. That is, since the shape of the second bonding part is longer in the connection direction than the first bonding part, the bonding pad must be formed longer to match the shape of the bonding part. Therefore, there is a drawback that the area on the chip is greatly restricted by the bonding pad. As described above, it is practically impossible to form a second bonding portion on the electrode of a semiconductor chip, and it has been difficult to connect semiconductor chips with each other using thin lead wires. However, in this embodiment, since the first bonding portions can be formed on both electrodes, it is possible to connect semiconductor chips to each other.

また、第3図Dからも明かなように、第二のボ
ンデイング部を形成する際に、半導体チツプ上に
形成された電極にキヤピラリ50が接触すること
がある。半導体チツプは薄くかつ強度も小さいた
め、電極にキヤピラリが接触すると電極又は半導
体チツプ自体が破損することがある。しかし、第
一のボンデイング部の形成の際は第3図Cのよう
に、キヤピラリ50によつて電極上に押し付けら
れたボールが電極上に大きく広がるため、キヤピ
ラリ50が電極に接触しない。従つて電極や半導
体チツプが破損せずに、ボンデイングが可能とな
る利点がある。
Furthermore, as is clear from FIG. 3D, when forming the second bonding part, the capillary 50 may come into contact with the electrode formed on the semiconductor chip. Semiconductor chips are thin and have low strength, so if a capillary comes into contact with an electrode, the electrode or the semiconductor chip itself may be damaged. However, when forming the first bonding part, as shown in FIG. 3C, the ball pressed onto the electrode by the capillary 50 spreads widely over the electrode, so the capillary 50 does not come into contact with the electrode. Therefore, there is an advantage that bonding can be performed without damaging the electrodes or the semiconductor chip.

なお、モノリシツクICチツプ3の右側におい
ても同様な効果が得られる。
Incidentally, a similar effect can be obtained on the right side of the monolithic IC chip 3.

また、本実施例ではリードフレーム下面の平面
形状が損なわれないので従来例と同様にボンデイ
ング作業が煩雑化することもない。
Further, in this embodiment, since the planar shape of the lower surface of the lead frame is not impaired, the bonding work does not become complicated as in the conventional example.

本考案の上記実施例は種々の変更が可能であ
る。
The above-described embodiments of the present invention can be modified in various ways.

例えば、中継部材10,20はシリコンウエハ
から作ることができる。即ち、シリコンウエハの
一方の主面(リード細線接続側)に酸化膜を熱酸
化により形成し、シリコン酸化膜を介してアルミ
ニウム電極を形成し、他方の主面(リードフレー
ムへの固着側)にはメツキによりニツケル電極を
形成する。酸化膜は6000Å〜1μmの厚さで十分な
絶縁耐圧を得ることができる。次にシリコンウエ
ハを所定の小片チツプに分割する。ここで、チツ
プの側面をガラス膜で被覆してもよい。なお、以
上の工程は他の半導体チツプの製造工程と共用す
ることができる。
For example, relay members 10, 20 can be made from silicon wafers. That is, an oxide film is formed by thermal oxidation on one main surface of the silicon wafer (the side where the thin lead wire is connected), an aluminum electrode is formed through the silicon oxide film, and an aluminum electrode is formed on the other main surface (the side that is fixed to the lead frame). Forms a nickel electrode by plating. An oxide film with a thickness of 6000 Å to 1 μm can provide sufficient dielectric strength. Next, the silicon wafer is divided into predetermined small chips. Here, the side surfaces of the chip may be covered with a glass film. Note that the above steps can be used in common with other semiconductor chip manufacturing steps.

ここで、第一のリード細線と第二のリード細線
のアルミニウム電極(導体層)に対する角度θは
小さいので、リード細線の垂下時にリード細線が
中継部材の側面と接触し、電気的短絡事故を発生
する危険がある。前述のガラス膜は電気的短絡事
故発生の防止に有効である。また、第一のリード
細線と第二のリード細線の形成後に両セカンドポ
ンデイング部及びその周辺をポリイミド系樹脂等
で被覆するとよい。これにより、リード細線の一
定の高さに固定することができる。このように、
セカンドボンデイング部及びその周辺に保護樹脂
を付着すると、絶縁性及びリード細線の固定の2
点で好ましい。上述の保護樹脂による被覆は、半
導体チツプ上の被覆と同一材料及び同一工程で行
うことができるので、被覆のために新たな異種の
工程が増加することはない。
Here, since the angle θ of the first thin lead wire and the second thin lead wire with respect to the aluminum electrode (conductor layer) is small, when the thin lead wire hangs down, the thin lead wire comes into contact with the side surface of the relay member, causing an electrical short circuit accident. There is a risk of The aforementioned glass film is effective in preventing the occurrence of electrical short circuit accidents. Further, after forming the first thin lead wire and the second thin lead wire, both second ponding portions and their surroundings may be coated with a polyimide resin or the like. This allows the thin lead wire to be fixed at a constant height. in this way,
When a protective resin is attached to the second bonding area and its surroundings, it improves insulation properties and fixes the thin lead wire.
This is preferable in this respect. Since the above-mentioned coating with the protective resin can be performed using the same material and the same process as the coating on the semiconductor chip, there is no need to add a new and different process for the coating.

中継部材10,20は、金属片であり、絶縁性
の樹脂によりリードフレーム上にこの金属片を固
着したものでもよい。例えば、中継部材10,2
0はニツケル被覆を施された銅材のような金属片
である。ニツケル被覆上のワイヤボンデイングさ
れる部分は更に銀メツキが施される。この場合、
エポキシ樹脂等の絶縁性接着材で中継部材10,
20を配線電極体8dに固着することにより、中
継部材10,20の主面とリードフレームの間が
前記接着剤により電気的に絶縁される。
The relay members 10 and 20 are metal pieces, and the metal pieces may be fixed onto a lead frame using an insulating resin. For example, relay members 10, 2
0 is a metal piece such as a copper material coated with nickel. The portions of the nickel coating to be wire bonded are further plated with silver. in this case,
The relay member 10 is made of an insulating adhesive such as epoxy resin.
By fixing 20 to the wiring electrode body 8d, electrical insulation is achieved between the main surfaces of the relay members 10 and 20 and the lead frame by the adhesive.

また、1本のリード細線のみでモノリシツク
ICチツプの電極とパワートランジスタチツプの
電極とを接続してもよい。即ち、一端がモノリシ
ツクICチツプの電極に接続されたリード細線を
少なくとも1度中継部材に接続した後に他端をパ
ワートランジスタチツプの電極に接続してもよ
い。この場合、中継部材の一方の側に接続された
リード細線を第一のリード細線、他方の側に接続
されたリード細線を第二のリード細線とする。
In addition, it is monolithic with only one thin lead wire.
The electrodes of the IC chip and the electrodes of the power transistor chip may be connected. That is, a thin lead wire whose one end is connected to the electrode of the monolithic IC chip may be connected to the relay member at least once, and then the other end may be connected to the electrode of the power transistor chip. In this case, the lead wire connected to one side of the relay member is the first lead wire, and the lead wire connected to the other side is the second lead wire.

前記実施例において中継部材10は第一の導体
層12と第二の導体層13を有する例を示した
が、第二の導体層13を形成しなくてもよい。こ
の場合は、絶縁層10を直接エポキシ樹脂系の接
着剤等でリードフレームに固着することができ
る。
In the embodiment described above, the relay member 10 has the first conductor layer 12 and the second conductor layer 13, but the second conductor layer 13 may not be formed. In this case, the insulating layer 10 can be directly fixed to the lead frame with an epoxy resin adhesive or the like.

考案の効果 本考案においては、リード線での接続が中継部
材を介して行われているので、リード細線の大幅
な垂下を防止でき、電気的短絡事故による不良が
発生しない。また、中継部材を設けることによ
り、交差配線が可能となり、良好な歩留まりで複
雑な配線を形成することができる。
Effects of the Invention In the present invention, since the lead wires are connected via the relay member, it is possible to prevent the thin lead wires from drooping significantly, and defects due to electrical short circuits do not occur. Further, by providing a relay member, cross wiring becomes possible, and complex wiring can be formed with a good yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の樹脂封止型半導体装置の実施
例を示す樹脂封止型複合ICを示す平面図、第2
図は第1図の部分的斜視図、第3図はネイルヘツ
ドボンデイング法によるリード細線の接続方法を
示す工程図であり、第3図Aはリード細線の先端
部にボールを形成する状態、第3図Bはボンデイ
ング部を形成する状態、第3図Cはキヤピラリを
移動する状態、第3図Dは第二のボンデイング部
を形成する状態、第3図Eはリード細線を切断す
る状態を示す。 3……モノリシツクICチツプ(第1の半導体
素子)、2a……パワートランジスタチツプ(第
3の半導体素子)、2b……パワートランジスタ
チツプ(第2の半導体素子)、9h……第1の支
持板、9c……第2の支持板、9a……第3の支
持板、10,20……中継部材、8d,8l……
配線電極体部(配線電極体)、12……第1の導
体層(電極体)、4……第1のリード細線、5…
…第2のリード細線、14……第3のリード細
線、15……第4のリード細線。
Fig. 1 is a plan view showing a resin-sealed composite IC showing an embodiment of the resin-sealed semiconductor device of the present invention;
The figure is a partial perspective view of FIG. 1, and FIG. 3 is a process diagram showing a method of connecting thin lead wires by the nail head bonding method. Figure 3B shows the state in which the bonding part is formed, Figure 3C shows the state in which the capillary is moved, Figure 3D shows the state in which the second bonding part is formed, and Figure 3E shows the state in which the thin lead wire is cut. . 3... Monolithic IC chip (first semiconductor element), 2a... Power transistor chip (third semiconductor element), 2b... Power transistor chip (second semiconductor element), 9h... First support plate , 9c... second support plate, 9a... third support plate, 10, 20... relay member, 8d, 8l...
Wiring electrode body portion (wiring electrode body), 12...first conductor layer (electrode body), 4...first lead thin wire, 5...
...Second thin lead wire, 14...Third thin lead wire, 15...Fourth thin lead wire.

Claims (1)

【実用新案登録請求の範囲】 (1) 第1の半導体素子が載置された第1の支持板
と第2の半導体素子が載置された第2の支持板
とを有し、前記第1の支持板と第2の支持板と
の間には中継部材が載置された配線電極体が介
在しており、前記中継部材は前記配線電極体と
電気的に絶縁された電極体を有し、前記中継部
材の電極体と前記第1の半導体素子に形成され
た電極体とが第1のリード細線を介して電気的
に接続されており、前記中継部材の電極体と前
記第2の半導体素子に形成された電極体とが第
2のリード細線を介して電気的に接続されてお
り、前記配線電極体は前記第1の半導体素子に
形成された他の電極体と第3のリード細線を介
して電気的に接続されており且つ前記第2の半
導体素子よりも前記第1の半導体素子から離間
して配置された第3の半導体素子の近傍まで延
在し、前記第3の半導体素子に形成された電極
体と第4のリード細線を介して電気的に接続さ
れていることを特徴とする樹脂封止型半導体装
置。 (2) 前記第1の半導体素子と第2の半導体素子は
一方がモノリシツクICチツプであり他方がパ
ワートランジスタチツプである実用新案登録請
求の範囲第1項記載の樹脂封止型半導体装置。 (3) 前記中継部材は、樹脂片から成る絶縁層と、
該絶縁層の一方の主面に形成された第1の金属
層と、前記絶縁層の他方の主面に形成された第
2の金属層とを有し、前記第1の金属層が前記
電極体となり、前記第2の金属層が前記配線電
極体の一方の主面に半田を介して固着されてい
る実用新案登録請求の範囲第1項に記載の樹脂
封止型半導体装置。 (4) 前記中継部材は、シリコン片と、該シリコン
片の一方の主面に形成された酸化膜から成る絶
縁層と、該絶縁層の表面に形成された第1の金
属層と、前記シリコン片の他方の主面に形成さ
れた第2の金属層とを有し、前記第1の金属層
が前記電極体となり、前記第2の金属層が前記
配線電極体に半田を介して固着されている実用
新案登録請求の範囲第1項に記載の樹脂封止型
半導体装置。
[Claims for Utility Model Registration] (1) A first support plate on which a first semiconductor element is placed and a second support plate on which a second semiconductor element is placed; A wiring electrode body on which a relay member is placed is interposed between the support plate and the second support plate, and the relay member has an electrode body electrically insulated from the wiring electrode body. , the electrode body of the relay member and the electrode body formed on the first semiconductor element are electrically connected via a first thin lead wire, and the electrode body of the relay member and the electrode body formed on the second semiconductor element The electrode body formed on the element is electrically connected via a second thin lead wire, and the wiring electrode body is connected to another electrode body formed on the first semiconductor element and the third thin lead wire. and extends to the vicinity of a third semiconductor element that is electrically connected to the first semiconductor element via the second semiconductor element and is arranged further away from the first semiconductor element than the second semiconductor element, and the third semiconductor element 1. A resin-sealed semiconductor device, characterized in that the device is electrically connected to an electrode body formed in the semiconductor device through a fourth thin lead wire. (2) The resin-sealed semiconductor device according to claim 1, wherein one of the first semiconductor element and the second semiconductor element is a monolithic IC chip and the other is a power transistor chip. (3) The relay member includes an insulating layer made of a resin piece;
a first metal layer formed on one main surface of the insulating layer; and a second metal layer formed on the other main surface of the insulating layer, and the first metal layer is connected to the electrode. 2. The resin-sealed semiconductor device according to claim 1, wherein the second metal layer is fixed to one main surface of the wiring electrode body via solder. (4) The relay member includes a silicon piece, an insulating layer made of an oxide film formed on one main surface of the silicon piece, a first metal layer formed on the surface of the insulating layer, and the silicon piece. a second metal layer formed on the other main surface of the piece, the first metal layer serving as the electrode body, and the second metal layer being fixed to the wiring electrode body via solder. A resin-sealed semiconductor device according to claim 1, which is a utility model registered as claimed in claim 1.
JP1987114582U 1987-06-05 1987-07-28 Expired - Lifetime JPH0525237Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987114582U JPH0525237Y2 (en) 1987-06-05 1987-07-28

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8664387 1987-06-05
JP1987114582U JPH0525237Y2 (en) 1987-06-05 1987-07-28

Publications (2)

Publication Number Publication Date
JPH0165134U JPH0165134U (en) 1989-04-26
JPH0525237Y2 true JPH0525237Y2 (en) 1993-06-25

Family

ID=31718608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987114582U Expired - Lifetime JPH0525237Y2 (en) 1987-06-05 1987-07-28

Country Status (1)

Country Link
JP (1) JPH0525237Y2 (en)

Also Published As

Publication number Publication date
JPH0165134U (en) 1989-04-26

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