JPH0684991A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0684991A
JPH0684991A JP4255732A JP25573292A JPH0684991A JP H0684991 A JPH0684991 A JP H0684991A JP 4255732 A JP4255732 A JP 4255732A JP 25573292 A JP25573292 A JP 25573292A JP H0684991 A JPH0684991 A JP H0684991A
Authority
JP
Japan
Prior art keywords
wire
loop
height
bonding
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4255732A
Other languages
Japanese (ja)
Inventor
Norio Nitta
法生 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP4255732A priority Critical patent/JPH0684991A/en
Publication of JPH0684991A publication Critical patent/JPH0684991A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To control mounting height of wiring areas by changing a shape of loop of wires bonded ordinarily. CONSTITUTION:An insulated wire 22 is bonded previously for electrically connecting a pad 21 of an integrated circuit chip 20 and a lead 23 of the other member. The bonding is carried out to the pad 25 so that the insulated wire 24 is crossed to clamp the ordinarily bonded wire 22. The shape of loop of the wire 22 is mechanically changed to the lower height to control the height of the wiring areas. Thereby, the height of loop can be controlled after the ordinary wire bonding and a semiconductor device with small size and lower height package can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ボンディングワイヤを
用いた配線箇所を有する半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a wiring portion using a bonding wire.

【０００２】[0002]

【従来の技術】従来、集積回路チップから電気信号を取
り出すためのワイヤボンディング法の一つとしてボール
ボンディング法がある。このボールボンディング法はパ
ッド直上にワイヤを取り出すために全方向へルーピング
できる自由度の高い汎用的なボンディング法である。と
ころで、近年の集積回路パッケージの薄型化に伴い、ボ
ンディングワイヤのループ高さの低減が求められてお
り、ボンディング法やワイヤ材によって低ループワイヤ
リングへの努力がなされてきている。2. Description of the Related Art Conventionally, there is a ball bonding method as one of wire bonding methods for extracting an electric signal from an integrated circuit chip. This ball bonding method is a general-purpose bonding method with a high degree of freedom that allows looping in all directions in order to take out the wire directly above the pad. By the way, as the integrated circuit package has been made thinner in recent years, it is required to reduce the loop height of the bonding wire, and efforts have been made for low loop wiring by a bonding method or a wire material.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、上記し
た従来のボンディング法やワイヤ材による低ループ化
は、通常のボンディング装置に特別な改造を施したり特
殊なワイヤ材を用いたりする必要があるので、これらに
よって配線箇所の実装高さを低減させることは簡単では
ないという問題があった。そこで本発明は、通常にボン
ディングされているワイヤのループ形状を変化させて配
線箇所の実装高さを低減させることができる半導体装置
を提供することを目的とする。However, in order to reduce the loop by the conventional bonding method and the wire material as described above, it is necessary to specially modify an ordinary bonding apparatus or to use a special wire material. There is a problem that it is not easy to reduce the mounting height of the wiring part by these. Therefore, an object of the present invention is to provide a semiconductor device capable of reducing the mounting height of a wiring portion by changing the loop shape of a wire that is normally bonded.

【０００４】[0004]

【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体装置は、電気的な接続を行うた
めに予めワイヤがボンディングされている配線箇所に、
絶縁被覆ワイヤを前記ワイヤに交差させてこのワイヤを
押さえ付けるようにボンディングしてなるものである。
また、前記予めボンディングされているワイヤが絶縁被
覆ワイヤであってもよい。なお、前記絶縁被覆ワイヤが
電気的な接続を行うワイヤであってもよい。In order to achieve the above object, the semiconductor device according to the present invention is provided with a wiring portion to which a wire is previously bonded in order to make an electrical connection.
The insulating coated wire is crossed with the wire and bonded so as to press the wire.
Further, the previously bonded wire may be an insulation coated wire. The insulation-coated wire may be a wire that makes an electrical connection.

【０００５】[0005]

【作用】上記のように構成された本発明においては、接
触しても十分な絶縁耐力を有しかつ裸金ワイヤと同程度
の接合性を有する絶縁被覆ワイヤを、ボンディングワイ
ヤによる配線箇所のループ変形に使用する。短絡の危険
性のない絶縁被覆ワイヤを、予めボンディングされてい
るワイヤ上に交差させて押さえ付けるようにボンディン
グすることによって、既にあるワイヤのループ形状を機
械的に変化させて低くし、実装高さの低減によって薄型
パッケージに対応した配線箇所になる。ワイヤを押さえ
付けるためにボンディング装置の通常の機能を使用する
ため、予めボンディングされているワイヤとして絶縁被
覆ワイヤを使用した場合は、ワイヤを交換せずに連続し
て低ループ化することができる。なお、従来のベアワイ
ヤを用いてある配線箇所に本発明を適用するには、ワイ
ヤの交換や複数台のボンディング装置を使用する。ルー
プ変形用の絶縁被覆ワイヤは電気的な接続とは関係の無
いワイヤでよいが、このループ変形用の絶縁被覆ワイヤ
によって電気的な接続も行うようにすると、より高密度
な配線箇所で実装高さを低減させることができる。In the present invention constructed as described above, an insulating coated wire having a sufficient dielectric strength even when contacted and having a bondability similar to that of a bare gold wire is used as a loop of a wiring portion by a bonding wire. Used for transformation. By bonding the insulation-coated wire, which has no risk of short-circuiting, so that it crosses over the pre-bonded wire and presses it down, the loop shape of the existing wire is mechanically changed to lower the mounting height. By reducing the number of wires, it becomes a wiring point corresponding to a thin package. Since the normal function of the bonding apparatus is used to hold down the wire, when an insulation-coated wire is used as the pre-bonded wire, the loop can be continuously reduced without replacing the wire. In addition, in order to apply the present invention to a wiring portion using a conventional bare wire, wire replacement or a plurality of bonding apparatuses are used. The insulation-coated wire for loop deformation may be a wire that has nothing to do with electrical connection, but if this insulation-coated wire for loop deformation is also used for electrical connection, the mounting height can be increased at higher density wiring points. Can be reduced.

【０００６】[0006]

【実施例】以下、本発明を実施例に従って説明する。EXAMPLES The present invention will be described below with reference to examples.

【０００７】実施例１ 図１（ａ）に示すように、集積回路チップの外部端子の
パッド面１１と他の部材のリード面１３とに、絶縁被覆
ワイヤ１２を通常にボンディングした。この絶縁被覆ワ
イヤ１２によるルーピングのループ高さは２５０μｍで
ある。この後、図１（ｂ）に示すように、絶縁被覆ワイ
ヤ１２によるルーピングに、絶縁被覆ワイヤ１４をクロ
スさせて押さえ付けるようにボンディングした。これに
よって、絶縁被覆ワイヤ１２のループ高さを２００μｍ
まで低減し、従来よりも薄型化した配線箇所を有する集
積回路パッケージを作製した。 Example 1 As shown in FIG. 1A, an insulating coated wire 12 was normally bonded to a pad surface 11 of an external terminal of an integrated circuit chip and a lead surface 13 of another member. The loop height of looping by the insulating coated wire 12 is 250 μm. After that, as shown in FIG. 1B, bonding was performed so that the insulating coated wire 14 was crossed and pressed against the looping by the insulating coated wire 12. As a result, the loop height of the insulation-coated wire 12 is 200 μm.
We have manufactured an integrated circuit package that has wiring parts that are thinner than before.

【０００８】実施例２ 図２に示すように、集積回路チップ２０の各パッド２１
と他の部材の各リード２３とに、それぞれ絶縁被覆ワイ
ヤ２２を通常にボンディングした。これら絶縁被覆ワイ
ヤ２２によるルーピングのループ高さは２４０μｍであ
る。この後、各絶縁被覆ワイヤ２２によるルーピングの
ループ高さを均一にするために、２本の絶縁被覆ワイヤ
２４をクロスさせて押さえ付けるようにパッド２５間で
ボンディングを交互に行った。これによって、各絶縁被
覆ワイヤ２２のループ高さを１６０μｍまで低減し、薄
型パッケージングを実現した。 Embodiment 2 As shown in FIG. 2, each pad 21 of the integrated circuit chip 20 is
The insulating coated wire 22 was normally bonded to the respective leads 23 of other members. The loop height of the looping by these insulating coated wires 22 is 240 μm. Thereafter, in order to make the loop height of the looping by each insulating coated wire 22 uniform, bonding was alternately performed between the pads 25 so that the two insulating coated wires 24 were crossed and pressed. As a result, the loop height of each insulation-coated wire 22 was reduced to 160 μm, and thin packaging was realized.

【０００９】[0009]

【発明の効果】以上説明したように、本発明によれば、
従来のボンディング法やワイヤ材による低ループ化の努
力ではなく、通常のワイヤボンディングの後に絶縁被覆
ワイヤのメリットを利用したループ変形を行うことによ
って、通常のボンディング装置に特別な改造を施したり
特殊なループ材を用いたりすることなく、簡単に配線箇
所の実装高さを低減させることができ、小型薄型パッケ
ージ化に貢献することができる。As described above, according to the present invention,
Rather than efforts to reduce loops using conventional bonding methods and wire materials, by performing loop deformation that takes advantage of the insulation-coated wire after ordinary wire bonding, special modifications are made to the ordinary bonding equipment or special bonding equipment is used. It is possible to easily reduce the mounting height of the wiring portion without using a loop material, and it is possible to contribute to a small and thin package.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１において、（ａ）は配線用の
絶縁被覆ワイヤを通常にボンディングした状態の概略断
面図、（ｂ）はループ変形用の絶縁被覆ワイヤでループ
高さを低減させた状態の概略断面図である。FIG. 1A is a schematic cross-sectional view of a state in which an insulating coating wire for wiring is normally bonded, and FIG. 1B is an insulating coating wire for loop deformation to reduce the loop height in Example 1 of the present invention. It is a schematic sectional drawing of the made state.

【図２】本発明の実施例２において、配線用の絶縁被覆
ワイヤのループ高さをループ変形用の絶縁被覆ワイヤで
低減させた状態の概略斜視図である。FIG. 2 is a schematic perspective view showing a state in which the loop height of the insulating coated wire for wiring is reduced by the insulating coated wire for loop deformation in the second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１１ パッド面 １２ 配線用の絶縁被覆ワイヤ １３ リード面 １４ ループ変形用の絶縁被覆ワイヤ ２０ 集積回路チップ ２１ パッド ２２ 配線用の絶縁被覆ワイヤ ２３ リード ２４ ループ変形用の絶縁被覆ワイヤ ２５ パッド 11 Pad Surface 12 Insulation Coated Wire for Wiring 13 Lead Surface 14 Insulation Coated Wire for Loop Deformation 20 Integrated Circuit Chip 21 Pad 22 Insulation Coated Wire for Wiring 23 Lead 24 Insulation Coated Wire for Loop Deformation 25 Pad

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 電気的な接続を行うために予めワイヤが
ボンディングされている配線箇所に、絶縁被覆ワイヤを
前記ワイヤに交差させてこのワイヤを押さえ付けるよう
にボンディングしてなる半導体装置。1. A semiconductor device in which an insulation-coated wire is cross-bonded to a wire location where a wire is previously bonded for electrical connection so as to press the wire. 【請求項２】 前記予めボンディングされているワイヤ
が絶縁被覆ワイヤであることを特徴とする請求項１記載
の半導体装置。2. The semiconductor device according to claim 1, wherein the pre-bonded wire is an insulation-coated wire. 【請求項３】 前記絶縁被覆ワイヤが電気的な接続を行
うワイヤであることを特徴とする請求項１記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the insulation-coated wire is a wire that makes an electrical connection.
JP4255732A 1992-08-31 1992-08-31 Semiconductor device Withdrawn JPH0684991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4255732A JPH0684991A (en) 1992-08-31 1992-08-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4255732A JPH0684991A (en) 1992-08-31 1992-08-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0684991A true JPH0684991A (en) 1994-03-25

Family

ID=17282866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4255732A Withdrawn JPH0684991A (en) 1992-08-31 1992-08-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0684991A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625235A (en) * 1995-06-15 1997-04-29 National Semiconductor Corporation Multichip integrated circuit module with crossed bonding wires
US5994784A (en) * 1997-12-18 1999-11-30 Micron Technology, Inc. Die positioning in integrated circuit packaging
US6441501B1 (en) * 2000-09-30 2002-08-27 Siliconware Precision Industries Co., Ltd. Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep
CN104051400A (en) * 2013-03-12 2014-09-17 飞思卡尔半导体公司 Brace for bond wire

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625235A (en) * 1995-06-15 1997-04-29 National Semiconductor Corporation Multichip integrated circuit module with crossed bonding wires
US5994784A (en) * 1997-12-18 1999-11-30 Micron Technology, Inc. Die positioning in integrated circuit packaging
US6441501B1 (en) * 2000-09-30 2002-08-27 Siliconware Precision Industries Co., Ltd. Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep
CN104051400A (en) * 2013-03-12 2014-09-17 飞思卡尔半导体公司 Brace for bond wire

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