JP3393800B2 - A method of manufacturing a semiconductor device - Google Patents

A method of manufacturing a semiconductor device

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Publication number
JP3393800B2
JP3393800B2 JP30253997A JP30253997A JP3393800B2 JP 3393800 B2 JP3393800 B2 JP 3393800B2 JP 30253997 A JP30253997 A JP 30253997A JP 30253997 A JP30253997 A JP 30253997A JP 3393800 B2 JP3393800 B2 JP 3393800B2
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wire
semiconductor chip
terminal
formed
semiconductor device
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JPH11145323A (en
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直幸 小泉
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新光電気工業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01076Osmium [Os]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は半導体装置の製造方法に係り、特に基板を使用しない半導体装置の製造方法に関する。 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor equipment, more particularly, to a method of manufacturing a semiconductor equipment that does not use a substrate. 【0002】 【従来の技術】近年の半導体装置の多ピン化に伴い、フリップチップ接続を使用した半導体装置が製品化されている。 [0002] As the number of pins of the Related Art In recent semiconductor device, a semiconductor device using a flip chip connection has been commercialized. このフリップチップ接続とは、半導体チップの能動素子面(電極端子が形成された面)を実装基板に向けて接続する接続方式であり、実装基板に形成された回路パターンと接続される半導体チップの電極端子はチップの周囲だけでなく、チップの任意の位置に(例えばマトリクス状に)配置できるため、容易に多くの電極端子数(I/O数)が取れるのである。 And the flip-chip connection, a connection method for connecting toward the active element surface of the semiconductor chip (the surface on which the electrode terminals are formed) on the mounting board, a semiconductor chip connected to the circuit pattern formed on the mounting substrate electrode terminal not only around the chip, (for example a matrix) in any position of the chip for possible placement, easily number of electrodes number of terminals (I / O number) than can be taken. そしてこの場合に電極端子同志の間隔が狭まる場合もあるが、実装基板の半導体チップが接続される面(半導体チップ搭載面)の裏面に外部接続用として形成される端子同志の間隔を、半導体チップの電極端子同志の間隔に規制されずに基板の配線の引回しによってさらに広げることができるので、実装工程において通常の設備で使用できる大きさの端子(例えばはんだバンプ)の形成が可能となるのである。 And there is a case where the interval of the electrode terminals comrades narrows in this case, the distance between the terminal comrades formed on the back surface of the surface on which the semiconductor chip mounting board is connected (the semiconductor chip mounting surface) for the external connection, the semiconductor chip it is possible to further expand without being restricted by the spacing of the electrode terminal comrades by routing of the substrate of the wiring, since the formation of the size of the terminal that can be used in conventional equipment in the mounting step (for example, solder bumps) can be is there. 【0003】 【発明が解決しようとする課題】しかしながら、上記のフリップチップ接続を使用した半導体装置には次のような課題がある。 [0003] The present invention is, however, the semiconductor device using the above flip-chip bonding has the following problems. この半導体装置では、基板(通常は多層配線基板)を構成要素としており、この基板は一般的に複数の製造工程から製造されるために製造コストが高い。 In this semiconductor device, the substrate (typically a multilayer wiring board) and a component of, the substrate generally has high production costs to be manufactured from a plurality of manufacturing steps. よって、半導体装置全体のコストも上昇してしまうという課題があった。 Therefore, the cost of the entire semiconductor device also has a problem that rises. 【0004】また、基板を使用しないで、半導体チップの能動素子面側に外部接続用の端子を形成するものとして特開平3-94438 号や特開平7-307409号に開示される半導体装置がある。 Further, without using the substrate, there is a semiconductor device disclosed in JP-A and JP-A 7-307409 3-94438 as forming a terminal for external connection to the active element surface of the semiconductor chip . この半導体装置では半導体チップの能動素子面側を樹脂封止すると共に、この封止樹脂の表面に外部接続用端子を形成し、能動素子面の電極端子と外部接続用端子とを接続するボンディングワイヤを封止樹脂内において配線する構造を採用する。 An active element surface of the semiconductor chip in the semiconductor device with resin sealing, bonding wire this to the surface of the sealing resin to form external connection terminals, for connecting the electrode terminals of the active element surface and the external connection terminal the adopted a structure that the wiring in the sealing resin. しかしながら、 However,
特開平7-307409号の半導体装置においては、使用される半導体チップは、能動素子面の周縁に電極端子が配置されているものしか想定されておらず、また特開平3-9443 In the semiconductor device of JP-A-7-307409, a semiconductor chip used is only not assumed that the periphery of the active element surface electrode terminals are arranged, also JP-A 3-9443
8 号の半導体装置においては、使用される半導体チップは能動素子面の全体に電極端子が配置されたものであるが、外部接続用端子は略電極端子の真上に位置したものであり、外部接続用端子の大きさによっては隣接する外部接続用端子同志が接触しないように半導体チップの電極端子の間隔自体を広げる必要が生じ、半導体チップの大きさが大きくなってしまうという課題がある。 In the semiconductor device of the No. 8, a semiconductor chip used is one in which the electrode terminals on the entire active element surface is disposed, the external connection terminals are those located directly above the substantially electrode terminals, external depending on the size of the connecting terminals becomes necessary to widen the distance between itself of the electrode terminals of the semiconductor chip so as not to contact the adjacent terminals each other for external connection, there is a problem that the size of the semiconductor chip increases. 【0005】従って、本発明は上記課題を解決すべくなされ、その目的とするところは、基板を使用することなく半導体チップの能動素子面の電極端子同志の間隔より広い間隔の外部接続用端子の形成が可能となる半導体装 Accordingly, the present invention is made to solve the above problems, it is an object of the external connection terminals widely spaced than the interval of the electrode terminals comrades of the active element surface of the semiconductor chip without using a substrate semiconductor instrumentation formation is possible
置の製造方法を提供することにある。 It is to provide a method of manufacturing location. 【0006】 【課題を解決するための手段】上記目的を達成するために、本発明に係る請求項1の半導体装置の製造方法は、 [0006] [Means for Solving the Problems] To achieve the above object, a method of manufacturing a semiconductor equipment according to claim 1 according to the present invention,
半導体チップの電極端子が形成された面が樹脂封止されると共に、封止樹脂層の前記半導体チップに対する背面側に外部接続用端子が装着され、前記封止樹脂層内に前記電極端子と前記外部接続用端子とを電気的に接続するボンディングワイヤが配されて成る半導体装置の製造方法において、一端が電極端子と接続されたボンディングワイヤを前記半導体チップの電極端子が形成された面に対して直角方向へN字状に延出させて切断するワイヤリング工程と、前記半導体チップの電極端子が形成された面及び該電極端子に接続されたボンディングワイヤを樹脂封止する樹脂封止工程と、前記封止樹脂層の前記半導体チップ側に対する背面側を研磨して前記ボンディングワイヤの端部を露出させる研磨工程と、前記ボンディングワイヤの端部に With the surface of the electrode terminals are formed of a semiconductor chip is sealed with resin, the external connection terminal is mounted on the rear side with respect to the semiconductor chip of the encapsulating resin layer, wherein said electrode terminal on the sealing resin layer the method of manufacturing a semiconductor device in which a bonding wire is disposed to electrically connect the external connection terminals for one end of the bonding wire connected to the electrode terminals electrode terminals of the semiconductor chip formed surface a wiring step of cutting by extending the N-shaped to perpendicular, and the semiconductor chip surface electrode terminals are formed, and a resin sealing step of the connected bonding wire electrode terminals sealed with resin, wherein a polishing step of exposing the end portion of the bonding wire by polishing the back side with respect to the semiconductor chip side of the sealing resin layer, an end of the bonding wire 部接続用端子を装着する外部接続用端子装着工程とを有することを特徴とする。 And having an external connection terminal mounting step for mounting the parts connecting terminals. これによれば、基板を使用することなく半導体チップの電極端子同志の間隔より広い間隔の外部接続用端子の形成が可能となる。 According to this, formation of the external connection terminals Broader spacing of the electrode terminals comrades semiconductor chip interval can be performed without using a substrate. また、前記ワイヤリング工程において、前記半導体チップの電極端子と該電極端子の真上に位置する前記外部接続用端子とを接続する前記ボンディングワイヤは、一端を電極端子と接続した後に半導体チップの電極端子が形成された面に対して直角方向へ延出させて切断すれば良い。 Further, in the wiring process, the bonding wire, semiconductor chips of the electrode terminals after connecting one end to the electrode terminals for connecting the external connection terminal located directly above the electrode terminal and the electrode terminal of the semiconductor chip it may be cut by extending the direction perpendicular to the plane but formed. 【0007】 【発明の実施の形態】以下、本発明に係る半導体装置の DETAILED DESCRIPTION OF THE INVENTION Hereinafter, a semiconductor device according to the present invention
製造方法の好適な実施の形態を添付図面に基づいて詳細に説明する。 It will be described in detail with reference to preferred embodiment of the manufacturing method in the accompanying drawings. 最初に、本発明に係る半導体装置の製造方 First, manufacturing side of the semiconductor device according to the present invention
法によって得られる半導体装置1 0について図1を用いて説明する。 It will be described with reference to FIG. 1 with the semiconductor device 1 0 obtained by law. なお、半導体チップ12の電極端子14 The electrode terminals 14 of the semiconductor chip 12
は、図2のように半導体装置10を外部接続用端子18 Is an external connection terminal of the semiconductor device 10 as shown in FIG. 2 18
が形成された面側から平面的に見ると、電極端子14が一列に並んでロ字状に半導体チップ12の能動素子面1 When There planarly viewed from the formed surface side, the active element surface 1 of the semiconductor chip 12 to the B-shaped electrode terminals 14 in a row
2aに形成されている。 It is formed in 2a. そして、電極端子14のピッチは外部接続用端子18が真上に配置できないような狭いピッチであるとする。 Then, the pitch of the electrode terminals 14 and the external connection terminal 18 is a small pitch which can not be located directly above. 【0008】 半導体装置10の基本的な構成は、半導体チップ12の電極端子14が形成された面(能動素子面とも言う)12aが樹脂封止されると共に、封止樹脂層16の半導体チップ12に対する背面(背面側)16a [0008] The basic structure of the semiconductor device 10 (also referred to as the active element surface) semiconductor chip surface on which the electrode terminals 14 are formed of 12 with 12a is sealed with a resin, the semiconductor chip 12 of the sealing resin layer 16 back to the (back side) 16a
に外部接続用端子(以下、単に端子とも言う。本実施の形態では一例としてはんだバンプ)18が装着され、封止樹脂層16内には各電極端子14と各外部接続用端子18とを電気的に接続するボンディングワイヤ(以下、 To the external connection terminal (hereinafter, simply solder as an example bumps in the form of referred. This example terminal) 18 is attached, electricity is in the sealing resin layer 16 and the electrode terminals 14 and the external connection terminals 18 bonding wires (hereinafter to connect,
単にワイヤとも言う)20が配されて成る。 Simply referred to as a wire) 20 is arranged constituted. そして、半 Then, half
導体装置10の特徴とする構成は図1に示すように、電極端子14の真上に位置せず、ピッチを広げるために電極端子14の外側に配置された各端子18と対応する電極端子14とを接続するワイヤ20が、半導体チップ1 Configuration as shown in FIG. 1, wherein the conductor device 10, not located directly above the electrode terminal 14, electrode terminals 14 corresponding to the terminals 18 disposed on the outer side of the electrode terminal 14 in order to widen the pitch wire 20 connects the door is, the semiconductor chip 1
2の電極端子14が形成された面12aと直角な平面内で略N字状に折曲されて形成されている点である。 Is that is formed is bent in a substantially N-shape in the second electrode terminal 14 is formed faces 12a perpendicular planes. 【0009】このように、電極端子14と当該電極端子14の真上から半導体装置10の中心部を基準として外側方向へずれた位置にある端子18とを接続するワイヤ20をN字状に折曲することによって、従来のように多層基板を使用することなく半導体チップ12の能動素子面12aの電極端子14同志の間隔より広い間隔で外部接続用端子18を封止樹脂層16の表面(上記背面16 [0009] folding this manner, the wire 20 for connecting the terminals 18 in the central portion of the semiconductor device 10 from above the electrode terminals 14 and the electrode terminal 14 at a position deviated outward direction with respect to the N-shaped by song, the surface of the external connection terminal 18 to the sealing resin layer 16 with a wide interval than the interval of the electrode terminals 14 comrades of the active element surface 12a of the semiconductor chip 12 without using a multi-layer substrate as in the prior art (the back 16
a)に形成することが可能となる。 It is possible to form the a). また、ワイヤ20としては、金ワイヤ、パラジウム(Pd)ワイヤ等を用いることができるが、外部接続用端子18としてはんだバンプを用いた場合には金ワイヤよりもPdワイヤを用いた方が良い。 As the wire 20, a gold wire, can be used palladium (Pd) wire or the like, it is better to use a Pd wire than gold wire in the case of using a solder bump as an external connection terminal 18. 金ワイヤは、はんだと合金化しやすいためである。 Gold wire is to easily solder alloyed. 【0010】そして、N字状に折曲して形成されたワイヤ20は、図2のように半導体装置10を外部接続用端子18が形成された面側から平面的に見ると、半導体チップ12の中心から半導体チップ12の外縁に向けて放射状に形成されることになる。 [0010] Then, the wire 20 formed by bending the N-shape when planarly viewed from the surface side of the semiconductor device 10 is an external connection terminal 18 is formed as shown in FIG. 2, the semiconductor chip 12 It will be formed radially toward the center of the outer edge of the semiconductor chip 12. また、ワイヤ20の横方向に延びる連絡部20aの長さや延び方向を変えることによって、能動素子面12aと平行な平面内で端子18 Further, by changing the length and extending direction of the contact portion 20a extending in the transverse direction of the wire 20, the terminal in the active element surface 12a parallel to the plane 18
の位置を任意に変えることが可能である。 It is possible to change the position arbitrarily. 【0011】また、図3や図4の半導体装置10のように半導体装置10を外部接続用端子18が形成された面側から平面的に見て、半導体チップ12の能動素子面1 [0011] Figure 3 and in plan view the semiconductor device 10 from the external connection terminal 18 is formed on the surface side as in the semiconductor device 10 of FIG. 4, the active element surface 1 of the semiconductor chip 12
2aに電極端子14がマトリクス状に形成されている場合も同様である。 Electrode terminal 14 2a is the same when formed in a matrix. この場合も、電極端子14と当該電極端子14の真上から半導体装置10の中心部を基準として外側方向へずれた位置にある端子18とはN字状に折曲されたワイヤ20で接続する。 Again, to connect a wire 20 which is bent in N-shaped and pin 18 in the central portion of the semiconductor device 10 from above the electrode terminals 14 and the electrode terminal 14 at a position deviated outward direction with respect . また、電極端子14の真上に当該電極端子14と接続されるべき端子18が位置する場合には、電極端子14と当該端子18とは、電極端子14から能動素子面12aに対して直角に真っ直ぐ延びるワイヤ20によって接続する。 Further, when the terminal 18 to be connected with the electrode terminal 14 directly above the electrode terminals 14 is located, the electrode terminals 14 and the terminal 18, the electrode terminal 14 at right angles with respect to the active element surface 12a connected by straight extending wire 20. そして、N字状に折曲されたワイヤ20は、同様に半導体装置10を外部接続用端子18が形成された面側から平面的に見ると、半導体チップ12の中心から半導体チップ12の外縁に向けて放射状に形成されることになる。 Then, the wire 20 which is bent in N-shaped similarly looking at the semiconductor device 10 from the external connection terminals 18 are formed side in a plane, the outer edge of the semiconductor chip 12 from the center of the semiconductor chip 12 It will be formed radially toward. そして、ワイヤ20の横方向に延びる連絡部20aの長さや延び方向を変えることによって、能動素子面12aと平行な平面内で端子18の位置を任意に変えることが可能である。 Then, by changing the length and extending direction of the contact portion 20a extending in the transverse direction of the wire 20, it is possible to arbitrarily change the position of the terminal 18 in the active element surface 12a parallel to the plane. またこのように電極端子14がマトリクス状に形成されている場合には、ある電極端子14から延びるワイヤ20の連絡部20aが隣接する電極端子14上を通過する場合もあるが、この場合には能動素子面12aから直角方向に延出するワイヤ20の長さを変えることにより、隣接するワイヤ20の連絡部20aと接触して短絡しないようにすることができる。 In the case where such the electrode terminals 14 are formed in a matrix is ​​sometimes passed over the electrode terminal 14 connecting portion 20a of the wire 20 extending from one electrode terminal 14 is adjacent, in this case by varying the length of the wire 20 extending perpendicularly from the active element surface 12a, it is possible to avoid a short circuit in contact with the contact portion 20a of the adjacent wires 20. 【0012】よって、上述したように電極端子14同志の間隔が端子18の外径よりも狭い半導体チップ12のように、従来では基板を用いなければ端子18を装着できなかった半導体チップ12であっても、封止樹脂層1 [0012] Thus, as in the narrow semiconductor chip 12 than the outer diameter of the electrode terminal 14 gap comrades the terminal 18 as described above, conventionally met semiconductor chip 12 could not be attached to the terminal 18 unless a substrate even, the sealing resin layer 1
6内においてワイヤ20を電極端子14の側方へずらしながらN字状に配線することによって半導体チップ12 The semiconductor chip 12 by wire to the N-shaped shifting the wire 20 to the side of the electrode terminal 14 in the 6
の領域内で十分な間隔をもって端子18を配置することが可能となる。 It is possible to arrange the pin 18 with sufficient spacing in the region. 【0013】さらに、半導体装置10の端子18を半導体チップ12の外縁よりもさらに外方に配置したい場合には、図5に示すように半導体チップ12と略同じ厚みをもった外形ロ字状の基材22を用意して、この基材2 Furthermore, when it is desired to place the pin 18 of the semiconductor device 10 further outward than the outer edge of the semiconductor chip 12, external shape hollow square with substantially with the same thickness as the semiconductor chip 12 as shown in FIG. 5 by providing a substrate 22, the substrate 2
2の中央孔22a内に半導体チップ12を装着し一体的に固定する。 The semiconductor chip 12 mounted in the second central hole 22a are fixed integrally. これにより、例えば外縁に近い位置にまで電極端子14が形成された半導体チップ12でも図6に示すように、封止樹脂層16を基材22の領域まで広げ、この基材22上の封止樹脂層16内にまでワイヤ2 Thus, as shown in FIG. 6, even the semiconductor chip 12 where the electrode terminals 14 are formed to a position nearly e.g. outer edge, extends the sealing resin layer 16 to the area of ​​the substrate 22, the sealing on the substrate 22 wire until in the resin layer 16 2
0を延ばして配線することによって端子18を基材22 The substrate terminal 18 by wires extending the 0 22
上の封止樹脂層16の背面16a上にも装着することが可能となる。 It becomes possible to mount on the back 16a of the upper of the sealing resin layer 16. よって、端子18の間隔を広げることができるので、端子18を形成するために電極端子14のピッチを広げる目的で用いていた回路基板を使用しないで半導体装置10を構成することが可能となる。 Therefore, it is possible to increase the distance of the terminals 18, it is possible to configure the semiconductor device 10 without using a circuit board which has been used for the purpose of widening the pitch of the electrode terminals 14 to form terminal 18. また、基材22は外形ロ字状、言い換えればリング状の形状に代えて、一方の面に半導体チップ12が装着できる凹溝が形成された台のような形状とすることも可能である。 Further, the substrate 22 is outer hollow square shape, instead of the ring-like shape in other words, it is possible to on one surface the semiconductor chip 12 is shaped like a table on which grooves can be attached are formed. 【0014】次に、この半導体装置10の製造方法について図7〜図10を用いて説明する。 [0014] Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 7-10. 第1工程は、半導体チップ12の能動素子面12aを上にして配置する。 The first step is arranged on the active element surface 12a of the semiconductor chip 12.
第2工程は、ワイヤリング工程であり、半導体チップ1 The second step is a wiring process, the semiconductor chip 1
2の能動素子面12aの各電極端子14にワイヤ(Pd Each electrode terminal 14 of the second active element surface 12a wire (Pd
ワイヤ)20を図7(a)のように立設する。 Wire) 20 is erected as shown in FIG. 7 (a). この場合、電極端子14の真上に接続されるべき端子18が配置される電極端子14(図7(a)中の真ん中の電極端子)では、ワイヤ20は公知の方法により能動素子面1 In this case, the electrode terminals 14 to which the terminal 18 to be connected directly above the electrode terminals 14 are arranged (electrode terminal in the middle in FIG. 7 (a)), the wire 20 is the active element surface by known methods 1
2aに対して直角に立設される。 It is erected at right angles to the 2a. そして、電極端子14 Then, the electrode terminals 14
の真上に接続されるべき端子18が配置されない電極端子14では、ワイヤ20は上述したように略N字状に形成され、能動素子面12aと直角となるワイヤ20の上端側は端子18が取り付けられる位置に配置される。 In the electrode terminal 14 terminal 18 to be connected directly above is not arranged, the wire 20 is formed in a substantially N-shape as described above, the upper end side of the wire 20 serving as an active element surface 12a and the right angle terminals 18 It is arranged at a position to be mounted. 【0015】このN字状のワイヤ20の配線方法についてさらに詳細に図8を用いてステップ毎に説明する。 [0015] will be described with reference to FIG. 8 in more detail how to wire the N-shaped wire 20 for each step. 1. 1. キャピラリ24から下方に延出するワイヤ20の下端をボール形成用トーチ(不図示)で溶かしてボール状に形成する図8(a) The lower end of the wire 20 extending from the capillary 24 downwardly dissolved in ball formation torch (not shown) formed on the ball-like [Figure 8 (a)]. 2. 2. キャピラリ24を下方に移動させ、ワイヤ20のボール状の下端を電極端子14に接着させる図8 Moving the capillary 24 down, adhering the ball-shaped lower end of the wire 20 to the electrode terminal 14 [Figure 8
(b) (B)]. 3. 3. ワイヤ20を繰り出しながらキャピラリ24を若干距離だけ上方へ移動させる。 While feeding the wire 20 is moved upward capillary 24 only slightly distance. なお、隣合うワイヤ20同志が接触して短絡しないように、延出させる長さを若干変えるようにする図8(c) Incidentally, adjacent the wire 20 so that each other is not shorted by contact, to vary the length to extend slightly [FIG 8 (c)]. 4. 4. キャピラリ24を横方向(電極端子14の側方) The capillary 24 laterally (side of the electrode terminal 14)
へ、端子18に対応する位置まで移動させる。 To, is moved to a position corresponding to the terminal 18. これによりワイヤ20は折曲され,連絡部20aが形成される。 Thus the wire 20 is bent, contact portion 20a is formed.
また、その時のキャピラリ24は接続されるべき端子1 The terminal 1 capillary 24 at that time to be connected
8の位置に達している図8(d) Has reached the 8 position [Figure 8 (d)]. 【0016】5. [0016] 5. その後、キャピラリ24をワイヤ20 Thereafter, the capillary 24 wire 20
を繰り出しながら若干距離だけ上方へ移動させる図8 The move slightly distance upward while feeding [8
(e) (E)]. これによりワイヤ20は再度折曲される。 Thus the wire 20 is bent again. ここで上記ステップ4における横方向の移動の際に、図8 Here, during the movement in the lateral direction in step 4, FIG. 8
(d)に示すように若干下方へも移動させ、ワイヤ20 Slightly moved downward (d), the wire 20
を全体としてN字状に形成するようにしても良い。 The may be formed as a whole N-shaped. これにより、ワイヤ20の形成領域の厚みが薄くなり、結果として半導体装置10全体が薄く形成できるようになる。 Thus, the thickness of the formation region of the wire 20 becomes thinner, the result the entire semiconductor device 10 will be able to form thin as. なお、図9に示すようにワイヤ20の折曲部分での折曲角度を90度にして横方向に延びる連絡部20aを能動素子面12aと略平行に形成させるようにしても良いし、また図10に示すようにワイヤ20全体を横S字状に形成しても良い。 Incidentally, it may also be a contact portion 20a extending transversely to the active element surface 12a substantially parallel to the bending angle in the bent portion of the wire 20 in the 90 degrees as shown in FIG. 9, also it may be formed across the wire 20 in the transverse S-shape as shown in FIG. 10. ワイヤ20の形状を表す「N字状」という言葉の中には、これら各対応も含まれるものとする。 Some word representing the shape of the wire 20 "N-shaped" is intended to also include those each corresponding. 【0017】6. [0017] 6. キャピラリ24を上方へ移動させた結果、キャピラリ24の下端とワイヤ20の2度目の折曲部分との間に隙間が生ずる。 Result of moving the capillary 24 upward, a gap is generated between the second time of the bent portion of the lower end and the wire 20 of the capillary 24. そしてこの隙間に位置するワイヤ20を図8(e)に示すようにクランパ26で掴み固定し、キャピラリ24を上方へ移動させることによって、クランパ26とキャビラリ24との間でワイヤ2 Then the wire 20 located in the gap gripping fixed with the clamper 26 as shown in FIG. 8 (e), by moving the capillary 24 upward, the wire 2 between the clamper 26 and the Kyabirari 24
0を切る。 Turn off the 0. これにより、下端が電極端子14に接続されたN字状のワイヤ20が形成される図8(f) 上記1〜6のステップを端子18との位置がずれた全電極端子14に対して行い、N字状のワイヤ20を形成する。 Thus, the total electrode terminal 14 whose position has deviated to the FIG. 8 (f)] terminal 18 steps of the 1-6 lower end N-shaped wire 20 connected to the electrode terminal 14 is formed performed to form an N-shaped wire 20. 【0018】第3工程は、樹脂封止工程であり、半導体チップ12の能動素子面12aを、各ワイヤ20が樹脂で隠れるように樹脂封止する。 A third step is a resin sealing step, the active element surface 12a of the semiconductor chip 12, the wires 20 are sealed with resin so as to be hidden by the resin. これにより、半導体チップ12の能動素子面12a上に封止樹脂層16が形成される図7(b) Thus, the sealing resin layer 16 is formed on the active element surface 12a of the semiconductor chip 12 [FIG. 7 (b)]. 第4工程は、研磨工程であり、封止樹脂層16の半導体チップ12に対する背面16aを半導体チップ12の能動素子面12aと平行となるように平面に研磨してワイヤ20の端部(上端)を露出させる図7(c) Fourth step, polishing is a process, the ends of the wire 20 are polished to a plane in parallel with the active element surface 12a of the semiconductor chip 12 to the back 16a to the semiconductor chip 12 of the sealing resin layer 16 (the upper end) exposing the FIG 7 (c)]. 第5工程は、研磨されて平面に形成された封止樹脂層16の表面に、当該表面に露出するワイヤ20の上端部に対応させて凹部28をドリル等を用いてザグリを入れて形成する。 The fifth step is the polished the surface of the sealing resin layer 16 formed on the flat surface, placed counterbore formed using a so as to correspond to the upper end portion of the wire 20 exposed to the surface recess 28 a drill or the like . 凹部28の形状は半球状、多角形状等、端子18の形状に合わせて種々の形状が採用し得る。 Recess 28 of the shape of a hemispherical shape, a polygonal shape, various shapes can be adopted according to the shape of the terminal 18. これにより、ワイヤ20の上端は凹部2 Thus, the upper end of the wire 20 recess 2
8の内面に露出する構成となる図7(d) A configuration exposed to 8 the inner surface of FIG. 7 (d)]. 【0019】第6工程は、凹部28に外部接続用の端子18(はんだバンプ)を装着し、端子18とワイヤ20 The sixth step is to mount the terminals 18 for external connection (solder bumps) in the recess 28, the terminal 18 and the wire 20
とを電気的に接続させる図7(e) Preparative to electrically connect [FIG 7 (e)]. これにより、 As a result,
半導体装置10が完成する。 The semiconductor device 10 is completed. なお、端子18の形態によって封止樹脂層16の表面に形成している凹部28が不要となる場合もある。 In some cases, the recesses 28 are formed on the surface of the sealing resin layer 16 by the form of the terminal 18 is not required. 【0020】以上、本発明の好適な実施の形態について種々述べてきたが、本発明は上述する実施の形態に限定されるものではなく、発明の精神を逸脱しない範囲で多くの改変を施し得るのはもちろんである。 [0020] Having thus various described preferred embodiments of the present invention, the present invention is not intended to be limited to the embodiments set above, it may subjected to many modifications without departing from the spirit of the invention the is a matter of course. 【0021】 【発明の効果】本発明に係る半導体装置の製造方法によれば、基板を使用することなく半導体チップの能動素子面の電極端子同志の間隔より広い間隔の外部接続用端子部の形成が可能となる。 The semiconductor equipment according to the present invention according to the manufacturing method, the external connection terminal portions of the widely spaced than the interval of the electrode terminals comrades of the active element surface of the semiconductor chip without using a substrate formation is possible. よって、高価な基板を使用しないで済み、半導体装置のコスト低減が図れる。 Thus, it finished without using an expensive substrate, thereby the cost of the semiconductor device.

【図面の簡単な説明】 【図1】本発明に係る半導体装置の製造方法で得られる Obtained by the method of manufacturing a semiconductor device according to BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] The present invention
半導体装置の一実施の形態の内部構成を示す図2のX− Of Figure 2 showing the internal structure of an embodiment of a semiconductor device X-
X断面図である(半導体チップに電極端子がロ字状に形成された場合)。 X is a cross-sectional view (when the electrode terminal is in the shape of a rectangular semiconductor chip). 【図2】本発明に係る半導体装置の製造方法で得られる Obtained by the method of manufacturing a semiconductor device according to the invention; FIG
半導体装置の一実施の形態を端子部側から見た平面図である。 An embodiment of the semiconductor device is a plan view seen from the terminal side. 【図3】本発明に係る半導体装置の製造方法で得られる Obtained by the method of manufacturing a semiconductor device according to the present invention; FIG
半導体装置の他の実施の形態の内部構成を示す図4のX X of Figure 4 showing the internal structure of another embodiment of a semiconductor device
−X断面図である(半導体チップに電極端子がマトリクス状に形成された場合)。 -X is a sectional view (when the electrode terminals are formed in a matrix on a semiconductor chip). 【図4】本発明に係る半導体装置の製造方法で得られる Obtained by the method of manufacturing a semiconductor device according to the present invention; FIG
半導体装置の他の実施の形態を端子部側から見た平面図である。 Another embodiment of the semiconductor device is a plan view seen from the terminal side. 【図5】さらなる他の実施の形態において、半導体チップを基材に装着する状態を示す斜視図である。 [5] in the form of yet another embodiment is a perspective view showing a state of mounting the semiconductor chip on the substrate. 【図6】図5のさらなる他の実施の形態の内部構造を示す断面図である。 6 is a sectional view showing an internal structure of still another embodiment of FIG. 【図7】本発明に係る半導体装置の製造方法を示す説明図である。 7 is an explanatory diagram showing a method for manufacturing a semiconductor device according to the present invention. 【図8】図7のワイヤリング工程をステップ単位で説明するための説明図である。 The [8] 7 of wiring process is an explanatory diagram for explaining in units of steps. 【図9】ボンディングワイヤの他の形状を示す説明図である。 9 is an explanatory view showing another shape of the bonding wire. 【図10】ボンディングワイヤのさらなる他の形状を示す説明図である。 10 is an explanatory view showing a further other shape of the bonding wire. 【符号の説明】 10 半導体装置12 半導体チップ12a 電極端子が形成された面(能動素子面) 14 電極端子16 封止樹脂層16a 背面18 外部接続用端子20 ボンディングワイヤ [Reference Numerals] 10 semiconductor device 12 semiconductor chip 12a electrode terminals are formed surface (active element surface) 14 electrode terminal 16 sealing resin layer 16a back 18 terminal 20 bonding wires for external connection

Claims (1)

  1. (57)【特許請求の範囲】 【請求項1】 半導体チップの電極端子が形成された面が樹脂封止されると共に、封止樹脂層の前記半導体チップに対する背面側に外部接続用端子が装着され、前記封止樹脂層内に前記電極端子と前記外部接続用端子とを電気的に接続するボンディングワイヤが配されて成る半導体装置の製造方法において、 一端が電極端子と接続されたボンディングワイヤを前記 (57) with Patent Claims: 1. A semiconductor chip surface on which the electrode terminals are formed of resin-sealed, the external connection terminals on the rear side with respect to the semiconductor chip of the encapsulating resin layer attached It is, in the manufacturing method of a semiconductor device in which a bonding wire is disposed to electrically connect the electrode terminal and the terminal for external connection to the sealing resin layer, a bonding wire having one end connected to the electrode terminal said
    半導体チップの電極端子が形成された面に対して直角方 Perpendicular way with respect to the electrode terminals of the semiconductor chips are formed surface
    向へN字状に延出させて切断するワイヤリング工程と、 前記半導体チップの電極端子が形成された面及び該電極 A wiring step of cutting by extending the N-shaped to counter the surface electrode terminals are formed of the semiconductor chip and the electrode
    端子に接続されたボンディングワイヤを樹脂封止する樹 Tree that the bonding wire connected to the terminal resin-sealed
    脂封止工程と、 前記封止樹脂層の前記半導体チップ側に対する背面側を And Aburafutome step, the back side with respect to the semiconductor chip side of the sealing resin layer
    研磨して前記ボンディングワイヤの端部を露出させる研 Polished and Labs exposing the end portions of the bonding wire
    磨工程と、 前記ボンディングワイヤの端部に外部接続用端子を装着 Mounting and polishing steps, the external connection terminal to an end of the bonding wire
    する外部接続用端子装着工程とを有する ことを特徴とする半導体装置の製造方法 The method of manufacturing a semiconductor device characterized by having an external connection terminal mounting step for. 【請求項2】 前記ワイヤリング工程において、前記半 Wherein in said wiring step, the half
    導体チップの電極端子と該電極端子の真上に位置する前 Before positioned directly above the electrode terminal and the electrode terminal conductor chips
    記外部接続用端子とを接続する前記ボンディングワイヤ The bonding wire for connecting the Kigaibu connection terminal
    は、一端を電極端子と接続した後に半導体チップの電極 The semiconductor chip after connecting one end to the electrode terminal electrodes
    端子が形成された面に対して直角方向へ延出させて切断 Cut is extended to the direction perpendicular to the terminals are formed surface
    することを特徴とする請求項1記載の半導体装置の製造 Manufacturing a semiconductor device according to claim 1, characterized in that
    方法 Method.
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