JP2013219385A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which deals with improvements of electric characteristics resulting from the downsizing, in particular, narrowing pitches and using a number of pins, and high speed operation.SOLUTION: A semiconductor device includes: a pad 2 provided on a semiconductor chip 1C3; a passivation film 3 having an opening on the pad 2 and provided on the semiconductor chip 1C3; a passivation film 5 having an opening on the pad 2 and provided on the pad 2 and the passivation film 3; and re-wiring 7 electrically connected with the pad 2 and provided on the passivation film 5; a pad 26 formed on the rewiring 7; and a wire 33b connected with the pad 26.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and in particular, is effective when applied to the manufacture of a semiconductor device having a conductive film formed by plating on a pad after a probe inspection process performed by bringing a probe needle into contact with the pad. Technology.

  In a probe inspection process (test process) of a semiconductor device provided with a semiconductor circuit (eg, LSI), a probe needle (probe) is brought into contact with the surface of a pad formed on a semiconductor wafer to measure electrical characteristics. Yes. Since this probe needle is made of a hard metal such as W (tungsten) and has a pointed tip, it is used as a probe mark on the surface of a pad made of, for example, Al (aluminum) in the probe inspection process. It will cause trauma.

  In JP 2007-318014 A (Patent Document 1), a pad having two regions is inspected by contacting a probe needle in one region, and a bump electrode is formed in the other region without a probe mark. Technology is disclosed.

JP 2007-31814 A

  1A and 1B are schematic views showing a cross section of a main part of a semiconductor device in a manufacturing process examined by the present inventors, in which FIG. 1A shows a state in which a process for forming a semiconductor circuit and a pad is completed, and FIG. A state in which probing is performed in the process, (c) shows a state in which rewiring is formed. In the figure, 1W is a semiconductor wafer, 2 is a pad, 3 is a passivation film, 4 is a probe needle, 5 is a passivation film, 6 is a seed film, 7 is a rewiring, 8 is a passivation film, and 9 is a bump electrode. is there.

  In the process of manufacturing the semiconductor device, there is a probe inspection process using the probe needle 4 in order to perform the characteristic inspection of the semiconductor circuit formed on the main surface (element formation surface) of the semiconductor wafer 1W. This probe inspection process is performed in a state where the probe needle 4 is in contact with a plurality of pads 2 (FIG. 1A) formed on each device formation region (region to be a semiconductor chip later, chip region). (FIG. 1 (b)). Therefore, probe marks 100 (traumas and depressions) due to the probe needles 4 are formed on the surface of each pad 2 in each device formation region after the probe inspection process. FIG. 1 shows a case where a cantilever method is applied to probing.

  In recent years, with the miniaturization of semiconductor devices, the pitch of pads (pad pitch) in a semiconductor chip tends to be narrowed. Therefore, it is necessary to reduce the size of each pad in order to cope with the increase in functionality and the number of pins. Thereby, when a probe test | inspection is performed with respect to such a pad, the magnitude | size of the probe trace with respect to a pad looks large.

  For example, when a wire (hereinafter simply referred to as a wire) is connected to a pad on which such probe marks are formed, the contact area between the wire and the pad is reduced by the amount of probe marks formed. The problem of poor connection occurs. Therefore, as shown in Patent Document 1, it is conceivable to connect a wire at a position avoiding the formed probe mark.

  On the other hand, as a countermeasure for narrowing the pitch of the semiconductor device, it is effective to change the pitch of the pad by a rewiring technique. Rewiring technology (WPP (Wafer Process Package) technology, also called WLP (Wafer Level Package) technology) is a technology that integrates a normal wafer process (pre-process) and a package process (post-process), and is a semiconductor wafer. After completing the packaging in this state, the semiconductor chips are separated into individual pieces. That is, a pad corresponding to a narrow pitch is formed by a wafer process miniaturization technique, and further, a rewiring electrically connected to the pad is formed to form a semiconductor chip converted into a wide pitch.

  The inventors of the present application are examining not a semiconductor device that connects wires to pads of a semiconductor chip, but a semiconductor device that converts the pitch of pads of a semiconductor chip using this redistribution technique. The following problems were found in such a semiconductor device.

  First, in the rewiring technique, a seed film 6 that is a conductive film is formed on a pad 2 formed in each device formation region using a sputtering method, and a rewiring 7 (wiring layer) is formed using a plating method. To do. Next, the pad 2 is pulled out to connect to the outside of the semiconductor chip up to a desired position (vacant area) on the main surface of the semiconductor wafer (which will later become a semiconductor chip). That is, since the rewiring 7 is formed by a plating method, even if the probe mark 100 is formed on the pad 2, the rewiring 7 is formed on the pad 2 so as to close the probe mark 100. Therefore, if the rewiring technique is used, the rewiring 7 and the pad 2 can be connected even if the probe mark 100 is formed large on the pad 2.

  However, the present inventors have newly discovered the following problems. First, the inventor of the present application noticed that a convex portion 101 like a hump was formed on the surface of the rewiring 7 as shown in FIG. As a result of analyzing the convex portion 101, it was found that a void 102 (gap) was generated at the interface between the surface of the pad 2 and the rewiring 7 as shown in FIG.

  At first glance, the rewiring 7 formed by the plating method seems to have the probe trace 100 closed by the rewiring 7, but inside the plating film (plating layer) so as to block the upper portion of the probe trace 100 (dent). ) Grows, it is considered that the void 102 was formed. When the region (including the margin) where the probe 4 is in contact with the region (including the margin) where the seed film 6 (conductive film) is formed on the pad 2 including the margin is equivalent to the current path, If such a void 102 is formed, the resistance as a wiring becomes high, and there is a possibility that a signal propagation speed is delayed.

  Further, the cutting of the seed film 6 due to the level difference of the probe mark 102 prevents the subsequent uniform plating growth. For this reason, voids are formed inside the plating, and there are concerns about a decrease in contact area, a decrease in connectivity, a deterioration in surface flatness, a decrease in coverage of the upper passivation film 8 and a short circuit with an adjacent portion.

  An object of the present invention is to provide a technique for downsizing a semiconductor device, in particular, a narrow pitch.

  Another object of the present invention is to provide a technique for increasing the number of pins of a semiconductor device.

  Another object of the present invention is to provide a technique for improving electrical characteristics accompanying the increase in speed of a semiconductor device.

  Another object of the present invention is to provide a technique for improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In one embodiment of the present invention, a pad having a probe region and a connection region is formed on a semiconductor wafer, and further, a first insulation that exposes the probe region and the connection region is formed, and then a probe is formed in the probe region. Electrical characteristics are measured by bringing a needle into contact with each other to form a conductive film that covers the first insulating film and the connection region on the pad.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one embodiment of the present invention, rewiring can be formed using a conductive film that does not have a void due to probe marks. As a result, it is possible to provide a technique for miniaturization of the semiconductor device, in particular, a technique for narrowing the pitch. In addition, a technique for increasing the number of pins of a semiconductor device can be provided. In addition, a technique for improving the reliability of the semiconductor device can be provided. In addition, it is possible to provide a technique for improving electrical characteristics accompanying the increase in speed of a semiconductor device.

2A and 2B are schematic views showing a cross-section of a main part of a semiconductor device in a manufacturing process studied by the present inventors, in which FIG. 1A shows a state in which a semiconductor circuit and pad forming process has been completed, and FIG. (C) shows a state in which rewiring is formed. It is a schematic diagram which shows the plane of the semiconductor device in one embodiment of this invention. FIG. 3 is a schematic diagram illustrating a main part of a cross section of the semiconductor device illustrated in FIG. 2. FIG. 3 is a schematic diagram showing a main part of a plane of the semiconductor device shown in FIG. 2. It is a figure which shows the flow of the manufacturing process of the semiconductor device in one embodiment of this invention. It is a schematic diagram which shows the plane of the semiconductor wafer in one embodiment of this invention. FIG. 6 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process shown in FIG. 5. FIG. 8 is a schematic view showing the main part of the cross section of the semiconductor device in the manufacturing process following FIG. 7. FIG. 9 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process following FIG. 8. FIG. 10 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process following FIG. 9. FIG. 11 is a schematic diagram illustrating a main part of a cross section of a semiconductor device during a manufacturing process subsequent to FIG. 10; FIG. 12 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process following FIG. 11. It is a schematic diagram which shows the mounting state to the mounting board | substrate of the semiconductor device in one embodiment of this invention. It is a schematic diagram which shows the plane of the semiconductor device in other embodiment of this invention. FIG. 15 is a schematic diagram illustrating a main part of a cross section of the semiconductor device illustrated in FIG. 14. FIG. 15 is a schematic diagram illustrating a main part of a plane of the semiconductor device illustrated in FIG. 14. The semiconductor device shown in FIG. 14 is connected to the bump electrode by wire bonding, and the plurality of pads of the semiconductor chip and the plurality of electrodes of the substrate on which the semiconductor chip is mounted are electrically connected via the plurality of wires. It is a schematic diagram which shows the principal part of a cross section. It is a schematic diagram which shows the connection state of the wire in planar view, (a) is the state connected with the pad via the bump electrode, (b), (c) is the state connected directly to the pad. It is a schematic diagram which shows the principal part of the cross section of the semiconductor device in the manufacturing process in other embodiment of this invention. FIG. 20 is a schematic view showing the main part of the cross section of the semiconductor device in the manufacturing process following FIG. 19. FIG. 21 is a schematic view showing a substantial part of a cross section of a semiconductor device in the manufacturing process following FIG. 20. FIG. 22 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process following FIG. 21. It is a schematic diagram which shows the principal part of the cross section of the semiconductor device in the manufacturing process in other embodiment of this invention. FIG. 24 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process following FIG. 23. It is a schematic diagram which shows the principal part of the cross section of the semiconductor device in other embodiment of this invention, (a) is the structure of rewiring and a solder bump electrode, (b) is the structure of a stud bump electrode, (c) is The case of rewiring and pad structure is shown. FIG. 26 is a schematic diagram showing the main part of the plane of the semiconductor device shown in FIG. It is a schematic diagram which shows the principal part of the cross section of the semiconductor device in the manufacturing process in other embodiment of this invention. FIG. 28 is a schematic view showing a main part of a cross section of the semiconductor device in the manufacturing process following FIG. 27. FIG. 29 is a schematic view showing a substantial part of a cross section of a semiconductor device in the manufacturing process following FIG. 28. It is a schematic diagram which shows the principal part of the plane of the semiconductor device in other embodiment of this invention, (a) is the state in which the opening part on a pad is constricted, (b) is the state in which the opening part is isolate | separated It is shown. It is a schematic diagram which shows the principal part of the plane of the semiconductor device in other embodiment of this invention, (a) is the state which arrange | positioned the probe area | region in zigzag form, (b) is the state which has arrange | positioned the probe area | region in the straight form It is shown. It is a schematic diagram which shows the principal part of the plane of the semiconductor device in other embodiment of this invention. It is a schematic diagram which shows the principal part of the plane of the semiconductor device in other embodiment of this invention, When the planar shape of a bump electrode is made into the rectangular shape in (a), When made into the polygonal shape in (b), ( c) shows a case of a circular shape. It is a schematic diagram which shows the principal part of the cross section of the semiconductor device in other embodiment of this invention, (a) isolate | separates a probe area | region and a connection area | region, (b) shows the case where a probe area | region is included in a connection area | region. Show. It is a schematic diagram which shows the cross section of the semiconductor device in the manufacturing process in other embodiment of this invention. FIG. 36 is a schematic view showing a cross section of the semiconductor device in the manufacturing process subsequent to FIG. 35. FIG. 37 is a schematic view showing a cross section of the semiconductor device in the manufacturing process subsequent to FIG. 36. FIG. 38 is a schematic view showing a cross section of the semiconductor device in the manufacturing process subsequent to FIG. 37. FIG. 39 is a schematic view showing a cross section of the semiconductor device in the manufacturing process subsequent to FIG. 38. It is a schematic diagram which shows an example of the connection of the wire in a laminated chip. It is a schematic diagram which shows another example of the connection of the wire in a laminated chip.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof may be omitted. In the drawings for explaining the following embodiments, hatching may be given even in plan views for easy understanding of the configuration.

(Embodiment 1)
First, the structure of the semiconductor device in this embodiment will be described with reference to the drawings. 2 is a schematic diagram illustrating a plan view of the semiconductor device according to the present embodiment, FIG. 3 is a schematic diagram illustrating a main part of a cross section of the semiconductor device illustrated in FIG. 2, and FIG. 4 illustrates the semiconductor device illustrated in FIG. It is a schematic diagram which shows the principal part of a plane. FIG. 4 shows a state in which a part thereof is removed.

  The semiconductor device in the present embodiment is composed of a semiconductor chip 1C having a BGA (Ball Grid Array) structure. Ball-shaped bump electrodes 9 arranged in a matrix are provided at the center of the semiconductor chip 1C. The bump electrode 9 is provided as an external electrode of the semiconductor chip 1C so as to protrude from the passivation film 8 serving as a surface protective film. In FIG. 2, the pad (electrode) 2 provided on the outer peripheral portion of the semiconductor chip 1 </ b> C and the rewiring 7 that electrically connects the pad 2 and the bump electrode 9 are covered with the passivation film 8. These are illustrated by dotted lines.

  A semiconductor circuit (for example, LSI) (not shown) is provided on the main surface (element formation surface) of the rectangular semiconductor chip 1C. The semiconductor circuit is formed by a well-known technique in a so-called pre-process (ordinary wafer process), and includes, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a resistor, a capacitor, and a wiring that electrically connects them.

  In addition, pads 2 that are electrically connected to the wirings constituting the semiconductor circuit and are provided on the semiconductor chip 1C (semiconductor circuit) are provided on the outer periphery of the rectangular semiconductor chip 1C. The pad 2 has a probe region 10A on the outer peripheral side of the semiconductor chip 1C and a connection region 10B on the central side as shown by two regions partitioned by broken lines in FIG.

  Further, a passivation film 3 is provided on the semiconductor chip 1C (semiconductor circuit). The passivation film 3 is made of, for example, an inorganic insulating silicon nitride film, and has an opening 11 on the pad 2 in the probe region 10A and the connection region 10B. A passivation film 5 is provided on the pad 2 and the passivation film 3. The passivation film 5 is made of, for example, a polyimide film of an organic insulating film, and has an opening 12 having a square planar shape on the pad 2 in the connection region 10B.

  As described with reference to FIG. 1, the probe mark 4 is generated on the pad 2 of the probe region 10A provided on the outer peripheral portion side of the semiconductor chip 1C from the connection region 10B. 100 (trauma, dent) is present. On the other hand, a rewiring 7 is electrically connected to the pad 2 and provided on the connection region 10B and the passivation film 5 via a seed film 6 (conductive film). Briefly, in the pad (electrode) 2 exposed from the passivation film (insulating film) 3, the flatness is higher than the region where the probe mark 100 is not formed (probe region (first region) 10A where the probe mark is formed). The wiring layer (seed film 6 and rewiring 7), which is a conductive member, is connected to the high connection region (second region) 10B). Further, a rewiring 7 exists from the connection region 10B to the central portion side of the semiconductor chip 1C through a seed film 6 (conductive film). Thus, on the surface of the pad 2, the connection region 10 </ b> B is provided on the center side of the semiconductor chip 1 </ b> C, and the other end of the rewiring 7 opposite to the one end connected to the pad 2 is connected to the semiconductor chip. The following effects can be obtained by pulling out and arranging the central portion on the main surface of 1C.

That is, the wiring layer (the seed film 6 and the rewiring 7) that is a conductive member is connected to a flat region where the probe mark 100 is not formed on the surface of the pad 2, so that the probe mark ( Since the gap 100 does not occur, the electrical characteristics of the semiconductor device can be improved, but between the connection region 10B and the central portion of the semiconductor chip 1C (under the path where the wiring layer (seed film 6 and rewiring 7) is disposed). When the probe region 10A is present in the uppermost part of the wiring layer, as described above, a part of the wiring layer is pushed upward by the protrusion 101 like a hump formed on the probe region 10A, and the passivation film on the outermost surface to be formed later is formed. The (insulating film) 8 is exposed, and the reliability of the semiconductor device may be reduced. Even if the connection region 10B is arranged on the peripheral edge (side) side of the semiconductor chip 1C, the wiring layer (seed film 6 and rewiring 7) is further from the pad 2 to the peripheral edge (side) side of the semiconductor chip 1C. If it can be drawn, there is no possibility that a part of the wiring layer described above is exposed from the passivation film 8. However, since the plurality of pads (electrodes) 2 are provided along each side of the semiconductor chip 1C having a square planar shape, a wiring layer is provided between the pad 2 and the peripheral edge (side) of the semiconductor chip 1C. It is difficult to arrange the other end of the.
Therefore, as shown in the first embodiment, in the pad 2 having a rectangular planar shape, the connection region 10B is provided close to the short side located on the center side of the main surface of the semiconductor chip 1C, thereby providing wiring. Since the problem that a part of the layer is exposed from the passivation film 8 can be suppressed, the reliability of the semiconductor device can also be improved.

  Further, a passivation film 8 serving as a protective film on the outermost surface is provided on the rewiring 7 and the passivation film 5. The passivation film 8 has an opening 13 on a part of the rewiring 7. On part of the rewiring 7, a ball-shaped bump electrode 9 protruding from the opening 13 is provided.

  The semiconductor chip 1 </ b> C configured in this way can have bump electrodes 9 converted to a wide pitch through rewiring 7 electrically connected to the pads 2 corresponding to the narrow pitch. That is, the semiconductor device according to the present embodiment can electrically connect the semiconductor circuit and the bump electrode 9 of the external electrode via the pad 2 and the rewiring 7 to cope with downsizing, in particular, narrow pitch. it can.

  Further, in the present embodiment, a probe region 10A that is a region (including a margin) to which the probe 4 is contacted, and a region (that is where a seed film 6 (conductive film) is formed on the pad 2 including the margin) And a connection region 10B including a margin) on the pad 2. Therefore, due to the influence of the probe mark 100 generated in the probe inspection process, the rewiring 7 and / or the seed film 6 can be prevented from being chipped as described with reference to FIG. Exposure of the rewiring 7 from the passivation film 8 can be suppressed.

  In the present embodiment, the planar shape of the pad 2 is a rectangular shape having long sides from the outer peripheral side to the central side of the semiconductor chip 1C. For example, the dimension 2a of the pad 2 is 130 μm, the dimension 2b is 75 μm, and the pitch dimension 2c of the pad 2 is 80 μm. Thus, by making the planar shape of the pad 2 rectangular, it is possible to cope with downsizing of the semiconductor device, in particular, narrow pitch. Furthermore, in the present embodiment, the pads 2 are provided in a staggered manner on the outer periphery of the rectangular semiconductor chip 1C. Thereby, it is possible to cope with a narrower pitch. For example, the pitch dimension 2d between the outer pad 2 and the inner pad 2 is 40 μm.

  As described above, according to the present embodiment, it is possible to cope with downsizing of the semiconductor device, in particular, narrowing of the pitch, so that the semiconductor circuit provided in the semiconductor chip 1C can be highly functionalized, and the multi-pin associated therewith. (Multi-input output) can also be supported.

  In addition to the method described in this embodiment, a method of dividing the connection region between the probe region and the conductive member (wire, rewiring) is also conceivable. In this case, the semiconductor device can be reduced in size by separating each region. Cannot be realized. In addition, the polyimide film that exposes a part of the pad is an organic insulating film having a hardness lower than that of the metal, so that the processing accuracy is worse than that of the metal material. Become. Therefore, when the pad is formed separately for each region, it is necessary to form a large pad in consideration of the processing accuracy of this polyimide film, and it is formed by one pad made of a rectangle as shown in this embodiment. It is not suitable for downsizing of a semiconductor device.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. FIG. 5 is a diagram showing the flow of the manufacturing process of the semiconductor device in the present embodiment, FIG. 6 is a schematic diagram showing the plane of the semiconductor wafer in the present embodiment, and FIGS. 7 to 12 are shown in FIG. It is a schematic diagram which shows the principal part of the cross section of the semiconductor device in a manufacturing process.

  First, a semiconductor wafer 1W having a device formation region 50 in which a semiconductor circuit is formed as shown in FIG. 6 is prepared (S10). In the figure, a scribe area 51 is shown. In a later step, individual semiconductor chips 1C are cut out from the semiconductor wafer 1W along the scribe region 51.

  More specifically, a semiconductor circuit (semiconductor element), a pad (electrode) 2 electrically connected to the semiconductor circuit, and a passivation film formed on the pad 2 so as to expose a part of the pad 2 are exposed. A semiconductor wafer 1W having a plurality of device forming regions 50 (chip regions) having (insulating film) 3 is prepared. Here, the pad 2 has a probe region (first region) 10A on the outer peripheral side of the device formation region 50, and is adjacent to the probe region 10A, and is connected to the center side of the chip region from the probe region 10A (second region). Region) 10B. The semiconductor wafer 1W is, for example, a planar circular single crystal Si substrate. A planar rectangular semiconductor chip 1C (see FIG. 2) is cut out from each of a plurality of device formation regions of the semiconductor wafer by dicing. The semiconductor wafer 1W is not limited to a Si substrate, and may be a compound semiconductor substrate such as a GaAs substrate or a SiC substrate.

  Subsequently, various semiconductor elements such as n-channel and p-channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors), resistors, capacitors, and wirings for electrically connecting them are formed on the main surface of the semiconductor wafer 1W by a well-known technique. A semiconductor circuit composed of (multilayer wiring) is formed (S20).

  Subsequently, as shown in FIGS. 2 and 7, a probe region (first region) 10A is adjacent to the outer peripheral portion of the device formation region, and is adjacent to the probe region 10A, and is closer to the center of the device formation region than the probe region 10A. The pad 2 having the connection region (second region) 10B is electrically connected to the wiring constituting the semiconductor circuit and formed on the semiconductor wafer 1W (S30). As shown in FIGS. 2 and 4, the pad 2 is formed in a rectangular shape having a long side from the outer peripheral side to the central side of the device formation region (which will later become the semiconductor chip 1C). Also, the dummy pads 2A shown in FIG. 4 are formed in alignment with the same size as the probe region 10A of the pads 2. The dummy pad 2A is formed in a row of the probe region 10A of the pad 2 for the purpose of controlling the probing position, and is in a floating state.

  The pad 2 has, for example, aluminum (Al) as a main conductive layer. For example, a structure in which the upper and lower sides of the Al film serving as the main conductive layer are sandwiched between barrier conductive films made of a laminated film of a Ti film and a TiN film may be employed. For such wiring, the lower barrier conductive film, the Al film, and the upper barrier conductive film are sequentially deposited, and then the laminated film is dry-etched using a photoresist film patterned by photolithography as a mask. By doing so, it can be formed.

  Subsequently, a passivation film 3 (first insulating film) is formed on the semiconductor wafer 1W (S40). The passivation film 3 is composed of, for example, a laminated film of a silicon oxide film and a silicon nitride film which are inorganic insulating films, and the laminated film can be formed by, for example, a plasma CVD (Chemical Vapor Deposition) method. Next, dry etching is performed using a photoresist film (not shown) patterned by photolithography as a mask to expose the probe region 10A and the connection region 10B of the pad 2 from the passivation film 3. As a result, the passivation film 3 has the opening 11. Of the opening 11, the area where the probe area 10A is exposed is, for example, 60 μm (dimension 11a) × 70 μm (dimension 11c), and the area where the connection area 10B is exposed is, for example, 60 μm (dimension 11b) × 70 μm (dimension 11c). Can do. Further, the opening 14 is formed on the dummy pad 2A shown in FIG. 4 with the same size as the probe region 10A of the opening 11.

  Subsequently, a probe inspection of the semiconductor circuit is performed (S50). For example, as shown in FIG. 8, various electrical characteristics are measured by bringing a cantilever probe needle 4 into contact with the pad 2 in the probe region 10A. At this time, a probe mark 100 (trauma) due to the probe needle 4 is formed on the surface of the pad 2. The probe needle 4 is made of a hard metal such as W (tungsten), and has a pointed tip. Therefore, the probe needle 4 is damaged as a probe mark 100 on the surface of the pad 2 having an Al film as a main conductive layer. End up.

  In the present embodiment, the planar shape of the pad 2 is rectangular, the probe region 10A is provided on the outer peripheral side of the semiconductor chip 1C, the connection region 10B is provided on the central side, and the probe needle 4 is brought into contact only with the probe region 10A. Yes. Therefore, the probe mark 100 is present on the pad 2 in the probe region 10A.

  In the present embodiment, simultaneously with the formation of the pad 2, an aligned dummy pad 2A having the same size as the probe region 10A of the pad 2 is also formed (see FIG. 4). Since the dummy pad 2A is targeted in the probe inspection process, the probe needle 4 can be prevented from shifting from the probe region 10A to the connection region 10B. That is, the probe mark 100 is present on the pad 2 in the probe region 10A.

  In addition to inspection at normal temperature, high temperature, and low operation guarantee temperature (for example, −40 ° C. to 125 ° C.), probe inspection requires inspection according to function due to high functionality of the semiconductor device. (Tester) brings the probe needle 4 into contact with the same pad 2 a plurality of times. The probe inspection also includes so-called wafer level burn-in. For example, in a high-temperature environment (high-temperature baking) near the solder melting point (200 ° C. or higher), the pad 2 in the probe region 10A for a long time (for example, several hours). A voltage is also applied to the semiconductor circuit by bringing the probe needle 4 into contact therewith. For this reason, it is considered that the probe mark 100 also becomes large. Even in this case, in this embodiment, the probe mark 100 can be present on the pad 2 in the probe region 10A.

  In addition, although the probe inspection can be performed after the bump electrode 9 is formed, the high temperature baking temperature is limited by the influence of the solder surface state (oxidation) change due to the temperature history and the melting point of the solder. It is not possible to perform the same inspection as the probe inspection performed in step 1.

  Subsequently, a passivation film 5 (second insulating film) is formed on the semiconductor wafer 1W (S60). The passivation film 5 is made of, for example, a polyimide film that is an organic insulating film, and can be formed by, for example, a spin coating method. Next, as shown in FIG. 9, wet etching is performed using a photoresist film (not shown) patterned by the photolithography technique as a mask to expose the connection region 10 </ b> B of the pad 2 from the passivation film 5. As a result, the passivation film 5 has the opening 12. Of the opening 12, the region where the connection region 10B is exposed has a square planar shape, and can be, for example, 45 μm (dimension 12a) × 45 μm (dimension 12b).

  Subsequently, as shown in FIG. 10, a seed film 6 (wiring layer, conductive film, plating layer) is formed on the connection region 10B and the passivation film 5 and electrically connected to the pad 2 (S70). The seed film 6 is a seed film of a conductive film that is formed using a plating method in a later step, and is composed of a Pd film or the like by an electroless plating method. The seed film 6 may be composed of a Pd / Ti film, a Ti film, or a TiN film deposited by a sputtering method. These films are also Cu diffusion barrier conductive films.

  Subsequently, as shown in FIG. 11, after a resist film is applied on the semiconductor wafer 1W, the resist film is patterned by a photolithography technique to expose a part of the seed film 6 for rewiring formation. A mask 16 having a portion 15 is formed.

  Subsequently, a rewiring 7 composed of a conductive film (wiring layer, plating film) is formed on the seed film 6 by electrolytic plating (S80). Specifically, the rewiring 7 is formed on the connection region 10B and the passivation film 5 so as to be electrically connected to the pad 2 so as to extend from the connection region 10B to the central portion side of the semiconductor chip 1C. The rewiring 7 is made of a Cu or Ni / Cu film. Thereafter, the mask 16 composed of a resist film is removed by ashing, and the seed film 6 is subjected to wet etching using the rewiring 7 as a mask, leaving the seed film 6 below the rewiring 7, and the rest. The seed film 6 under the mask 16 is removed.

  Subsequently, as shown in FIG. 12, a passivation film 8 (third insulating film) is formed on the semiconductor wafer 1W (S90). The passivation film 8 is made of, for example, a polyimide film that is an organic insulating film, and can be formed by, for example, a spin coating method. In the present embodiment, the passivation film 8 is a protective film on the outermost surface and is formed to be thicker than the passivation film 5 in order to improve coverage. Next, wet etching is performed using a photoresist film (not shown) patterned by photolithography as a mask, and a part of the rewiring 7 is exposed from the passivation film 8. As a result, the passivation film 8 has the opening 13. Here, when photosensitive polyimide is used as the material of the passivation film 8, the opening 13 is formed by photo treatment. By applying the photo processing technique, the opening 13 can be processed more finely than the wet etching method.

  Next, as shown in FIG. 3, in the other end of the conductive film (wiring layer, plating film) opposite to the one end connected to the connection region (second region) 10B of the pad 2, electroless An Au film (not shown) is formed on the rewiring 7 exposed from the opening 13 by plating. After the solder paste is printed on the semiconductor wafer 1W by a solder printing technique, the solder paste is melted and recrystallized by a reflow process, and bump electrodes (conductive members, solder balls) as external terminals are formed on the Au film. 9 is formed (S100). As the solder paste, for example, Pb (lead) -free solder formed from Sn (tin), Ag (silver) and Cu can be used. Further, instead of using the solder paste, the bump electrode 9 can also be formed by supplying a solder ball previously formed in a spherical shape onto the opening 13 and then performing a reflow process on the semiconductor wafer 1W. The Au film is not diffused into the bump electrode 9 due to the solder paste reflow process.

  Thereafter, the semiconductor wafer 1W is cut along a scribe (dicing) region between the partitioned device forming regions (between adjacent chip regions), and divided into individual semiconductor chips 1C as shown in FIG. Thus, the semiconductor device in this embodiment is completed. For example, as shown in FIG. 13, the semiconductor chip 1 </ b> C can be mounted on the substrate 52 via the bump electrodes 9. Specifically, after the semiconductor chip 1C is disposed on the substrate 52, the bump electrode 9 is reflowed on the electrode 53, and then the underfill resin 54 is filled between the semiconductor chip 1C and the substrate 52. The semiconductor device can be configured.

  Due to high functionality (increase in pin count) and miniaturization (chip miniaturization), the pads of the connection portion are narrowed and miniaturized. Factors that can reduce the pad size include probing accuracy, probe mark size control, and the like.

  For example, although the pad pitch (size) is reduced due to technological innovation, it is difficult to drastically reduce the probe mark size due to the influence of the contact property of the probe inspection process and the electrical resistance of probing.

  Further, as a probing system, a vertical movement system has been promoted from a cantilever system as shown in the present embodiment, but further technical development is required from the viewpoint of cost and contactability.

  Further, as shown in FIG. 1C, when the contact between the pad 2 and the rewiring 7 is made on the probe mark 100, the plating 102 is insufficiently formed and the void 102 is formed inside. This void 102 causes a failure in electrical characteristics after assembly, and also causes defects such as a short circuit with an adjacent pad and the rewiring 7 exposed on the surface (convex portion 101) due to the formation of irregularities by plating. End up.

  In the present embodiment, the probe region 10A to be probed and the connection region 10B to which the pad 2 and the rewiring 7 are connected are partitioned so that the respective regions are sufficiently secured and the restriction on the probing property is eased. I have to. For the purpose of controlling the probing position, a dummy pad 2A is formed in the row of the probe region 10A of the pad 2. As a result, the probing by the cantilever method can be used, so that the contact property can be secured without restricting the probe inspection method, and the product performance including the analog characteristics that will become increasingly severe in the future can be sufficiently satisfied.

(Embodiment 2)
In the above-described embodiment, the case where the rewiring is configured by the conductive film (plating film) formed by the plating method has been described, but in this embodiment, the case where the bump electrode is configured by the plating film will be described. Other contents are the same as those in the first embodiment.

  First, the structure of the semiconductor device in this embodiment will be described with reference to the drawings. 14 is a schematic diagram illustrating a plan view of the semiconductor device according to the present embodiment, FIG. 15 is a schematic diagram illustrating a main part of a cross section of the semiconductor device illustrated in FIG. 14, and FIG. 16 illustrates the semiconductor device illustrated in FIG. It is a schematic diagram which shows the principal part of a plane.

  A semiconductor circuit (for example, LSI) (not shown) is provided on the main surface of the rectangular semiconductor chip 1C constituting the semiconductor device in the present embodiment. A pad 2 that is electrically connected to wiring constituting the semiconductor circuit and is provided on the semiconductor chip 1C (semiconductor circuit) is provided on the outer periphery of the rectangular semiconductor chip 1C. An electrode 17 is provided. The pad 2 has a connection region 10B on the outer peripheral side of the semiconductor chip 1C and a probe region 10A on the central side as shown by two regions partitioned by broken lines in FIG. By providing the connection region 10B on the outer periphery of the semiconductor chip 1C in this way, it becomes easy to extend a wire (conductive member) from the bump electrode 17 provided on the connection region 10B to the outside of the semiconductor chip 1C.

  That is, as shown in FIG. 17, a plurality of electrodes 56 (bonding leads) formed on the main surface (upper surface) of the substrate 55 (wiring substrate) and a semiconductor chip mounted on the main surface (upper surface) of the substrate 55 The lengths of the plurality of wires 57 (conductive members) that electrically connect the plurality of pads 2 formed on the main surface (front surface) of 1C can be shortened. Thereby, the electrical characteristics of the semiconductor device can be improved.

  Here, in the present embodiment, it has been described that the connection region 10B of the wire 57 is disposed closer to the peripheral edge (side) of the semiconductor chip 1C than the probe region 10A on the surface of the pad 2. However, the present invention is not limited thereto. Instead, the connection region 10B may be disposed closer to the center of the semiconductor chip 1C than the probe region 10A, and one end portion (ball 20) of the wire 57 may be connected to the connection region 10B via the bump electrode 17. However, considering the distance to the electrode 56 (bonding lead) provided on the main surface of the substrate 55 (wiring substrate), the connection region 10B and the bump electrode are arranged on the peripheral portion (side) side where the length of the wire 57 can be reduced. 17 is preferably arranged.

  Further, a passivation film 3 is provided on the semiconductor chip 1C (semiconductor circuit). The passivation film 3 is made of, for example, an inorganic insulating silicon nitride film, and has an opening 11 on the pad 2 in the probe region 10A and the connection region 10B. A passivation film 18 is provided on the pad 2 and the passivation film 3. The passivation film 18 is made of, for example, a polyimide film of an organic insulating film, and has an opening 21 on the pad 2 in the connection region 10B.

  As described with reference to FIG. 1, the probe mark 4 is generated on the pad 2 of the probe region 10 </ b> A provided on the center side of the semiconductor chip 1 </ b> C from the connection region 10 </ b> B as a result of the probe needle 4 contacting the pad 2 in the probe inspection process. 100 (trauma) is present. On the other hand, the bump electrode 17 is electrically connected to the pad 2 and provided on the connection region 10B and the passivation film 3 via a seed film 19 (conductive film). In the present embodiment, the planar shape of the bump electrode 17 is shown as a rectangular shape (see FIG. 16), but may be a polygonal shape or a circular shape, and wire bonding can be performed from the bump electrode 17. Such a planar shape may be used.

  In the present embodiment, the planar shape of the pad 2 is a rectangular shape having a long side from the outer peripheral portion side to the central portion side of the semiconductor chip 1C. For example, the dimension 2a of the pad 2 is 130 μm, the dimension 2b is 75 μm, and the pitch dimension 2c of the pad 2 is 80 μm. Thus, by making the planar shape of the pad 2 rectangular, it is possible to cope with downsizing of the semiconductor device, in particular, narrow pitch. Furthermore, in the present embodiment, the pads 2 are provided in a staggered manner on the outer periphery of the rectangular semiconductor chip 1C. Thereby, it is possible to cope with a narrower pitch. For example, the pitch dimension 2d between the outer pad 2 and the inner pad 2 is 40 μm.

  Here, the case where the wire 57 which is a conductive member is electrically connected to the semiconductor chip 1C in the present embodiment will be described with reference to the drawings. 17 is connected to the bump electrode 17 by wire bonding, the plurality of pads 2 of the semiconductor chip 1C and the plurality of electrodes 56 (bonding) of the substrate 55 (wiring substrate) on which the semiconductor chip 1C is mounted via the plurality of wires 57. FIG. 15 is a schematic diagram showing a main part of a cross section of the semiconductor device shown in FIG. 14 in which leads are electrically connected to each other. 18A and 18B are schematic views showing the connection state of the ball 20 of the wire 57 in plan view. FIG. 18A shows the case where the wire 2 is connected to the pad 2 via the bump electrode 17, and FIGS. This is the case of connection. In each of FIGS. 18A to 18C, the left side of the drawing shows a state before wire bonding, and the right side of the drawing shows a state after wire bonding.

  In the present embodiment, the rectangular pad 2 corresponding to the narrow pitch is formed. For this reason, as shown in FIGS. 18A and 18C, regions 20 a and 20 c (shown by broken lines in the drawing) including the misalignment of wire bonding cover each opening 11, that is, the passivation film 3.

  In FIG. 18 (c), when the ball 20 is electrically connected to the pad 2 within the region 20c including the deviation of wire bonding, the ball 20 rides on the passivation film 3 and cracks in the surrounding passivation film 3 are broken. Cause. This is because a step is generated between the surface (upper surface) of the passivation film 3 and the surface (upper surface) of the pad 2 in the opening 11 of the passivation film 3. Therefore, when one end portion of the wire is connected to the pad 2, if a displacement occurs, the wire rides on the passivation film 3, and if a load is applied in this state, a part of the passivation film 3 is cracked.

  Therefore, as shown in FIG. 18B, by reducing the diameter of the ball 20, the region 20 b including the wire bonding deviation can be reduced, and the climbing onto the passivation film 3 can be prevented. However, it is conceivable that the connection area of the balls 20 decreases and the strength decreases.

  For this reason, in the present embodiment, bump electrodes 17 are provided on the pads 2 as shown in FIGS. Thus, when one end of the wire is connected to the bump electrode 17, even if the center of the one end of the wire is shifted from the center of the bump electrode 17, the surface of the bump electrode 17 (upper surface, wire connection surface) ) Is flat, it can be connected without deforming one end of the wire. Even when a load is applied in this state, the back surface (the lower surface, the connection surface with the pad 2) opposite to the front surface of the bump electrode 17 is connected only to the connection region 10B which is a flat region in the pad 2. Therefore, a part of the passivation film 3 exposing the pad 2 (opening 11) is not subjected to a load during wire connection, and cracking of the passivation film 3 can be suppressed.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. 19 to 22 are schematic views showing the main part of the cross section of the semiconductor device during the manufacturing process in the present embodiment. The steps described with reference to FIG. 19 are subsequent to the steps described with reference to FIG. 7 in the first embodiment, and thus the description thereof is omitted.

  As shown in FIG. 19, a passivation film 18 is formed on the semiconductor wafer 1W. The passivation film 18 is made of, for example, a polyimide film that is an organic insulating film, and can be formed by, for example, a spin coating method. Next, wet etching is performed using a photoresist film (not shown) patterned by photolithography as a mask to expose the passivation film 3 around the pad 2 from the passivation film 18 (see FIG. 20). As a result, the passivation film 18 has the opening 21. Here, in the present embodiment, the material of the pad (electrode) 2 is composed of, for example, an Al film. Further, when using photosensitive polyimide as the material for the passivation film 8, the opening 13 is formed by photo treatment. By applying the photo processing technique, the opening 13 can be processed more finely than the wet etching method.

  Subsequently, a probe inspection of the semiconductor circuit is performed. For example, as shown in FIG. 20, a cantilever probe needle 4 is brought into contact with the pad 2 in the probe region 10A to measure various electrical characteristics. At this time, a probe mark 100 (trauma) due to the probe needle 4 is formed on the surface of the pad 2.

  Subsequently, as shown in FIG. 21, a seed film 19 is formed on the semiconductor wafer 1 </ b> W by being electrically connected to the pad 2. The seed film 19 is a seed film of a conductive film that is formed using a plating method in a later step, and is composed of a Cu film deposited by a sputtering method.

  Subsequently, as shown in FIG. 22, after a resist film is applied on the semiconductor wafer 1W, the resist film is patterned by a photolithography technique to expose a part of the seed film 19 for rewiring formation. A mask 23 having a portion 22 is formed. Next, a bump electrode 17 made of a conductive film (plating film) is formed on the seed film 19 by electrolytic plating. Specifically, the bump electrode 17 is formed in electrical connection with the pad 2 on the connection region 10B. The bump electrode 17 is made of, for example, an Au film. Here, by using Au as the material of the bump electrode 17, the bondability with the wire made of Au can be improved. Further, when a wire made of Au is directly connected to a pad 2 made of Al, Au diffuses into Al, and the bonding surface (bonding region) with the wire in the pad 2 made of Al is contaminated, so that the wire is bonded. Strength may be reduced. However, in this embodiment, a Pd film is formed on the Ni film as a seed film (wiring layer, conductive film, plating layer) 19 on the surface of the pad 2 made of Al, and a bump made of Au is further formed on the seed film. Since the electrode 17 is formed, a decrease in the bonding strength of the wire can be suppressed.

  Subsequently, the mask 23 made of a resist film is removed by ashing, and the seed film 19 is subjected to a wet etching process using the bump electrode 17 as a mask, thereby leaving the seed film 19 below the bump electrode 17 and the others. The seed film 19 under the mask 23 is removed (see FIG. 15).

  Thereafter, the semiconductor wafer 1W is cut along scribe (dicing) regions between the partitioned device formation regions, and divided into individual semiconductor chips 1C as shown in FIG. Complete. Using the semiconductor device in the present embodiment, for example, an external terminal and the bump electrode 17 are electrically connected by wire bonding, and various semiconductor devices are sealed by resin-sealing the semiconductor chip 1C with a resin. Can be configured.

(Embodiment 3)
In the first embodiment, the case where the bump electrode using the solder printing technique is formed on a part of the rewiring has been described, but in this embodiment, the pad using the plating method on the part of the rewiring is described. The case of forming the will be described. Other contents are the same as those in the first embodiment.

  23 and 24 are schematic views showing the main part of the cross section of the semiconductor device during the manufacturing process according to the present embodiment. Note that the process described with reference to FIG. 23 is a continuation of the process described with reference to FIG. 11 in the first embodiment, and therefore the following process will be described below.

  As shown in FIG. 23, after a resist film is applied on the semiconductor wafer 1W, the resist film is patterned by a photolithography technique to expose a part of the rewiring 7 made of, for example, a Cu / Ni film. A mask 24 having an opening 25 is formed. Next, a pad 26 made of a conductive film (plating film) is formed on the rewiring 7 by electrolytic plating. Specifically, the pad 26 is formed in electrical connection with the rewiring 7 and is made of, for example, an Au film. If the rewiring 7 is a Cu film, the pad 26 may be a Ni / Au film. Further, for example, in order to provide a diffusion barrier property with Al of the pad material, a seed film or a plating layer made of a Pd, Ni film is provided.

  Subsequently, as shown in FIG. 24, the mask 24 made of a resist film is removed by ashing, and the seed film 6 is subjected to a wet etching process using the rewiring 7 as a mask. The seed film 6 remaining under the mask 24 is removed while leaving the film 6.

  Thereafter, the semiconductor wafer 1W is cut along scribe (dicing) regions between the partitioned device formation regions, and divided into individual semiconductor chips, whereby the semiconductor device in the present embodiment is completed. For example, various semiconductor devices can be configured by electrically connecting an external terminal and the pad 26 by wire bonding and sealing a semiconductor chip with a resin. The contact resistance can be reduced by forming an Au film on the surface of the rewiring 7 and wire bonding the Au film.

  For example, if the entire rewiring 7 is formed of an Au film, it is not possible to ensure adhesion with the mold resin when assembling the package. Therefore, in the present embodiment, the reliability of the semiconductor device can be ensured by forming the pad 26 composed of the Au film only at the place where wire bonding is performed.

  In addition, in the step of forming the pad 26 including the Au film, a thin film such as electroless plating, sputtering, or printing metal is formed if a mask made of, for example, a resist for forming the pad 26 is formed after the seed film 6 is removed. Technology can also be applied.

  Further, the Ni film under the Au film constituting the pad 26 may be configured as the rewiring 7 or the pad 26, but the Ni film having a larger film stress is configured as the pad 26 than the rewiring 7. It is possible to reduce the influence of wafer (chip) warpage due to the above.

  In consideration of the Cu / Ni interface connection, the pad 26 made of the Cu / Ni / Au film can be formed on the rewiring made of the Cu film.

(Embodiment 4)
In the first to third embodiments, the case where the conductive film (plating film) is not formed by plating on the probe region pad has been described. However, in the present embodiment, the connection region is enlarged and the probe region pad is formed. The case where a plating film is formed also on it will be described. Other contents are the same as those in the first to third embodiments.

  FIG. 25 is a schematic diagram showing the main part of the cross section of the semiconductor device in the present embodiment, where (a) shows the structure of rewiring and solder bump electrodes, (b) shows the structure of stud bump electrodes, and (c) shows the re-use. The case of the wiring and pad structure is shown. FIGS. 25A, 25B, and 25C are schematic views showing the main part of the cross section of the semiconductor device in the present embodiment corresponding to FIGS. 3, 15, and 24, respectively. FIG. 26 is a schematic diagram showing the main part of the plane of the semiconductor device shown in FIG. Moreover, in FIG. 26, it has shown in the state which removed one part. Note that the structure of the stud bump electrode shown in FIG. 25B can cope with Au—Au bonding, Au—solder bonding, and ACF bonding for flip chip mounting.

  As shown in FIGS. 25A and 26, in the connection region 10B where the pad 2 and the rewiring 7 are connected through the seed film 6, the probe region 10A where the probe contacts the pad 2 by the probe inspection process. It is included. That is, the rewiring 7 formed by the plating method is also provided on the pad 2 in the probe region 10A. Thereby, it is possible to avoid exposure of Al to concerns such as corrosion of Al constituting the pad 2.

  As described with reference to FIG. 1, it is conceivable that the seed film 6 due to the step of the probe mark 100 deteriorates the contact property and the flatness of the rewiring 7 that is a plating film. Therefore, in the present embodiment, the contact size between the pad 2 and the rewiring 7 is ensured by increasing the area size of the pad 2, and the flatness of the rewiring on the pad 2 is improved.

  Similarly, in FIG. 25B and FIG. 25C, the contact area between the pad 2 and the plating film (bump electrode 17, rewiring 7) is ensured by increasing the area size of the pad 2. The flatness of the rewiring can be improved.

(Embodiment 5)
In the second embodiment, the case where a single-layer conductive film (plating film) is formed on the pad by a plating method has been described. However, in this embodiment, a multilayer conductive film is formed by repeating the plating method. Will be described. Other contents are the same as those in the second embodiment.

  27 to 29 are schematic views showing the main part of the cross section of the semiconductor device during the manufacturing process according to the present embodiment. Note that the process described with reference to FIG. 27 is a continuation of the process described with reference to FIG. 21 in the second embodiment, and therefore, the subsequent process will be described below.

  As shown in FIG. 27, after applying a resist film on the semiconductor wafer 1W, the resist film is patterned by a photolithography technique to expose a part of the seed film 19 made of a Cu film. A mask 27 is formed. The planar area opened by the opening 28 is larger than the planar area of the pad 2 whose main conductive layer is an Al film.

  Subsequently, a conductive film 29 (plating film) is formed on the seed film 19 by electrolytic plating. Specifically, the conductive film 29 is formed in electrical connection with the pad 2 through the seed film 19 and is made of, for example, an Au film. Thereafter, the mask 27 made of a resist film is removed by ashing.

  Subsequently, as shown in FIG. 28, after a resist film is applied on the semiconductor wafer 1W, the resist film is patterned by a photolithography technique to expose a part of the conductive film 29 composed of the Au film. A mask 30 having an opening 31 is formed. Next, a bump electrode 17 composed of a conductive film (plating film) is formed on the conductive film 29 by electrolytic plating. Specifically, the bump electrode 17 is formed in electrical connection with the pad 2 and is made of, for example, an Au film. Thus, in this Embodiment, the electrically conductive film 29 and the bump electrode 17 are laminated | stacked by the plating method. Thereafter, the mask 30 made of a resist film is removed by ashing.

  The planar shape of the bump electrode 17 may be a planar shape that allows wire bonding from the bump electrode 17, and may be a rectangular shape, a polygonal shape, a circular shape, or a shape that can increase the contact surface ( Maximum size shape) is desirable.

  Subsequently, as shown in FIG. 29, wet etching is performed on the seed film 19 using the conductive film 29 as a mask, leaving the seed film 19 under the conductive film 29 and removing the other seed film 19. . Thereafter, the semiconductor wafer 1W is cut along a scribe (dicing) region between the partitioned device formation regions, and divided into individual semiconductor chips 1C, thereby completing the semiconductor device in the present embodiment.

  By using the semiconductor device in this embodiment, for example, an external terminal and the bump electrode 17 can be electrically connected by wire bonding to form various semiconductor devices. When performing wire bonding, Au / Au bonding can be performed with lower damage such as low temperature and lower load than Al / Au bonding. That is, in this embodiment, since the bump electrode 17 made of the Au film is provided on the conductive film 29 made of the Au film, wire bonding can be performed at a low temperature. In addition, since the Al / Au alloy grows and becomes brittle (deteriorates), in this embodiment, the formation of the Al / Au alloy is avoided or suppressed by the effect of the barrier metal layer formed of the seed film or the plating layer. Therefore, the reliability of wire bonding connection is improved.

  Further, in the present embodiment, the conductive film 29 and the bump electrode 17 are laminated by a plating method, and the conductive film 29 is coated on the entire surface of the pad 2 made of Al, so that the resistance to Al corrosion is improved. Further, the bump electrode 17 has a height 17a higher than the passivation film 18 which is a surface protective film, so that the wire bonding ball (or stitch portion) can be brought into contact with the outer peripheral portion of the passivation film 18 or the like. Can be prevented.

(Embodiment 6)
In the first embodiment, the probe region to be probed and the connection region to which the pad and the rewiring are connected are partitioned so that the respective regions are sufficiently secured and the restriction on the probing property is eased. . In this embodiment, a case will be described in which the section between the probe region and the connection region is further clarified. Other contents are the same as those in the first embodiment.

  FIGS. 30A and 30B are schematic views showing the main part of the plane of the semiconductor device according to the present embodiment. FIG. 30A shows a state in which the opening 11 on the pad has a constriction, and FIG. 30B shows the opening 11 separated. The state is shown. FIG. 30 shows a state in which a part thereof is removed.

  Compared to the case described with reference to FIG. 4 in the first embodiment, the probe region 10A and the connection region 10B where the pad 2 and the rewiring 7 are connected are formed in the passivation film 3 (see also FIG. 3). The openings 11 can be more clearly defined. For this reason, due to the influence of the probe mark 100 generated in the probe inspection process, it is possible to more reliably prevent the rewiring 7 (seed film 6) from being chipped as described with reference to FIG. It is possible to more reliably suppress the shown rewiring 7 from being exposed from the passivation film 8.

(Embodiment 7)
In the first embodiment, the case where the planar shape of the pad is rectangular has been described, but in this embodiment, the case where the pad is convex is described. Other contents are the same as those in the first embodiment.

  FIGS. 31A and 31B are schematic views showing the main part of the plane of the semiconductor device in the present embodiment. FIG. 31A shows a state in which the probe regions are arranged in a staggered manner, and FIG. 31B shows a state in which the probe regions are arranged in a straight shape. It is shown. Moreover, in FIG. 31, it has shown in the state which removed one part.

  In the present embodiment, the probe region 10A to be probed is made smaller than the connection region 10B where the pad 2 and the rewiring 7 are connected. For example, when probing by the cantilever method is used, as described with reference to FIG. 8, the probe needle 4 contacts in such a way as to be displaced in one direction, so that the probe mark 100 extends in that one direction. For this reason, the probe region 10A only needs to secure a region in one direction in which the probe mark 100 extends. On the other hand, the connection region 10B needs to secure a contact area in order to reduce the contact resistance with the rewiring 7, and is larger than the region where the probe needle 4 contacts. Therefore, as shown in FIG. 31, in the pad 2 having a convex planar shape, the protruding region (upper part) is a probe region 10A, and the protruding region (lower part) is a connection region 10B.

  Thus, by reducing the probe region 10A to be probed with respect to the connection region 10B to which the pad 2 and the rewiring 7 are connected, it is possible to cope with the downsizing of the semiconductor device, particularly the narrow pitch. .

  Further, for example, in the case of an area I / O (Input / Output) having a lead-out space in the outer peripheral portion even in the peripheral, the rewiring 7 can be drawn out in both directions. Furthermore, as shown in FIG. 31 (b), by arranging the probe regions 10A in a straight shape, it is possible to cope with further downsizing of the semiconductor device, particularly narrow pitch.

(Embodiment 8)
In the first embodiment, the case where the planar shape of the rewiring connection opening formed on the pad is square has been described. However, in the present embodiment, the rectangular opening is also described. . Other contents are the same as those in the first embodiment.

  FIG. 32 is a schematic diagram showing the main part of the plane of the semiconductor device in the present embodiment. FIG. 32 shows a state in which a part thereof is removed.

  In the present embodiment, a square opening 12 similar to the rewiring connection opening 12 formed on the pad 2 described in the first embodiment with reference to FIG. It has a rectangular opening 12 </ b> A smaller than the opening 12. In the case where the connection between the pad 2 and the rewiring 7 may be high resistance, it is possible to cope with downsizing of the semiconductor device, in particular, narrow pitch, by reducing the opening 12A.

  Further, the connection through the opening 12 is used for connection of, for example, a power (large current) system, analog, or low resistance, and the connection through the opening 12A is used for connection of high resistance. By arranging the terminals more than the terminals, it is possible to cope with the downsizing of the semiconductor device, particularly the narrow pitch.

(Embodiment 9)
In the second embodiment, the case where the bump electrode is provided so as to be within the plane area of the pad has been described, but in the present embodiment, the case where the bump electrode is provided beyond the plane area of the pad will be described. Other contents are the same as those in the first embodiment.

  FIG. 33 is a schematic diagram showing the main part of the plane of the semiconductor device according to the present embodiment. When the planar shape of the bump electrode is a rectangular shape in (a), when it is a polygonal shape in (b), (c ) Shows a case of a circular shape. Moreover, in FIG. 33, it has shown in the state which removed one part.

  In the semiconductor device according to the present embodiment, a mask 23 having a planar opening 22 as shown in FIGS. 33A to 33C is formed in the process described with reference to FIG. 22 in the second embodiment. Thereafter, a bump electrode 17 made of, for example, an Au film is formed on the seed film 19 by an electrolytic plating method.

  For example, in the case of a multi-pin product, the bump electrode 17 composed of the Au film in the present embodiment secures a connection area with the outside rather than the stud bump electrode for wire bonding or the flip. This is advantageous in terms of mitigating damage to the -k layer (interlayer insulating film). Further, since the connection of the bump electrode 17 on the probe mark 100 causes problems such as ensuring flatness, it is necessary to separate into the probe region 10A and the connection region 10B and to make a reliable connection in the connection region 10B. .

(Embodiment 10)
In the first embodiment, the case where the bump electrode made of solder is provided on a part of the plating film (rewiring) at a position away from the pad has been described, but in this embodiment, plating is performed on the pad. The case where the bump electrode comprised from a solder is provided through a film | membrane is demonstrated. Other contents are the same as those in the first embodiment.

  FIG. 34 is a schematic view showing the main part of the cross section of the semiconductor device in the present embodiment. FIG. 34A shows a case where the probe region 10A and the connection region 10B are separated, and FIG. 34B shows the probe region 10A in the connection region 10B. The case of including is shown.

  For example, if a bump electrode made of solder is formed directly on the pad 2 made of an Al film, the connection strength may be low and the reliability of the semiconductor device may be lowered. Therefore, as shown in the present embodiment, by using a plating film 7 formed by plating between the pad 2 made of Al film and the bump electrode 9 made of solder, the connection strength is increased. The reliability of the semiconductor device can be improved.

  As shown in FIG. 34 (b), when the connection region 10B includes the probe region 10A, the connection region 10B can be enlarged from FIG. 34 (a). Further, the present invention can be applied to a product in which the pad 2 made of an Al film cannot be exposed.

(Embodiment 11)
In this embodiment, a case where a small and high density SiP (System in Package) is configured by stacking semiconductor chips using flip chip technology and wire bonding technology will be described.

  35 to 39 are schematic views showing cross sections of the semiconductor device during the manufacturing process in the present embodiment. First, as shown in FIG. 35, for example, the semiconductor chip 1C1 as shown in the first embodiment is flip-mounted on one surface (front surface) of the insulating substrate 32 made of glass epoxy resin, polyimide resin, or the like. The insulating substrate 32 is substantially the same shape as the semiconductor chip 1C1 and is slightly larger than the semiconductor chip 1C1, and a plurality of land electrodes (not shown) are disposed on the surface side in the same positional relationship as the ball-shaped bump electrodes 9 of the semiconductor chip 1C1. Is formed. That is, the bump electrode 9 of the semiconductor chip 1C1 and the land electrode of the insulating substrate 32 are electrically connected by flip mounting. Specifically, as described in the first embodiment, since the bump electrode 9 is provided on the rewiring drawn from the pad with a narrow pitch and the ball diameter is secured, the deviation between the land electrode and the bump electrode 9 is prevented. It can be prevented and electrically connected.

  Subsequently, as shown in FIG. 36, the semiconductor chip 1C2 shown in the second embodiment and the semiconductor chip 1C3 shown in the third embodiment are stacked on the semiconductor chip 1C using an adhesive. Next, as shown in FIG. 37, the land electrodes on the insulating substrate 32 and the pads on the semiconductor chips 1C2 and 1C2 are electrically connected by wires 33.

  Here, an example of the connection of the wires 33 in the laminated chip is shown in FIGS. In FIG. 40 and FIG. 41, the semiconductor chip 1C2 and the semiconductor chip 1C3 are joined by the adhesive 36. In FIG. 40, the wire 33a is electrically connected from the pad 17 of the semiconductor chip 1C2 to the pad 26 of the semiconductor chip 1C3. That is, the ball of the wire 33a is formed on the pad 17 of the semiconductor chip 1C2, and the stitch of the wire 33a is formed on the pad 26 of the semiconductor chip 1C3. Conventionally, since it is difficult to stitch a narrow pitch Al pad, a stud bump for wire bonding is formed and stitched on the stud bump. A wire 33b is electrically connected from the pad 26 of the semiconductor chip 1C3 to the land electrode on the surface of the insulating substrate 32. That is, a ball of the wire 33 b is further formed on the stitch formed on the pad 26. In this manner, the semiconductor device can be reduced in size by bonding the wires 33a and 33b.

  In FIG. 41, a plurality of wire bonding regions are provided in the rewiring 7 of the semiconductor chip 1C3. A wire 33a is electrically connected from the pad 17 of the semiconductor chip 1C2 to the pad 26a of the semiconductor chip 1C3. That is, the ball of the wire 33a is formed on the pad 17 of the semiconductor chip 1C2, and the stitch of the wire 33a is formed on the pad 26a of the semiconductor chip 1C3. A wire 33b is electrically connected from the pad 26b of the semiconductor chip 1C3 to the land electrode on the surface of the insulating substrate 32. That is, the ball of the wire 33b is formed on the pad 26b. Thus, by dividing the pads 26a and 26b on the rewiring 7 of the semiconductor chip 1C3, the wire bondings 33a and 33b can be connected in a flat region, and good connectivity can be ensured. Even if the wire bondings 33a and 33b have a distance, they can be electrically connected by the rewiring 7.

  Subsequently, as shown in FIG. 38, the semiconductor chips 1C1, 1C2, and 1C3 are resin-sealed by the resin 34. Next, as shown in FIG. 39, a ball electrode 35 electrically connected to the land electrode on the front surface is formed on the back surface opposite to the front surface of the insulating substrate 32. The ball electrodes 35 are formed at intervals wider than the interelectrode pitch of the land electrodes so as to correspond to the land electrodes on the surface of the insulating substrate 32. That is, the insulating substrate 32 is a so-called interposer substrate.

  Thereby, the SiP product (semiconductor device) in the present embodiment can be completed. Various semiconductor devices can be configured by mounting the SiP product in this embodiment on a mother substrate. In addition, according to the method using the interposer, the electrode pattern of the mother substrate may be formed in correspondence with the ball electrode pattern of the interposer substrate. In addition, a mother substrate can be formed at a low cost.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the cantilever method is used in the probe inspection process has been described, but the present invention can also be applied to the case where the vertical movement method is used.

  Moreover, although the said embodiment demonstrated connecting a conductive member to a connection area | region after performing a probe test | inspection process, it is not limited to this. For example, products that do not want to be subjected to thermal load such as passivation, seed, resist, and plating after the probe test (ROM writing performed in the probe process disappears, fuse cut (memory bit switching, resistance fluctuation adjustment, etc.) is required Product) is preferably implemented after the bump electrode (Au plating) is formed. In the case where the probe inspection process is performed after the conductive member is formed, since the probe needle is not brought into contact with the pad, Cu may be used as the pad material.

  If the conductive member is connected to the connection region before the probe inspection process, the surface of the connection region may be contaminated due to the influence of the thermal load in the probe inspection process. It is good to clean.

  The present invention is widely used in the manufacturing industry of a semiconductor device, particularly a semiconductor device having a conductive film formed on a pad after a probe inspection process performed by bringing a probe needle into contact with the pad. For example, the present invention can be applied to products such as mobile products that are narrow pitch products, navigation products, in-vehicle products, and analogs that require strict electrical characteristics.

1C, 1C1, 1C2, 1C3 Semiconductor chip 1W Semiconductor wafer 2 Pad (electrode)
2A Dummy pad 3 Passivation film (first insulating film)
4 Probe needle 5 Passivation film (second insulating film)
6 Seed film (wiring layer, conductive film, plating layer)
7 Rewiring (wiring layer, conductive film, plating film)
8 Passivation film (third insulating film)
9 Bump electrode 10A Probe area (first area)
10B Connection area (second area)
11, 12, 12A, 13, 14, 15 Opening 16 Mask 17 Bump electrode 18 Passivation film 19 Seed film (wiring layer, conductive film, plating layer)
20 Ball 21, 22 Opening 23, 24 Mask 25 Opening 26, 26a, 26b Pad 27 Mask 28 Opening 29 Conductive film 30 Mask 31 Opening 32 Insulating substrate 33, 33a, 33b Wire (conductive member)
34 Resin 35 Ball electrode 36 Adhesive 50 Device forming area 51 Scribe area 52 Substrate 53 Electrode 54 Underfill resin 55 Substrate 56 Electrode 57 Wire 100 Probe trace (trauma)
101 Convex part 102

Claims (16)

A first main surface, a first pad formed on the first main surface, a first passivation film formed on the first main surface such that a part of the first pad is exposed, and the first pad First wiring having a first portion connected to the first portion and a second portion formed on the first passivation film, and a first back surface opposite to the first main surface. A semiconductor chip;
A first wire having one end connected to the second portion of the wiring;
Including a semiconductor device. A conductive film is formed on the second portion of the wiring;
The semiconductor device according to claim 1, wherein the one end portion of the first wire is connected to the second portion of the wiring via the conductive film. A ball is formed on the one end of the first wire,
The semiconductor device according to claim 2, wherein the ball of the first wire is connected to the second portion of the wiring via the conductive film. The first semiconductor chip includes the upper surface, the first back surface of the first semiconductor chip facing the upper surface of the wiring substrate, and the bonding leads of the wiring substrate exposed from the first semiconductor chip. It is mounted on the wiring substrate having a bonding lead and a lower surface opposite to the upper surface,
The semiconductor device according to claim 3, wherein the other end portion of the first wire is connected to the bonding lead of the wiring board.   The semiconductor device according to claim 4, wherein the first semiconductor chip and the first wire are sealed with a resin. A ball is formed on the one end of the first wire,
The semiconductor device according to claim 1, wherein the ball of the first wire is connected to the second portion of the wiring. The first semiconductor chip includes the upper surface, the first back surface of the first semiconductor chip facing the upper surface of the wiring substrate, and the bonding leads of the wiring substrate exposed from the first semiconductor chip. It is mounted on the wiring substrate having a bonding lead and a lower surface opposite to the upper surface,
The semiconductor device according to claim 6, wherein the other end portion of the first wire is connected to the bonding lead of the wiring board.   The semiconductor device according to claim 7, wherein the first semiconductor chip and the first wire are sealed with a resin. The first semiconductor chip includes the upper surface, the first back surface of the first semiconductor chip facing the upper surface of the wiring substrate, and the bonding leads of the wiring substrate exposed from the first semiconductor chip. It is mounted on the wiring substrate having a bonding lead and a lower surface opposite to the upper surface,
The semiconductor device according to claim 1, wherein the other end portion of the first wire is connected to the bonding lead of the wiring board.   The semiconductor device according to claim 9, wherein the first semiconductor chip and the first wire are sealed with a resin.   2. The semiconductor device according to claim 1, wherein the first part of the wiring is connected to the part of the first pad of the first semiconductor chip that is different from a part where a probe mark is formed. A second main surface, a second pad formed on the second main surface, a second passivation film formed on the second main surface so that a part of the second pad is exposed, and the second A second semiconductor chip having a second back surface opposite to the main surface, such that the second back surface of the second semiconductor chip faces the first main surface of the first semiconductor chip; and It is mounted on the first main surface of the first semiconductor chip so that the wiring of the first semiconductor chip is exposed from the second semiconductor chip,
2. The semiconductor device according to claim 1, wherein the second pad of the second semiconductor chip is electrically connected to the wiring of the first semiconductor chip through a second wire. One end of the second wire is connected to the second pad of the second semiconductor chip,
The semiconductor device according to claim 12, wherein the other end of the second wire is connected to the second portion of the wiring of the first semiconductor chip. A conductive film is formed on the second portion of the wiring;
The semiconductor device according to claim 13, wherein the other end portion of the second wire is connected to the second portion of the wiring via the conductive film. One end of the second wire is connected to the second pad of the second semiconductor chip,
The semiconductor device according to claim 12, wherein the other end portion of the second wire is connected to a third portion of the wiring of the first semiconductor chip that is different from the first portion and the second portion. . A conductive film is formed on the third portion of the wiring;
The semiconductor device according to claim 15, wherein the other end portion of the second wire is connected to the third portion of the wiring via the conductive film.

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