JPH0864799A - Semiconductor chip, semiconductor device using it and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a semiconductor chip having a back electrode which has a high bonding strength and a low contact resistance and a semiconductor device using it. CONSTITUTION: A semiconductor chip is composed of an N-type silicon substrate 11, an alloy layer 17 which is composed of vanadium and V-metal and formed on the main surface of the substrate 11, a nickel layer 18 provided onto the alloy layer 17, and a gold layer 19 formed on the nickel layer 18. The semiconductor chip is fused to the die pad of a package component through the intermediary of a brazing material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a method for manufacturing a semiconductor device using the same, and more particularly to a semiconductor chip having a back surface electrode having excellent adhesive force and low contact resistance, and a method for assembling a semiconductor device using the same. Regarding

[0002]

2. Description of the Related Art In general, a semiconductor chip whose back surface constitutes one of electrodes like a transistor has a back surface on the die pad of an enclosure part such as a lead frame, a metal package, a circuit board, etc. To be joined. In the case of a semiconductor chip that handles a small current, a conductive adhesive may be used as the conductive joining means, but in the case of a semiconductor chip that handles a relatively large current, soldering, brazing such as soft soldering, etc. used. When a relatively low contact resistance is required, a eutectic method of forming a eutectic metal between the back metal of the chip and the die pad metal may be used.

When a conductive adhesive or a joining means such as brazing is adopted, the back surface of the chip and the die pad must be connected by ohmic contact. Therefore, the back surface electrode of the semiconductor chip is subjected to ohmic contact treatment. When the semiconductor device is exposed to a thermal cycle due to the operation or non-operation of the semiconductor device or a rapid change in the ambient temperature, it occurs due to the difference between the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the envelope part on which the die pad is formed. A strong joining force that can withstand heat stress is also required.

Therefore, in a method of forming a back surface electrode of a power transistor or the like which handles a relatively large current, a thin film of vanadium (V) having a high adhesion strength with silicon is deposited on the back surface of the chip,
A method in which a nickel (Ni) layer having a good bondability with the brazing material and a gold (Au) layer are further deposited on the above to further prevent oxidation of the nickel layer are often used. The semiconductor chip thus processed on the back surface is joined to the die pad by soldering or soft brazing to form a packaged semiconductor device.

Usually, the impurity concentration on the back surface of the n-type silicon semiconductor chip is about 2 × 10 ¹⁸ atoms / cm ³ , and when the impurity concentration on the back surface is at this level, a potential difference is generated between it and vanadium of the first layer. This may result in an increase in contact resistance.
As a countermeasure for the back surface impurity concentration deficiency, gold and a Group V alloy such as gold antimony (AuSb) are deposited on the first layer of vanadium, a nickel layer is further deposited thereon, and a gold layer is further coated thereon. There is also a method of adhering it to form a back surface electrode of a semiconductor chip.

FIG. 6 is a sectional view of a transistor having such a structure. The n-type silicon substrate 111 constitutes a collector, and a base 112 and an emitter 113 are formed in this surface region. The silicon substrate 11
The surface of 1 is covered with an insulating film 114, but the base 11
2. The insulating film 114 is opened at the electrode extraction portion of the emitter 113, and the base electrode 115 and the emitter electrode 116 are formed respectively.

On the other hand, on the back surface of the silicon substrate 111, first, a vanadium (V) layer 117 as a first layer having a film thickness of 10 to 2 is formed.
It is formed with 00 nm. Further, as a second layer, an alloy layer 118 of gold antimony (AuSb) (the content of Sb is 1
0 to 50%) is formed with a film thickness of 20 to 200 nm. Further, a nickel (Ni) layer 119 is formed as a third layer.
It is formed to a film thickness of 00 to 1000 nm, and a gold (Au) layer 120 is further formed thereon to a film thickness of 50 to 300 nm as a fourth layer.

In this method, antimony of the second layer of gold antimony alloy is thermally diffused into the silicon substrate through the vanadium layer to locally supplement the back surface impurity concentration.
However, in this method, vanadium in the first layer serves as a barrier, and antimony may not be diffused into the n-type substrate. Therefore, it is necessary to reduce the film thickness of vanadium, and management is complicated. There is also a drawback that the bonding strength decreases as the vanadium film thickness decreases.

On the other hand, when the semiconductor substrate is p-type, the impurity concentration is usually about 5 × 10 ¹⁹ atoms / cm ^3, which is higher than that of n-type by one digit or more, and the influence of the contact potential difference with vanadium is negligible. No trouble will occur.

[0010]

When the back surface treatment of the semiconductor chip using the n-type silicon substrate uses vanadium as the bonding layer as described above, the contact resistance on the back surface of the semiconductor chip may increase. It was

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor chip having a back surface electrode having high bonding strength and low contact resistance, and a method of manufacturing a semiconductor device using the same. .

[0012]

In order to solve the above problems, a semiconductor chip according to the present invention comprises an n-type silicon substrate,
An alloy layer made of vanadium and a group V metal formed on one main surface of the silicon substrate; a nickel layer formed on the alloy layer; and a gold layer formed on the nickel layer. It is characterized by having.

A gold germanium alloy layer may be further provided as a brazing material between the nickel layer and the gold layer. Further, antimony is preferable as the group V metal, and arsenic, phosphorus and the like can also be used.

The method of manufacturing a semiconductor device according to the present invention is provided with n
Type silicon substrate, an alloy layer made of vanadium and a Group V metal formed on one main surface of the silicon substrate, a nickel layer formed on the alloy layer, and formed on the nickel layer A step of forming a semiconductor chip having a laminated electrode composed of the formed gold layer, and a step of heat-fusing the laminated electrode of the semiconductor chip to a die pad of an envelope part via a brazing material. It has a feature.

Another method of manufacturing a semiconductor device according to the present invention is an n-type silicon substrate, an alloy layer made of vanadium and a Group V metal formed on one main surface of the silicon substrate, and the alloy layer. A semiconductor chip comprising a nickel layer formed on the above, a gold germanium alloy layer formed on the nickel layer, and a laminated electrode including a gold layer formed on the gold germanium alloy layer. It is characterized by including a step of forming and a step of heating and melting the laminated electrode of the semiconductor chip to a die pad of an envelope part.

[0016]

In the present invention, since the alloy layer in which the group V atom such as antimony is added to the metal layer of vanadium having a strong bonding force with silicon provided in the first layer on the back surface of the silicon substrate is used, the die mount is performed. The antimony or the like diffuses into the silicon substrate by the heating at that time, and the impurity concentration on the back surface of the silicon substrate becomes 1 × 10 ¹⁹ atoms / cm ³ or more, and the contact resistance can be reduced. Since antimony or the like is contained in the metal layer of vanadium which is in direct contact with the silicon substrate, antimony or the like can be easily diffused into the silicon substrate.

[0017]

Embodiments will be described below with reference to the drawings. FIG. 1 is a sectional view of an npn transistor chip according to the first embodiment of the present invention. The n-type silicon substrate 11 constitutes a collector, and the base 12 and the emitter 13 are formed in this surface region. The surface of the silicon substrate 11 is covered with an insulating film 14, but the insulating film 14 is opened at the electrode extraction portions of the base 12 and the emitter 13 to form a base electrode 15 and an emitter electrode 16, respectively.

On the other hand, on the back surface of the silicon substrate 11, a vanadium antimony (VSb) layer 17 which is an alloy of vanadium (V) and antimony (Sb) which is a metal of Group 5 is sputtered as a first layer for 10 to 200 nm. And the like. In this case, the content of antimony is determined by the upper limit of the allowable contact resistance and is usually 1 to
It is 30% by weight, preferably 5 to 20%. If the content of antimony exceeds 30%, the melting point becomes high and diffusion into silicon becomes difficult. If the thickness of the vanadium antimony layer 17 is 10 μm or less, the antimony addition effect is small, and if it is 200 μm or more, the series resistance of the vanadium antimony layer 17 becomes too large. The film thickness is preferably 50-100 nm.

Further, as a second layer, a nickel (Ni) layer 1
8 is vapor-deposited with a film thickness of 100 to 1000 nm. Further, a gold (Au) layer 19 as the third layer has a thickness of 50 to 300 nm.
It is vapor-deposited with a film thickness of.

After the characteristic inspection, the transistor chip thus constructed is cut into individual chips and mounted on a die pad of an enclosure component such as a lead frame, a metal package, or a circuit board by a soldering method. Eg 400
The transistor chip was mounted on high-temperature solder (Pb, Sn.Cu, P alloy with a melting point of 310 ° C.) that was melting on the die pad in a reducing atmosphere at 0 ° C., and transferred to the cooling zone after about 4 to 5 seconds. Mounting is done by mounting.
During this period, the residence time at a temperature of 350 ° C. or higher including the preheating and cooling steps is about 7 to 8 seconds.

FIG. 2 is a schematic cross-sectional view showing the state immediately before this mounting. On the lower surface of the semiconductor chip 30, the back surface electrode 31 (number 1 in FIG.
(Corresponding to 7, 18, and 19) are formed. A solder foil 34 is placed on the die pad 33 of the envelope part 32 placed on a heating stage (not shown) and is in a molten state by the heat from the heating stage. The back surface electrode 31 of the semiconductor chip 30 is aligned and pressure-bonded onto the solder foil 34. After that, the solder mounting is completed by transferring to the cooling zone.

The antimony of the vanadium antimony layer 17 is diffused to the back surface of the silicon substrate 11 by the heating in the above mounting step. As a result, the impurity concentration on the back surface of the silicon substrate 11 becomes 1 × 10 ¹⁹ atoms / cm ³ or more, and the contact resistance between the silicon substrate 11 and the vanadium antimony layer 17 can be suppressed low.

Although high-temperature solder was used as the solder in the above embodiment, the present invention is not limited to high-temperature solder, and solder having a working temperature of 250 ° C. or higher (usually melting point + 20 ° C.)
The above temperature is selected as the working temperature).

Next, the effects of the present invention will be compared with the prior art,
Forward voltage drop (V between collector-base of transistor)
CBF). FIG. 3 is a graph showing the distribution of VCBF when a current of 1 A is applied to three types of samples. (A) is a first comparative example according to the prior art in which vanadium is formed on the first layer, nickel is formed on the second layer, and gold is formed on the third layer, and (b) is vanadium on the first layer and It is a second comparative example of a four-layer structure in which gold antimony is formed in two layers, nickel is formed in the third layer, and gold is formed in the fourth layer. (C) is the sample of the present embodiment, and the VCBF was measured for each of the above three kinds of samples, and each of them was represented by an x mark to form a frequency distribution. The sample of this example is the same as the above example except that the antimony content is 20%, the thickness of the vanadium antimony layer 17 is 75 μm, the solder mount is 400 ° C. for 4 to 5 seconds (the residence time at a temperature of 350 ° C. or higher is 7 to 8
Seconds). As is clear from this figure, the method of this example has a VCBF of 0.1 to 0.4 as compared with the comparative example.
V is low, and in addition, variations are small.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a sectional view of an npn transistor chip according to the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. On the back surface of the silicon substrate 11, first, a vanadium antimony (VSb) layer 17 which is an alloy of vanadium (V) and antimony (Sb) which is a group 5 metal is used as a first layer by a method such as 10 to 200 nm sputtering. Has been formed. Further, as the second layer, a nickel (Ni) layer 18 is vapor-deposited with a film thickness of 100 to 1000 nm. Further, a gold germanium (AuGe) alloy layer 20 (Ge content 5 to 20%) is vapor-deposited thereon in a thickness of 1 to 2 μm as a brazing material. Further, a gold (Au) layer 21 as a fourth layer is vapor-deposited thereon as an antioxidant film of the gold germanium layer 20 with a film thickness of about 100 nm.

The transistor chip thus constructed is cut into individual chips after characteristic inspection, and then mounted on a die pad of an envelope part by a brazing method. For example, the transistor chip is mounted on a gold-plated die pad in a reducing atmosphere at 380 ° C., scrubbed for about 1 second, and then transferred to a low temperature zone for mounting. At this time, the residence time at a temperature of 350 ° C. or higher including the preheating and cooling steps is about 5 to 6 seconds.

FIG. 5 is a schematic cross-sectional view of the state immediately before this mounting. On the lower surface of the semiconductor chip 40, the back surface electrode 41 (number 1 in FIG.
(Corresponding to 7, 18, 20, and 21) are formed. The die pad 43 of the envelope part 42 placed on a heating stage (not shown) is plated with gold, and the back surface electrode 41 of the semiconductor chip 40 is aligned on the die pad 43 and pressure-bonded swing (scrub). To be done. At this time, the aforementioned gold germanium contained in the back surface electrode 41 (No. 2 in FIG. 3).
0) is fused and brazed with the gold plating of the die pad 43. After that, the brazing mount is completed by transferring to the cooling zone.

By the heating in the above mounting step, antimony of the vanadium antimony layer 17 is diffused to the back surface of the silicon substrate 11. As a result, the impurity concentration on the back surface of the silicon substrate 11 becomes 1 × 10 ¹⁹ atoms / cm ³ or more, and the contact resistance between the silicon substrate 11 and the vanadium antimony layer 17 can be suppressed low.

The present invention has been described above based on the embodiments.
It is needless to say that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, as the Group V metal, arsenic (As), phosphorus (P), or the like can be used in addition to the antimony described in the above embodiment.

[0030]

As described above, since the back surface electrode of the semiconductor chip of the present invention is formed of the alloy of vanadium and the metal of the group V as the first layer on the n-type silicon substrate,
In the heating step (die mounting step) after the formation, the group V metal diffuses into the n-type silicon substrate, lowering the contact resistance at the contact interface. Further, since vanadium and the silicon substrate form a strong adhesive surface, it is possible to obtain a semiconductor device having high mechanical strength and low electrical contact resistance (collector series resistance).

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a schematic view showing a cross-sectional view of a semiconductor chip mounting process according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention;
In the graph which compared F (at 1A) distribution with the prior art, (a) is the distribution of the first comparative example, (b) is the distribution of the second comparative example,
(C) represents the distribution of the first embodiment.

FIG. 4 is a sectional view of a semiconductor chip according to a second embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a mounting process of a semiconductor chip according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a conventional semiconductor chip.

[Explanation of Codes] 11 ... Silicon substrate (collector), 12 ... Base, 13
... Emitter, 14 ... Insulating film, 15 ... Base electrode, 16 ...
Emitter electrode, 17 ... Vanadium antimony layer, 18 ...
Nickel layer, 19 ... Gold layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/41 H01L 29/44 B

Claims (5)

[Claims] 1. An n-type silicon substrate, an alloy layer made of vanadium and a group V metal formed on one main surface of the silicon substrate, a nickel layer formed on the alloy layer, And a gold layer formed on the nickel layer. 2. Between the nickel layer and the gold layer,
The semiconductor chip according to claim 1, further comprising a gold germanium alloy layer. 3. The semiconductor chip according to claim 1, wherein the Group V metal is antimony. 4. An n-type silicon substrate, an alloy layer composed of vanadium and a Group V metal formed on one main surface of the silicon substrate, a nickel layer formed on the alloy layer, and A step of forming a semiconductor chip having a laminated electrode formed of a gold layer formed on a nickel layer, and heat-fusing the laminated electrode of the semiconductor chip to a die pad of an envelope part via a brazing material. A method of manufacturing a semiconductor device, comprising: 5. An n-type silicon substrate, an alloy layer composed of vanadium and a Group V metal formed on one main surface of the silicon substrate, a nickel layer formed on the alloy layer, and A step of forming a semiconductor chip comprising a gold germanium alloy layer formed on a nickel layer and a gold electrode formed on the gold germanium alloy layer, and the stacked electrode of the semiconductor chip And a step of heat-sealing the die pad of the envelope part to the semiconductor device.