JPS59117171A - High-frequency high-output field-effect transistor - Google Patents
High-frequency high-output field-effect transistorInfo
- Publication number
- JPS59117171A JPS59117171A JP57232400A JP23240082A JPS59117171A JP S59117171 A JPS59117171 A JP S59117171A JP 57232400 A JP57232400 A JP 57232400A JP 23240082 A JP23240082 A JP 23240082A JP S59117171 A JPS59117171 A JP S59117171A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- electrode
- semiconductor substrate
- substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 230000017525 heat dissipation Effects 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高周波商量力１乱界効果トランジスタに関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high frequency turbulent field effect transistor.
従来、尚周波帯、超尚周波帯に使用される′電界効果ト
ランジスタ（以下ＦＩｆｌＴと記す）はＧａＡｓ等の化
合物千尋体が使用さ扛ている。そして尚周波高出力ＦＥ
Ｔでは半導体基板の裏面に通常ＰＨ８（Ｐｌａｔｅｄ
ｌ１ｅａｔ ５ｉｎｋ）と呼ばれるメッキしたヒートシ
ンクが設け、放熱を改善し、高出力が得られるようにし
である。−万、高周波特性を改善するためにも柳々の設
計上の工夫がなされているが。Conventionally, field effect transistors (hereinafter referred to as FIflT) used in the low frequency band and ultra low frequency band have been made of a compound such as GaAs. And still frequency high output FE
In T, there is usually PH8 (Plated) on the back side of the semiconductor substrate.
It is equipped with a plated heat sink called LEAT 5INK to improve heat dissipation and provide high output power. -Yanagi's design has been improved to improve its high frequency characteristics.
その一つとしてソース・インダクタンスを低減するため
にバイア・ホール構造が開発されている。As one of these, via-hole structures have been developed to reduce source inductance.
そしてＰＨ８とバイア・ホールとが併用されることが多
い。PH8 and via holes are often used together.
第１図は従来の高周波高出力Ｆ Ｅ ’ｌ’の一例の断
面図である。FIG. 1 is a sectional view of an example of a conventional high frequency high output F E 'l'.
ＧａＡｓ等の半導体基板１にソース′…、極Ｓ、ゲート
篭極Ｇ、ドレイン電極りを設け、ソース電極Ｓの下に穴
２をあけ、放熱層３をメッキ法によりル成する。このバ
イア・ホールとＰＨ８とを併用した構造では、基板１の
厚さを薄くシ、裏面に厚い放熱層３を形成することによ
り、ソース・インダクタンスを低減するのみならず熱抵
抗をも低減できる。しかしながら、穴２の深さは、通常
１０〜５０μｍであり、メッキを厚くしても放熱層３に
凹剖４が形成さ才り、−との凹部４ケなくすことは難し
い。この牛心体チップを容器に半田等でマウントすると
き、凹部４を埋めることができず、凹部４に空気が残り
、熱抵抗値が設計通りに下らないとか、信頼性を低下さ
せるというような欠点があった。A semiconductor substrate 1 made of GaAs or the like is provided with a source '..., a pole S, a gate shield G, and a drain electrode, a hole 2 is made under the source electrode S, and a heat dissipation layer 3 is formed by plating. In the structure using this via hole and PH8 in combination, by reducing the thickness of the substrate 1 and forming a thick heat dissipation layer 3 on the back surface, it is possible to reduce not only the source inductance but also the thermal resistance. However, the depth of the hole 2 is usually 10 to 50 .mu.m, and even if the plating is thick, a recess 4 is formed in the heat dissipation layer 3, and it is difficult to eliminate the four recesses. When this cow-centered chip is mounted on a container with solder or the like, the concave part 4 cannot be filled, and air remains in the concave part 4, resulting in disadvantages such as the thermal resistance value not falling as designed and reliability being reduced. was there.
本発明は上記入点全除去し、バイア・ホールとＰＩ−Ｊ
８とを有する構造で、しかもバイア・ホールに空気を閉
じこめてしまうことがなく、電気的符性及び信頼性を向
上させた尚周波高出力電界効果トランジスタラ提供する
ものである。The present invention eliminates all of the above entry points and removes via holes and PI-J.
The present invention provides a high-frequency, high-output field effect transistor having a structure having a structure of 8 and 8, which does not trap air in via holes, and has improved electrical consistency and reliability.
本発明の尚周波尚出力・電界効果トランジスタは、半導
体晶析の表面に形成されたケート電極とドレイン電極と
、前記半導体基板を貫通する貫通孔と、該貫通孔の側面
を復いかつ半病８体華板表面に伸びるソース・電極と、
前記十ｍ体基枦に設けらｎ前記ソース市、極に前記貫通
孔側面でｈわｐ−ａ−る放熱層とを含んで栴成さ几る。The high frequency low output/field effect transistor of the present invention includes a gate electrode and a drain electrode formed on the surface of the semiconductor crystallization, a through hole penetrating the semiconductor substrate, and a semicircular 8 A source/electrode extending on the surface of the body plate,
The source plate is provided on the base plate, and a heat dissipation layer is formed on the side surface of the through-hole at the source plate.
次に、本発明の実施例についで図面を用いて説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例の断面図である。FIG. 2 is a sectional view of one embodiment of the present invention.
この実施例は、半導体基板１１の表面（で形成されたケ
ート電極Ｇとドレイン電極りと、半導体基板１１を貫通
する貫通孔１２と、この貫通孔１２の側面を覆いかつ半
導体基板表面に伸びるソース′に極Ｓと、半導体基板１
の裏面に設けられ、ソース電極Ｓと貫通孔１２の側面で
接続する放熱層１３とを含んで構成される、
このような構造にすると、放熱層１３には凹部ができな
いので、従来品のような壁気が閉じこめられるという欠
点は除去される。し炉も貫通孔１２を介してソース１ｕ
極Ｓが放熱層１３Ｖｃ＆続しているので、ソース・イン
ダクタンス、熱抵抗共に低減さ几る。ソース電極Ｓに回
置［＼１４がフレＦｙ、さｎるが、こｎは時性に何ら影
響を及ぼさない。This embodiment includes a gate electrode G and a drain electrode formed on the surface of a semiconductor substrate 11, a through hole 12 penetrating the semiconductor substrate 11, and a source covering the side surface of the through hole 12 and extending to the surface of the semiconductor substrate. ′ is the pole S, and the semiconductor substrate 1
With such a structure, the heat dissipation layer 13 is provided on the back side of the through hole 12 and connected to the source electrode S on the side surface of the through hole 12. The drawback of air being trapped in walls is eliminated. The source 1u is also connected to the furnace through the through hole 12.
Since the pole S is connected to the heat dissipation layer 13Vc, both source inductance and thermal resistance are reduced. Although the source electrode S is replaced with a frame Fy, this has no effect on the temporality.
次に、この実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.
第３図（ａｌ〜（ＣＪは本発明の一実施しリの製］肯方
法を説明するための工程順に示した断面図である。FIG. 3 is a cross-sectional view showing the order of steps for explaining a method of manufacturing (CJ is an embodiment of the present invention).
まず、第３図（ａｌｌで示すように、最終製品の基板厚
さの設計値よりも厚い半導体基板１１を川魚する。そし
て最終製品の基板厚さの設計値と同じ値の深さの穴１２
’を」屈る。First, as shown in Figure 3 (all), a semiconductor substrate 11 that is thicker than the design value of the board thickness of the final product is drilled. 12
``Bend over''.
次に、第３図（ｂ）に示すように２通常の方法でソース
電極Ｓ、ゲート電極Ｇ、）レイン電極りを形成する。Next, as shown in FIG. 3(b), a source electrode S, a gate electrode G, and a rain electrode are formed using two conventional methods.
次に、第３図［Ｃ１に示すように一基板］１の裏面をエ
ツチングまたはラッピング等により切削し、基板１１を
設計値の厚さにする。これにより穴１２′の紙が削り取
ら几てなくなり、穴１２′は基板１１を貫通するＷ通孔
１２りなる。最後に、裏面に放熱層１３をメッキ法で形
成すると、第２図に示す扮遣が傅らｎる。Next, the back surface of the substrate 1 as shown in FIG. 3 [C1] is cut by etching or lapping to make the substrate 11 a designed thickness. As a result, the paper in the hole 12' is scraped off, and the hole 12' becomes a W through hole 12 penetrating the substrate 11. Finally, when the heat dissipation layer 13 is formed on the back surface by plating, the appearance shown in FIG. 2 is obtained.
以上詳細に説明したように、本発明によ′ｎは、バイア
・ホールとＰＨ８とを有し、電気的特性及びイに粗性を
向上させた高周波尚出カ′眩界効果トランジスタが得ら
ｎるのでその効果は太きい。As explained in detail above, according to the present invention, a high-frequency brightness effect transistor having a via hole and a pH of 8 and having improved electrical characteristics and roughness can be obtained. n, so the effect is strong.
加、１区１は従来の高尚波筒出力１” ｇ ’１”の−
例の断面し１、第２図は本発明の一実旋し１」の断面図
、第３図（ａｌ〜（Ｃ）は本発明の一実施例の製造方法
を説明するだめの工程順に示した断面図である。
１・ ・・半導体基板、２・・・・・・穴、３ ・・放
熱層、４・・・・凹部、１１・・・・・半導体基板、１
２ 貫通孔、】２′・・・・・穴、】３ ・放熱層、
】４・・・・凹部、■）・・・ ドレイン電極、Ｇ・
・ゲート屯１ｍ、Ｓ 。
ソース電極。1 section 1 is the conventional high wave cylinder output 1" g '1" -
Example 1 and 2 are cross-sectional views of one example of the present invention, and Figures 3 (al to (C) are shown in order of steps to explain the manufacturing method of an embodiment of the present invention. 1... Semiconductor substrate, 2... Hole, 3... Heat dissipation layer, 4... Concavity, 11... Semiconductor substrate, 1
2 Through hole, ]2'... hole, ]3 ・Heat dissipation layer,
]4... Concavity, ■)... Drain electrode, G.
・Gate length 1m, S. source electrode.
Claims (1)
極と、前記半導体基板を貫通する貫通孔と、該貫通孔の
側面を覆いかつ半導体基板表面に伸ひるソース電極と、
前記半導体基板裏面に設けられ前記ソース′電極に前記
貫通孔側面で接続する放熱層とを含むことを９ザ徴とす
る高周波筒出力電界効果トランジスタ。a gate electrode and a drain electrode formed on a surface of a semiconductor substrate; a through hole penetrating the semiconductor substrate; a source electrode covering a side surface of the through hole and extending to the surface of the semiconductor substrate;
9. A high frequency cylindrical output field effect transistor comprising: a heat dissipation layer provided on the back surface of the semiconductor substrate and connected to the source electrode at a side surface of the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57232400A JPS59117171A (en) | 1982-12-23 | 1982-12-23 | High-frequency high-output field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57232400A JPS59117171A (en) | 1982-12-23 | 1982-12-23 | High-frequency high-output field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59117171A true JPS59117171A (en) | 1984-07-06 |
Family
ID=16938644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57232400A Pending JPS59117171A (en) | 1982-12-23 | 1982-12-23 | High-frequency high-output field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117171A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61187371A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US5324981A (en) * | 1988-07-01 | 1994-06-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor device with contact in groove |
| US6664640B2 (en) | 2001-07-30 | 2003-12-16 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5661170A (en) * | 1979-10-25 | 1981-05-26 | Mitsubishi Electric Corp | Preparation of field effect transistor |
| JPS56131963A (en) * | 1980-03-19 | 1981-10-15 | Nec Corp | Electric field effect transistor and its preparation |
| JPS5892277A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
-
1982
- 1982-12-23 JP JP57232400A patent/JPS59117171A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5661170A (en) * | 1979-10-25 | 1981-05-26 | Mitsubishi Electric Corp | Preparation of field effect transistor |
| JPS56131963A (en) * | 1980-03-19 | 1981-10-15 | Nec Corp | Electric field effect transistor and its preparation |
| JPS5892277A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61187371A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US5324981A (en) * | 1988-07-01 | 1994-06-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor device with contact in groove |
| US5434094A (en) * | 1988-07-01 | 1995-07-18 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a field effect transistor |
| US6664640B2 (en) | 2001-07-30 | 2003-12-16 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device |
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