JPS56131963A - Electric field effect transistor and its preparation - Google Patents

Electric field effect transistor and its preparation

Info

Publication number
JPS56131963A
JPS56131963A JP3546580A JP3546580A JPS56131963A JP S56131963 A JPS56131963 A JP S56131963A JP 3546580 A JP3546580 A JP 3546580A JP 3546580 A JP3546580 A JP 3546580A JP S56131963 A JPS56131963 A JP S56131963A
Authority
JP
Japan
Prior art keywords
source electrode
selectively
substrate
concave
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3546580A
Other languages
Japanese (ja)
Other versions
JPS6250991B2 (en
Inventor
Yoichi Aono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3546580A priority Critical patent/JPS56131963A/en
Publication of JPS56131963A publication Critical patent/JPS56131963A/en
Publication of JPS6250991B2 publication Critical patent/JPS6250991B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enhance the electric characteristics by a method wherein source and drain electrodes are arranged alternately on an active layer on semi-insulating substrate, gate electrode is formed at source electrode side from the center of active layer concave, while a thick gold plating is applied on the source electrode part connecting with the substrate penetrating through the active layer to improve heat dissipating. CONSTITUTION:An N epitaxial layer 32 is placed on semi-insulating GaAs 31 and an opening 34 is provided to SiO2 33 of the surface to make a concave by etching, and further an inpedenent mesa 32 is formed by selectively opening and etching. An AuGeNi alloy source electrode 35 or drain electrode 36 is formed selectively. Heat-treatment is applied in H2 to lower contact resistance and a thick Au plating 37 is applied on source electrode 35 only selectively. Next, when oblique evaporation 41 of Mo and Au in order are applied, gate electrode 38 is formed at the location closer to the side of source electrode 35 from the center of the concave through an opening 34. Removing the film 41 selectively to form pads 39 and 40, eliminating substrate 31 by polishing to expose plating layer 37, applying thick Au plate 42 to the thinly formed substrate 31 and fitting a cooling board 42, the process is completed.
JP3546580A 1980-03-19 1980-03-19 Electric field effect transistor and its preparation Granted JPS56131963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3546580A JPS56131963A (en) 1980-03-19 1980-03-19 Electric field effect transistor and its preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3546580A JPS56131963A (en) 1980-03-19 1980-03-19 Electric field effect transistor and its preparation

Publications (2)

Publication Number Publication Date
JPS56131963A true JPS56131963A (en) 1981-10-15
JPS6250991B2 JPS6250991B2 (en) 1987-10-28

Family

ID=12442527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3546580A Granted JPS56131963A (en) 1980-03-19 1980-03-19 Electric field effect transistor and its preparation

Country Status (1)

Country Link
JP (1) JPS56131963A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117171A (en) * 1982-12-23 1984-07-06 Nec Corp High-frequency high-output field-effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117171A (en) * 1982-12-23 1984-07-06 Nec Corp High-frequency high-output field-effect transistor

Also Published As

Publication number Publication date
JPS6250991B2 (en) 1987-10-28

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