JPS5950091B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPS5950091B2
JPS5950091B2 JP11634976A JP11634976A JPS5950091B2 JP S5950091 B2 JPS5950091 B2 JP S5950091B2 JP 11634976 A JP11634976 A JP 11634976A JP 11634976 A JP11634976 A JP 11634976A JP S5950091 B2 JPS5950091 B2 JP S5950091B2
Authority
JP
Japan
Prior art keywords
electrode
plating
manufacturing
semiconductor device
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11634976A
Other languages
Japanese (ja)
Other versions
JPS5341173A (en
Inventor
浅光 東坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11634976A priority Critical patent/JPS5950091B2/en
Publication of JPS5341173A publication Critical patent/JPS5341173A/en
Publication of JPS5950091B2 publication Critical patent/JPS5950091B2/en
Expired legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、さらに詳しくは
半絶縁性半導体を基板とするプレーナ型半導体装置の製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a planar semiconductor device using a semi-insulating semiconductor as a substrate.

近年半絶縁性半導体を基板として形成されるプレーナ構
造の半導体装置として各種の半導体装置が開発されてき
た。前記プレーナ構造の半導体装置の製造においては形
成された半導体装置の素子電極の一つを接地電極に短絡
させることがしばしば行なわれる。このような場合、通
常ボンディングワイヤを用いてなされてきたが、その接
地インダクタンスは相互インダクタンスの影響によリボ
ンディングワイヤの数を増しても5oItI程度以下に
抑うることは容易ではなく、いかにして接地インダクタ
ンスを減少させるかがプレーナ型素子の製造技術上の1
・つの大きな課題であつた。
In recent years, various semiconductor devices have been developed as semiconductor devices with a planar structure formed using a semi-insulating semiconductor as a substrate. In manufacturing a semiconductor device having a planar structure, one of the element electrodes of the formed semiconductor device is often short-circuited to a ground electrode. In such cases, bonding wires have usually been used, but due to the influence of mutual inductance, it is not easy to keep the grounding inductance below about 5oItI even if the number of bonding wires is increased. Decreasing the grounding inductance is the first step in manufacturing technology for planar elements.
・There were two major challenges.

この様な要請から従来例えばビームリードを用いた接地
方法が開発されてきた。この方法においては、例えば第
1図のごとく半絶縁性基板上11の半導体結晶層12を
用いたプレーナ型素子13の接地すべき電極14からビ
ームリード15、16を引き出し、このビームリードを
放熱板を兼ねたアース電極に熱圧着を行う。この場合に
は接地がボンディングワイヤのように「線」ではなく
「面」状の金属によつて行なわれるので接地インダクタ
ンスは極めて低減される。しかしながら、ビームリード
の熱圧着に熟練が要求されるし、さらには製造作業時に
ビームリードが曲つてしまうという危険もある等の欠点
があり、半導体装置の製造においてその量産性に乏しい
欠点があつた。本発明の目的は、前記従来の欠点を除去
せしめた量産性の優れた半導体装置の製造方法を提供す
ることにある。
In response to such demands, grounding methods using, for example, beam leads have been developed. In this method, for example, as shown in FIG. 1, beam leads 15 and 16 are drawn out from an electrode 14 to be grounded of a planar element 13 using a semiconductor crystal layer 12 on a semi-insulating substrate 11, and these beam leads are connected to a heat sink. Thermo-compression is applied to the ground electrode which also serves as a ground electrode. In this case, the ground is not a "wire" like a bonding wire.
Since this is done with "plane" metal, the grounding inductance is extremely reduced. However, there are drawbacks such as the need for skill in thermocompression bonding of the beam lead and the risk of the beam lead being bent during manufacturing, and the drawback is that it is not suitable for mass production in the manufacture of semiconductor devices. . SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which eliminates the above-mentioned conventional drawbacks and is excellent in mass production.

本発明によれば半絶縁性GaAs半導体を基板としてプ
レーナ型半導体装置を形成せしめた後、該′装置の素子
電極のうちの少なくとも一つの電極と接地電極とを短絡
せしめる半導体装置の製造方法において、形成せしめた
プレーナ型半導体装置の前記接地せんとする素子電極と
接地電極とを結ぶ連続した露出面を構成するように他の
部分を絶縁5被覆せしめた後、前記素子電極および接地
電極のいずれが一方が導電性保持台と接触するように保
持し、かつこれをめつき液中に完全に浸漬するように挿
入せしめて前記導電性保持台に通電して電気めつきを行
うことによつて素子電極と接地電極とを短絡せしめるこ
とを特徴とする半導体装置の製造方法が得られる。
According to the present invention, a method for manufacturing a semiconductor device includes forming a planar semiconductor device using a semi-insulating GaAs semiconductor as a substrate, and then short-circuiting at least one of the device electrodes and a ground electrode. After covering other parts of the formed planar semiconductor device with insulation 5 so as to constitute a continuous exposed surface connecting the element electrode to be grounded and the ground electrode, which of the element electrode and the ground electrode is The element is held so that one side is in contact with a conductive holder, and the element is inserted so as to be completely immersed in the plating solution, and electricity is applied to the conductive holder to perform electroplating. A method for manufacturing a semiconductor device is obtained, which is characterized in that an electrode and a ground electrode are short-circuited.

前記本発明は、本願発明者が発見した新らしい現象を利
用した量産性の優れた半導体装置の製造方法である。
The present invention is a method for manufacturing a semiconductor device with excellent mass productivity, which utilizes a novel phenomenon discovered by the inventor of the present application.

すなわち、従来の電気めつき法はめつきを施こしたい物
質が導電性物質にしか適用できず、比抵抗103〜10
10Ω−Cmの半絶縁性半導体物質に電気めつきを施こ
すことは全く不可能であつた。しかしながら本願発明者
が発見した新らしい現象によれば、半絶縁性半導体と該
表面の一部に設けられためつき用電極とを共にめつき液
中に浸漬せしめて前記めつき用電極に通電すると、めつ
き用電極を浸漬しない従来の方法ではめつき電流が殆ん
ど流れないため、めつきが全く施さなかつた条件、例え
ば設定電流密度4mA/Cnl霊、液温60℃の条件で
もめつきが容易に施され、しかもめつきが半絶縁性基板
表面を進行していく速さが、めつきが厚み方向に成長し
ていく速さの105倍程度と速いという全く新しい現象
が発明された。またこの現象は半絶縁性半導体表面に設
けた絶縁被膜表面には全くめつきされす、さらに半絶縁
性半導体表面を絶縁被膜によりめつき用電極を含む露出
面と、めつき用電極を含まない露出面とに分割した場合
電極を含む露出面にはめつきが行なわれ、分割に用いた
絶縁被膜を通り越してめつき電極を含まない露出面にま
でめつきが進行することはない。まためつき用電極とし
ては、必ずしも金属の蒸.着電極である必要はなく半導
体結晶でも或いは半絶縁性半導体物質の表面と単に接触
する導電体であつてもよく、例えば金属製のピンセツト
ではさむだけでもめつきが行なわれる。
In other words, the conventional electroplating method can only be applied to conductive materials, with a specific resistance of 103 to 10.
It was simply impossible to electroplate 10 ohm-cm semi-insulating semiconductor materials. However, according to a new phenomenon discovered by the inventor of the present application, when a semi-insulating semiconductor and a plating electrode provided on a part of the surface thereof are both immersed in a plating solution and the plating electrode is energized. In the conventional method in which the plating electrode is not immersed, almost no plating current flows, so plating can be performed under conditions where no plating is applied at all, such as at a set current density of 4 mA/Cnl and a liquid temperature of 60°C. A completely new phenomenon has been invented in which plating can be applied easily, and the speed at which plating progresses on the surface of a semi-insulating substrate is about 105 times faster than the speed at which plating grows in the thickness direction. . In addition, this phenomenon occurs when the surface of the insulating coating provided on the semi-insulating semiconductor surface is completely plated, and furthermore, the semi-insulating semiconductor surface is coated with the insulating coating on the exposed surface including the plating electrode and the exposed surface not including the plating electrode. When divided into exposed surfaces, plating is performed on the exposed surfaces containing the electrodes, and the plating does not progress past the insulating coating used for division to the exposed surfaces that do not contain the plating electrodes. Also, plating electrodes are not necessarily made of evaporated metal. It does not have to be a deposited electrode, but may be a semiconductor crystal or a conductor that simply contacts the surface of a semi-insulating semiconductor material. For example, plating can be carried out by simply pinching it with metal tweezers.

以下、前記新らしく発見した現象を利用した本.発明の
一実施例として半絶縁性半導体物質として半絶縁性Ga
As結晶、半導体結晶層としてn型GaAs結晶層を用
いてなるGaAsシヨツトキ一障壁ゲート型電界効果ト
ランジスタの製造方法を例にとり、詳しく説明する。
Below are books that utilize the newly discovered phenomenon mentioned above. As an embodiment of the invention, semi-insulating Ga is used as the semi-insulating semiconductor material.
A method for manufacturing a GaAs shot-barrier gate field effect transistor using an n-type GaAs crystal layer as an As crystal and a semiconductor crystal layer will be explained in detail by taking as an example.

GaAsシヨツトキ一障壁ゲート型電界効果トランジス
タ(以下GaAsSBFETと称す)は半絶縁性GaA
s結晶表面に設けられたn型GaAs結晶層にソース・
ドレインと称するオーム性電極と、シヨツトキ一障壁接
合のゲート電極とによつて構成された三端子素子であり
、特にX−バンド以上の高周波帯においては電力利得、
雑音特性ともに従来のSiバイポーラトランジスタを上
回る素子として期待されている。
A GaAs short-barrier gate field effect transistor (hereinafter referred to as GaAs SBFET) is a semi-insulating GaA
A source and an n-type GaAs crystal layer provided on the s-crystal surface
It is a three-terminal device consisting of an ohmic electrode called the drain and a gate electrode with a short barrier junction, and it has a high power gain, especially in high frequency bands above the X-band.
It is expected that the device will have better noise characteristics than conventional Si bipolar transistors.

ここでは、GaAsSBFETのソース電極を接地する
場合を例にとつて本発明を具体的に説明する。
Here, the present invention will be specifically explained using an example in which the source electrode of a GaAs SBFET is grounded.

素子製造にあたつては第2図Aにおいて、まず半絶縁性
基板11上にキヤリア密度が例えば1×1017/Cm
、厚みが例えば0.25μのn型GaAs結晶層を形成
して後、動作領域となる領域を残して他の領域をエツチ
ング除去しメサ状の動作領域12をうる。次に該メサ状
の動作領域表面にソース21.ゲート22、ドレイン2
3を形成しGaAsSBFETの原形をうる。ここでゲ
ート長は例えば1μ、ソース・ドレイン間距離は例えば
4μ、ゲート幅は例えば300μとする。またゲート、
ソース(ドレイン)の材料は各夕例えばアルミニウム(
A1)、金(Au)−ゲルマニウム(Ge)合金とする
。次に、ウエハ全面に例えば熱分解法によりSiO2膜
(厚みは例えば0.5μ) 74を形成し、さらに適当
なホトレジストマスクを設けた後、ゲート、ソース、ド
レインの各電極に対応した部分のSiO2膜を除去し、
さらにウエハを切断分離することにより第2図Aに示す
ごときペレツトをうる。次に半絶縁性基板゛およびSi
O2膜で覆われていない動作領域表面に電流密度が例え
ば4mA/Crff液温例えば50℃の条件でめつきを
施せば、第2図Bに示すごとくソース電極22が金(A
u)めつき層によつて基板の裏側と短絡された素子がえ
られる。次に具体的なめつき方法についていくつかの実
施例を示す。まずめつき用電極としては、第2図Aのソ
ース電極21あるいはドレイン電極23を利用すること
が可能である。この場合半絶縁性基板11への金(Au
)めつきはソース電極端25から進行し、該基板の裏面
を覆うごとくなる。なおこの場合には基板の裏面に直接
金(Au)めつき膜が付着するので素子の半田付の際そ
れらの接着性が問題になる場合には、ペレツトの裏面2
6にクロム(Cr)一金(Au)等の金属を蒸着してお
いてもよくこの場合該クロム一金蒸着膜をめつき用電極
とすることも可能てある。
In manufacturing the device, first, as shown in FIG. 2A, a carrier density of, for example, 1×10 17 /cm
After forming an n-type GaAs crystal layer having a thickness of, for example, 0.25 μm, a mesa-shaped operating region 12 is obtained by etching away the remaining region except for a region that will become an operating region. Next, a source 21. Gate 22, drain 2
3 to obtain the original form of GaAsSBFET. Here, the gate length is, for example, 1μ, the source-drain distance is, for example, 4μ, and the gate width is, for example, 300μ. Also the gate,
The source (drain) material should be changed each evening, e.g. aluminum (
A1), a gold (Au)-germanium (Ge) alloy. Next, a SiO2 film (thickness: 0.5 μm, for example) is formed on the entire surface of the wafer by, for example, a thermal decomposition method, and after a suitable photoresist mask is provided, SiO2 film 74 is formed on the portions corresponding to the gate, source, and drain electrodes. remove the membrane,
Further, the wafer is cut and separated to obtain pellets as shown in FIG. 2A. Next, a semi-insulating substrate and Si
If plating is performed on the surface of the operating region not covered with the O2 film at a current density of, for example, 4 mA/Crff and a liquid temperature of, for example, 50°C, the source electrode 22 will be made of gold (A) as shown in FIG. 2B.
u) A plating layer results in an element short-circuited to the back side of the substrate. Next, some examples of specific plating methods will be shown. First, the source electrode 21 or drain electrode 23 shown in FIG. 2A can be used as the plating electrode. In this case, gold (Au) is applied to the semi-insulating substrate 11.
) The plating progresses from the source electrode end 25 and covers the back surface of the substrate. In this case, the gold (Au) plating film is directly attached to the back side of the substrate, so if the adhesion of the film is a problem when soldering the element, the back side 2 of the pellet should be removed.
A metal such as chromium (Cr) and gold (Au) may be deposited on the layer 6, and in this case, the chromium and gold deposited film can be used as a plating electrode.

一方、電気めつきを行う場合には各素子のめつき用電極
にめつき用電圧を加えることが必要であるが、この場合
素子1個1個にリード線を設けることは極めて非能率的
であり量産性がない。従つて、第3図Aに示すごとく金
属製のバスケツト34を用い該バスケツトの中にペレツ
ト33を入れてめつきを行うことができる。第3図Bは
、金属製の板35をリード線として用いた場合である。
第3図において、金属製のバスケツト34、板35は前
記各ペレツトのめつき用電極にめつき用の電圧を与える
ためのものであるが、該バスケツトあるいは板の表面が
該めつき用電極と接触せず半絶縁性基板の表面と接触し
た場合にもその接触部からめつきが進行し第2図Bのご
とくソース電極とペレツト裏面が短絡された素子をうる
ことが可能である。第2図、第3図で説明した実施例で
はウエーハはペレツト状態に切断分離されているが、本
発明における方法はウエーハが完全にペレツト化されて
おらず例えば第4図に示すように各素子41が例えばプ
レーテツドヒートシンク (Platedheatsi
nk)42上に互いに分離して形成されている場合にも
適用できる。
On the other hand, when performing electroplating, it is necessary to apply a plating voltage to the plating electrode of each element, but in this case it is extremely inefficient to provide a lead wire for each element. Yes, it is not suitable for mass production. Therefore, as shown in FIG. 3A, plating can be carried out by using a metal basket 34 and placing pellets 33 in the basket. FIG. 3B shows a case where a metal plate 35 is used as a lead wire.
In FIG. 3, a metal basket 34 and a metal plate 35 are used to apply a plating voltage to the plating electrode of each pellet, but the surface of the basket or plate is connected to the plating electrode. Even in the case of contact with the surface of a semi-insulating substrate without contact, plating progresses from the contact portion, and it is possible to obtain an element in which the source electrode and the back surface of the pellet are short-circuited, as shown in FIG. 2B. In the embodiment explained in FIGS. 2 and 3, the wafer is cut and separated into pellets, but in the method of the present invention, the wafer is not completely pelletized and each element is separated as shown in FIG. 41 is, for example, a plated heat sink.
This can also be applied to the case where they are formed separately from each other on the 42.

第4図における素子は第2図において説明したと同様に
半絶縁性基板上のn型動作層を用いて素子を形成したあ
と、半絶縁性基板の裏面に例えば厚さ500μの金(A
u)膜(プレーテツド・ヒート・シンク)92を例えば
金(Au)めつきによつて形成し、しかる後に動作領域
表面に適当なホツトレジストマスクをかぶせて後、基板
を選択的に化学エツチングして除去することによりえら
れるものであるが、この様な素子に本発明によるめつき
方法を適用する場合には、前記プレーテツドヒートシン
クをめつき用電極として電気めつきを行なえばよい。こ
の場合には、ノース電極とプレーテツドヒート・シンク
が半絶縁性基板の側面にめつきされた金(Au)層によ
つて短絡される。以上、この発明における素子製造方法
を用いれば接地すべき電極と素子ペレツトの裏面とが金
属膜で短絡されるので接地インダクタンスの小さい素子
を製造することが可能である。
In the device shown in FIG. 4, the device is formed using an n-type active layer on a semi-insulating substrate in the same manner as explained in FIG.
u) forming a film (plated heat sink) 92, for example by gold (Au) plating, and then covering the active area surface with a suitable photoresist mask and selectively chemically etching the substrate; However, when applying the plating method according to the present invention to such an element, electroplating may be performed using the plated heat sink as a plating electrode. In this case, the north electrode and the plated heat sink are shorted by a gold (Au) layer plated on the side of the semi-insulating substrate. As described above, if the device manufacturing method of the present invention is used, the electrode to be grounded and the back surface of the device pellet are short-circuited by the metal film, so it is possible to manufacture a device with small grounding inductance.

さらにこの方法において製造された素子においては、素
子を放熱板に半田付けを行うとき、素子の接地も自動的
に行なわれるので、接地用のボンデイング工程が省かれ
るという利点がある。
Furthermore, in the device manufactured by this method, when the device is soldered to the heat sink, the device is automatically grounded, so there is an advantage that the bonding step for grounding can be omitted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はビーム・リードを用いたプレーナ型素子の接地
方法を示す図、第2図、第3図、第4図は本発明におけ
るめつき方法をプレーナ型素子の接地に応用する場合の
接地例を示す。 図において、11・・・・・・半絶縁性GaAs基板、
12・・・・・・ n型GaAs結晶層、13・・・・
・・プレーナ型素子、14・・・・・・接地すべき電極
、15,16・・・・・・ビームリード、21・・・・
・・ソース電極、22・・・・・・ゲート電極、23・
・・・・・ドレイン電極、24・・・・・・SiO。
Fig. 1 is a diagram showing a method of grounding a planar type element using a beam lead, and Figs. 2, 3, and 4 are diagrams showing grounding when the plating method of the present invention is applied to grounding of a planar type element. Give an example. In the figure, 11... semi-insulating GaAs substrate,
12... N-type GaAs crystal layer, 13...
...Planar type element, 14... Electrode to be grounded, 15, 16... Beam lead, 21...
... Source electrode, 22 ... Gate electrode, 23.
...Drain electrode, 24...SiO.

Claims (1)

【特許請求の範囲】[Claims] 1 半絶縁性、GaAs基板上にプレーナ型半導体装置
を形成せしめたあと、該装置の電極のうちの少なくとも
接地せんとする1つの電極と基板裏面の接地電極とを短
絡せしめる半導体装置の製造方法において、前記接地せ
んとする電極と接地電極とを結ぶ連続した露出面を形成
するように他の部分を絶縁被覆せしめたあと、前記接地
せんとする電極および接地電極の少なくとも一方が導電
性の保持台と接触するように保持し、かつこれをめつき
液中に完全に浸漬せしめて前記導電性保持台に通電して
前記露出面に電気めつきを行うことによつて前記接地せ
んとする電極と接地電極とを短絡せしめることを特徴と
する半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, which comprises forming a planar semiconductor device on a semi-insulating GaAs substrate, and then short-circuiting at least one of the electrodes of the device to be grounded and a ground electrode on the back surface of the substrate. , after insulating other parts so as to form a continuous exposed surface connecting the electrode to be grounded and the grounding electrode, a holding table in which at least one of the electrode to be grounded and the grounding electrode is conductive; The electrode to be grounded is held in contact with the electrode, completely immersed in a plating solution, and electrically applied to the exposed surface by energizing the conductive holding base. A method for manufacturing a semiconductor device, comprising short-circuiting a ground electrode.
JP11634976A 1976-09-28 1976-09-28 Manufacturing method of semiconductor device Expired JPS5950091B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11634976A JPS5950091B2 (en) 1976-09-28 1976-09-28 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11634976A JPS5950091B2 (en) 1976-09-28 1976-09-28 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5341173A JPS5341173A (en) 1978-04-14
JPS5950091B2 true JPS5950091B2 (en) 1984-12-06

Family

ID=14684744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11634976A Expired JPS5950091B2 (en) 1976-09-28 1976-09-28 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5950091B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255265U (en) * 1985-09-27 1987-04-06

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612742A (en) * 1979-07-11 1981-02-07 Fujitsu Ltd Semiconductor device
JPS5837005A (en) * 1981-08-31 1983-03-04 Mitsui Toatsu Chem Inc Removal of volatile matter from thermoplastic resin

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6255265U (en) * 1985-09-27 1987-04-06

Also Published As

Publication number Publication date
JPS5341173A (en) 1978-04-14

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