JPH036817A - Manufacture of multilayer electrode of semiconductor element - Google Patents

Abstract

PURPOSE:To improve adhesion between layers and to prevent peeling by covering the outer periphery of a first metal layer in contact with a silicon semiconductor region made of aluminum with an insulating film, and sequentially forming an aluminum layer, a metal layer having desirable adhesive properties to the aluminum layer and a nickel layer, and the nickel layer by depositing. CONSTITUTION:An AI layer is formed on the whole upper region of a semiconductor substrate 1 by a known depositing method, partly removed by etching, and the AI layer 8 and an EQR AI layer 9 remain. After a silicon oxide film is formed on the whole upper region by a CVD method, the center of the element and the periphery of the element are removed by etching, and a silicon oxide film 10 is formed. The upper surface of the layer 8 is etched with HF, and the oxide film is removed. A second AI layer, a Ti layer and a Ni layer are sequentially deposited in vacuum on the whole upper region, the periphery of the element is removed by etching, and an AI layer 12, a Ti layer 13 and a Ni layer 14 are formed. Accordingly, the oxidation, corrosion of the layers 8, 9 is prevented, the breakdown strength of the outer periphery is improved. Adhesion between the layers is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing multilayer electrodes for semiconductor devices such as diodes, transistors, and ICs.

[Prior art and the problem to be solved by the invention] A multilayer electrode consisting of an Al (aluminum) layer and a Ti (nickel layer and Ni) N is formed by vacuum evaporation on a silicon semiconductor element (silicon conductor chip). In this AI-Ti-Ni71L electrode, the 41st layer has good adhesion with the silicon semiconductor element regardless of the conductivity type of the semiconductor region to be connected.
It also functions as a contact metal layer that provides good ohmic contact with the silicon semiconductor element, and N
The i-layer has good solder adhesion and functions as a metal layer for soldering, and is a glue metal layer that is interposed between the Ti layer, the iAI layer, and the Ni layer to improve the adhesion between both layers. Therefore, the above-mentioned AI-Ti-Ni electrode is an ideal electrode that allows good soldering of the lead electrode and has good adhesion to the semiconductor element.

The inventor of the present application applied the above AI-Ti-Ni electrode to the electrode of a planar type PN junction diode, and in one embodiment, the lower 41 layers were extended to the outer circumferential side of the Ni layer, and this one layer was Al functioned as a field plate
-An attempt was made to produce a Ti-Ni electrode.

In this case, the 41st layer will corrode due to long-term use, and it may also cause damage to the absolute R withstand voltage.
It is desirable to cover the outer periphery of the <41 layer serving as a field plate with a protective film to improve reliability. The inventor of this application manufactured the above AI Ti-Ni electrode using the following two manufacturing methods. In the first method, a thermal oxide film is first formed on the upper surface of a semiconductor element, and then a central portion of the thermal oxide film is removed by etching.

Next, after the 41st layer, the Ti layer, and the Ni layer are vacuum-deposited in sequence, the periphery of the Ni layer and the Ti layer is removed by etching to expose the 41st layer functioning as a field plate. next,
A protective film (insulating film) made of a silicon oxide film or the like is formed on the exposed upper surface of the 41 layer by CVD (vapor phase growth) or the like.In the second method, a thermal oxide film is first formed on the upper surface of the semiconductor element. After that, the central portion of the thermal oxide film is removed by etching.

Next, after vacuum-depositing 41 layers, a protective film made of a silicon oxide film or the like is formed on the upper surface of the first layer on the side around the element by CVD or the like. Next, a Ti layer and a Ni layer are placed on the top surface of the semiconductor element.
The layers are vacuum deposited one after another, and the deposited layers are etched away from the device periphery. However, it has been found that the AI-Ti-Ni electrodes formed by the above two manufacturing methods have the following problems. That is, in the first method, the upper surface of the Ni layer is oxidized during the formation of the protective film, and its solder adhesion is impaired. An attempt was made to etch the upper surface of the Ni layer.
Since it is generally formed as thin as 0^, it is difficult to selectively remove just the oxide film, and if the oxide film is sufficiently removed to sufficiently improve adhesion, the Ni layer will be thinner than necessary. There were five times when I removed the etching. Also, in method 1 and 2.

The upper surface of the 41st layer was oxidized during the formation of the protective film, resulting in poor adhesion between the AI shoulder and the upper Ti layer, and peeling occurred between the two layers. In this case, KAI before depositing the Ti layer
It is considered that etching the upper surface of the layer is sufficient. However, even with this, peeling cannot be sufficiently prevented.
The yield did not increase much.

Therefore, an object of the present invention is to provide a means for solving the above problems.

[Means for Solving the Problems] To achieve the above object, the present invention includes a first step of preparing a semiconductor substrate in which at least one main surface bottoms out from a silicon semiconductor region; a second step of forming a first metal layer made of aluminum on the surface so that at least a portion thereof contacts the silicon semiconductor region; a second metal layer made of aluminum on the upper surface of the first metal layer; and a metal layer that has good adhesion to the aluminum layer and the nickel layer and is made of a material other than aluminum and nickel. This relates to a method for manufacturing a multilayer electrode for a semiconductor device, comprising a fourth step of sequentially forming a third metal layer made of metal and a fourth metal layer made of nickel by vapor deposition. be.

Also, if you want a field plate structure.

A first insulating film is provided under the outer periphery of the first metal layer,
It is desirable to provide a second insulating film on the outer periphery of the metal layer.

[For production]

According to the invention described in claim 1, since the outer peripheral portion of the first metal layer made of aluminum is covered with an insulating film (protective film), oxidation and corrosion of the first gold tt4h are prevented, and , the dielectric strength voltage at the outer peripheral part of the first metal layer is improved.Also, since both the first metal layer and the second metal layer are made of aluminum, the first metal layer and the second metal layer
A layer that can be called a solid solution layer (solid solution region) is formed between the metal layers, and the two layers adhere well.Also, although the second, third, and fourth metal layers are made of different metal materials, Since the layers are formed sequentially without intervening an insulating film formation step, good adhesion can be obtained between the second metal layer and the third metal layer and between the third metal layer and the fourth metal layer. .

According to the second aspect of the invention, the outer peripheral portion of the first metal layer can function well as a field plate.

[First Embodiment] A method for manufacturing a planar PN junction diode according to a first embodiment of the present invention will be described below.

In order to form the Brehner type PM junction diode of this embodiment shown in FIG. This semiconductor substrate 1 includes a +N region 2 of a first conductivity type, an N region 3 formed on its top surface, and a second conductivity type region 3 formed within the N region 3 so that its top surface is exposed. It has a P region 4 and an N region 5. Here, N area 3
and N+ region 2 constitute a cathode region of the PN junction diode, and P region 4 constitutes an anode region. N+ region 5 is spaced apart from P+ region 4 and surrounds it in an annular manner.

Next, the semiconductor substrate 1 is subjected to heat treatment in an oxidizing atmosphere,
#! - Form a silicon oxide film with a thickness of approximately 1 μm over the entire upper surface of the conductive substrate 1. Note that this silicon oxide film may be a thermal oxide film formed during the diffusion of the P+ region 4 and the N+ region 2. Subsequently, the silicon oxide film was etched away from the center of the device and the peripheral portion of the device, as shown in Figure 1).
As shown in , the first silicon oxide as the first insulating film! 6-31 remains. This first silicon oxide M
The exposed surface portion of the PN junction 70 between the 6FiN region 6 and the P region 4 is covered.

Next, Al@ as a first metal layer is formed over the entire upper surface of the semiconductor substrate 1 by a well-known vacuum evaporation method.

Subsequently, this vapor deposited A1 layer is partially etched away,
A first A1 layer 8 and an EQR (equipotential ring) layer 9 are left in FIG. A central portion of layer 8 is in ohmic contact with the upper surface of P region 4 exposed on the upper surface of semiconductor substrate 1 .

The outer peripheral portion of the 10th A1 layer 8 is covered with a first silicon oxide film 6.
It extends over the N region 3 and beyond the exposed portion of the PN junction 7 . Therefore, the outer peripheral portion of the first A1 layer 8 is adjacent to the N region 3 via the first silicon oxide film 6, acts as a well-known field plate, and contributes to improving the peripheral breakdown voltage of the PN junction 7. E remaining in a ring shape
QR A layer 1 layer 9 is in ohmic contact with the annular N+ region 5 exposed on the upper surface of the semiconductor substrate 1. This A1
Layer 9 and N region 5 act as a well-known EQR (equipotential ring) and contribute to stabilizing the withstand voltage of PN junction 7.

Next, after or without sinking the A1 layer 8.9,
The entire upper surface of the semiconductor substrate 1 is coated with a thickness of about 1 μm by CVD method.
After forming a silicon oxide film, the central and peripheral parts of the silicon oxide film are removed by etching to form a second silicon oxide film as a second insulating film, as shown in FIG. form 10. This second silicon oxide film 10
covers the entire upper surface of the A1 layer 9 for the equipotential ring and the upper surface of the outer peripheral portion of the first A1 layer 8 for the ohmic electrode. Second
An opening 11 for exposing the first A1 layer 8 for an ohmic electrode is formed in the center of the silicon oxide film 10 of the device. Note that the opening 11 is arranged inside the surface exposed portion of the PN junction 7.

Next, before vacuum-depositing the second metal layer on the top surface of the first 41 layer 8, the top surface of the first A1 layer 8 is etched with an HF (hydrofluoric acid) based etching solution. The oxide film formed when forming the silicon oxide film 10 of No. 2 is removed. Note that if the oxide film on the upper surface of the first 41 layer 8 is extremely thin, it may remain.

Next, a second A1 layer, a Ti layer, and a Ni layer are sequentially vacuum-deposited over the entire upper surface of the semiconductor substrate 1, and then the parts around the device of these deposited layers are removed by etching, as shown in the 11th = η■. , a second A1 layer (second metal layer) 12, a Ti layer (third metal layer) 16, and a Ni layer (fourth metal layer) 14 are formed. Note that for the A1 layer, Ti layer, and Ni layer, the deposition materials are sequentially switched to A1Ti and NiK while maintaining a low pressure atmosphere;
It is formed by a so-called sequential vapor deposition method. Second AI layer 12
The thickness of the Ti layer 13 and the 81 layer 14 is 5000 mm, respectively.
A, 1000A, and 5000A. Second AI
Layer 12 is in contact with first A1 layer 8 through opening 11 .

It is electrically connected to the first 41 layer 8 together with the Ti layer 13 and the 81 layer 14, and an anode electrode 15 is formed by these. The outer peripheral ends of the second AI layer 12, Ti layer 16, and 81 layer 14 are spaced apart from the edge of the opening 11 of the second silicon oxide film 10. Therefore, the second AI layer 12, Ti
A part of the surface of the first A1 layer 8 is exposed on the outer peripheral side of the layer 13 and the N1 layer 14.

However, this exposed area is only small.

Oxidation or corrosion of this part does not cause problems with the characteristics or reliability of the electrode. After that, sinking is performed at 300° C. to 400° C. to improve the adhesion between the first 41 layer 8 and the second AI layer 12. Further, on the lower surface of the 1,000-hundred-thousand substrate 1, as shown in FIG.

According to the manufacturing method of this embodiment, the following effects can be obtained.

(1, 1 The outer peripheral portion of the first A1 layer 8 not covered by the second AI layer 12, the Ti layer 13, and the first layer 14 is
It is covered with a silicon oxide film 10 to prevent its corrosion. Therefore, the first 41 layer 8 functions well as an anode electrode and a field plate. Also,
The dielectric strength voltage of the first 41 layers 8 and the EQR A layer 1 layer 9 can be sufficiently increased, and problems with dielectric strength zones do not occur.

(2) Since the 81 layer 14 is formed after forming the second silicon oxide film 10 covering the first 41 layer 8, N
Oxidation of the first layer 14 does not occur. Therefore, good solder adhesion of the 81 layer 14 can be obtained.

(3) Second AI layer 12, Ti layer 13 and 81 layer 14
Since it is continuously vapor-deposited, good adhesion between the AI layer 12 and the TiJi@13 and between the Ti layer 16 and the 81 layer 14 can be obtained. In addition, although the step of forming the silicon oxide film 10 is interposed between the step of forming the first A1 layer 8 and the step of forming the second AI layer 12, the first and second A1 layers 8, 12 Since they are the same metal layer, both layers adhere well. That is,
When the surface of the first A1 layer 8 is chemically treated before forming the second AI layer 12, even if an extremely thin oxide film remains on the first AI layer 8, the first and second Since the A1 layer 8.12 of is bonded by a solid solution layer formed by solid solution,
Adhesion between both layers is sufficiently high. As a result, peeling between the first A1 layer 8 and the second A1 layer 12 is prevented, and 41
The chemical treatment process for layer 8 can be simplified. In addition,
The second AI layer 12 can be formed by continuous deposition using the deposition process of the ViTi layer 16 and the 81 layer 14, and its thickness is also 5.
000A, the manufacturing process does not become so complicated by providing this.

(4) 81 layers 14 with good solder adhesion in plan view
A first A1 layer 8 having poor solder adhesion adjoins and surrounds the outer peripheral side of the electrode. Therefore, the lead electrode is 81
When soldering to layer 14, the solder spreads only on the top surface of Ni skin 14 and #! The knee field does not spread to the outer periphery of the first A1 layer 8 that serves as a field plate. As a result, there is no phenomenon in which the peripheral part of the electrode (in this case, the outer peripheral part of the A1 layer 8) peels off due to tensile stress, etc. due to manual solidification, so that the mechanical strength It is possible to form a multilayer electrode with a large number of layers.

[Second Embodiment] Next, a method for manufacturing a Brehner type PN junction diode according to a second embodiment of the present invention will be described.

In this example, a PN junction diode shown in FIG. 2 is manufactured. To form the PN junction diode shown in FIG.
As in the embodiment described above, a semiconductor substrate 1 shown in FIG. 1 is first prepared. Thereafter, this semiconductor substrate 1 is subjected to the same steps as in the first embodiment to prepare the semiconductor substrate 1 shown in FIG. 10. Next, an A1 layer and a T layer are formed over the entire upper surface of this semiconductor substrate 1.
The i layer and the Ni layer are successively deposited, and then these deposited layers are selectively removed by etching, and as shown in FIG. A second A1 layer 12, 17 layer 13 and N7 layer 14 are formed. Note that the second A1 layer 12. Ti layer 16 and N7
The outer peripheral end of the layer 14 is also located inside the outer peripheral end of the first A1 layer 8. First and second A1 layer 8° 12.17 layer 13
, the N7 layer 14 functions as the anode electrode 15, and the 11th
A portion of the A1 layer 8 extending over the upper surface of the N region 3 functions as a field plate.

Note that, as in the first embodiment, a T
A cathode electrode 16 is formed by successively depositing i and Ni.

The second embodiment has the same effects as (1) to (31) of the first embodiment, and also has the second A1 layer 12, 17 layer 13
It also has the effect that the N7 layer 14 can be selectively and well etched. That is, in the first embodiment, since the first A1 layer 8 and the N2 A1 layer 12 are continuous in the etched region, the N2 A1 layer 12 is
It is difficult to accurately etch up to the boundary with the A1 layer 8. On the other hand, according to the second embodiment, the first
Since silicon oxide M1° is present between the A1 layer 8 and the second A1 layer 12, the second A1 layer 12 can be easily etched away in a controlled manner up to the interface of the oxide film 1D. be able to. Furthermore, peeling of the electrode around the periphery does not pose a practical problem because the adhesion between the second A1 layer 12 and the second silicon oxide film 1Q is relatively good.

[Modified example from this book E! A is not limited to the above embodiments,
For example, the following transformations are possible.

(11) In the first embodiment, the outer peripheral edge of the second A1 layer 12 may be adjacent to the edge of the opening 11 of the silicon oxide M10.

(2) Cr instead of 17 layer 13 as the green metal layer
(chromium) layer may be provided.

(31 In the second example, 17 layers 13 and NiN1
4 is formed inside the second A1 layer 12, and the second AI/ii! 12, Ti layer 16 and N7 layer 14
It may be extended to the outer periphery side. In this case, the cracks spread only on the upper surface of the N7 layer 14 and are not formed on the upper surface of the A1 layer 12, so that peeling at the interface between the A1 layer 12 and the second silicon oxide film 10 can be more reliably prevented. I can do it. In this case, the structure is such that the periphery of the second A1 layer 12 is exposed, but the exposed portion 1jTiii pole 1 of the second A1 layer 12
3 and the first A1 layer 8 or does not directly function as a field plate, corrosion of this portion hardly affects the characteristics. Furthermore, since the upper surface of the first A1 layer 8 is covered with the second silicon oxide film 10, corrosion of the second A1 layer 12 affects the surface of the first AI layer 8'P semiconductor substrate 1. Never.

f41 The second A1 layer 12#: is well adhered to the first A1 layer 8 by the solid solution layer, so it does not need to be formed thickly. Taking into account the shortening of the vacuum deposition process, the second A
The thickness of one layer 12 may be 2 μm or less, preferably 1 μm or less.

(5) The present invention can also be applied to a case where the first A1 layer 8 is formed only inside the P@ region 4 when viewed in plan (a case where no field grating is provided).

〔Effect of the invention〕

As described above, according to the manufacturing methods of claims 1 and 2, good adhesion between the semiconductor element and the insulating film, good solder adhesion, and adhesion between each layer can be obtained, and the first material made of aluminum can be A highly reliable multilayer electrode in which the outer periphery of the metal layer is covered with an insulating film to reliably prevent oxidation and corrosion can be formed with high yield and with relative ease. According to the manufacturing method of claim 2, a good field plate effect can be obtained.

[Brief explanation of the drawing]

Figures 1-3 are cross-sectional views for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention in the order of steps, and Figure 2 is a cross-sectional view showing the semiconductor device according to the second embodiment of the present invention. It is. 1... Semiconductor substrate, 6... First silicon oxide film. 8... First A1 layer, 10... Second silicon oxide film. 12... Second A1 layer, 16... Ti layer, 14...
・Ni layer.

Claims (1)

[Scope of Claims] [1] A first step of preparing a semiconductor substrate having at least one main surface made of a silicon semiconductor region, and at least a first metal layer made of aluminum on one main surface of the semiconductor substrate. a second step of forming a portion of the first metal layer in contact with the silicon semiconductor region; a third step of covering an outer peripheral portion of the first metal layer with an insulating film; and an upper surface of the first metal layer. a second metal layer made of aluminum; a third metal layer that has good adhesion to the aluminum layer and the nickel layer and made of a metal other than aluminum and nickel; and a fourth metal layer made of nickel. a fourth step of sequentially forming metal layers by vapor deposition. [2] A first step of preparing a semiconductor substrate whose at least one main surface is a first semiconductor region of a first conductivity type made of silicon; a second semiconductor region of a second conductivity type opposite to the first conductivity type; and at least an exposed surface portion of a PN junction between the first semiconductor region and the second semiconductor region and a second step of forming a first insulating film covering the vicinity thereof and having an opening exposing the second semiconductor region, contacting the second semiconductor region through the opening, and contacting the second semiconductor region through the opening; At least the PN via the first insulating film
a third step of forming a first metal layer made of aluminum located above the exposed surface of the bond and the vicinity thereof; and forming a second insulating film covering the outer periphery of the first metal layer. a fourth step; a second metal layer made of aluminum on the upper surface of the first metal layer; a metal layer having good adhesion to the aluminum layer and the nickel layer, and a metal other than aluminum and nickel; A method for manufacturing a multilayer electrode for a semiconductor device, comprising a fifth step of sequentially forming a third metal layer made of nickel and a fourth metal layer made of nickel.