TWI284419B - Schottky barrier diode and process - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
Description
案號 91 ]J/774q 1284419Case No. 91 ]J/774q 1284419
五 發明說明（1) [發明之詳細說明] [發明所屬技術領域] 本發明係關於高頻 % 面 體 特基屏障二極體及其製造方：所合物半導 構造以實現：作領域及晶圓尺寸π關於藉由形成平 之肖特基屏P早二極體及其製造。t之化合物 [先行之技術] 隨著世界各國行動 送接收機器的需求量也隨之增加，<二古=於數位衛星傳 急速成長。在高頻裝置元件方面， 裴置的需求量 使用鎵、石申（GaAs)之場效電晶！t，因:頻^用，其多 路予以集成化之單石微波積體電路（m 將則述開關電 F E T之開發亦隨之蓮勃發展。 、局部震逯用 此外，GaAs肖特基屏障二極體在基地台 上亦大幅增加。 寺之使用需求 第9圖，顯示傳統之肖特基屏障二極體 分之剖面圖。 動作領域部 在n+型GaAs基板上層疊約m左右之n+型磊日 〔5x 1018Cnr3)後，再層疊約莫 ％曰 蠢晶層23( H 10ncm-3)。 之作為動作層的η型 形成電阻電極28的第1層金屬層，係與η+型蠢晶層22 電阻連接之AnGe/Ni/Au。而第2層的金屬層係Ti/Pt=Au曰， 第2層金屬層之圖案具有陽極側與陰極側之2種類。在陽極 側开> 成與η型蟲晶層2 3之肖特基連接。以下，將具有今肖。[Description of the Invention] (1) [Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a high frequency % facet barrier barrier and a manufacturer thereof: a semiconductor structure to achieve: The wafer size π is related to the fabrication of the early diode by forming a flat Schottky screen P. The compound of t [advanced technology] As the demand for receivers in various countries around the world increases, < Ergu = rapid growth in digital satellite transmission. In terms of high-frequency device components, the demand for the device is the use of gallium, Shishen (GaAs) field effect crystal! t, because: frequency use, its multi-channel integrated monolithic microwave integrated circuit (m will be described in the development of switching electrical FETs will also develop with the development of the local shock. In addition, GaAs Schottky barrier The diodes have also increased significantly on the base station. The use of the temple is shown in Figure 9, which shows a cross-section of the traditional Schottky barrier diode. The action field is stacked on the n+ GaAs substrate by about n+. After Lei Ri [5x 1018Cnr3), about 5% of the stupid layer 23 (H 10ncm-3) was laminated. The n-type barrier layer forming the resistive electrode 28 is an anGe-Ni/Au electrically connected to the η+-type stray layer 22. On the other hand, the metal layer of the second layer is Ti/Pt=Au, and the pattern of the second metal layer has two types of the anode side and the cathode side. On the anode side, it is connected to the Schottky of the n-type crystal layer 23. Below, there will be this Xiao.
313891.ptc 第10頁 案號 9Π17740 1284419 修正 曰 五、發明說明（2) 特基連接領域3 1 a之陽極側的篦9思人β p Π1 士 弟2層金屬層稱之為肖特基電 極3卜為特基電極31亦可成為形成陽極接合墊之第綠^ 電鑛層的底部電極而使兩者之固索 曰 荼完全重疊。除極側之箆 2層金屬層與電阻電極接觸， Λ ΤΤ^ ^ BL 成為^成陰極接合墊之第3層 A U電鐘層的底部電極，而盘陽搞 舌田 甘# L ^ ％極側相同，兩者之圖案完全 重豐。基於肖特基電極3 1，必須脾兮闽在山 ^ ^ ^ ^ ^ ^ ^ 乂 4將该圖案端的位置配置在 二，亞胺層之上面，而在肖特基連接領域3ia周邊之i6" m 陰極侧進打磨光並使之形成圖案。肖特基連接部以外的基 板為陰極電位，於陽極電極34與形成陰極電位之GaAs之交 叉部位，設置用以絕緣之聚醯亞胺層30。該交叉部位的面 積變為3 0 0/z m生右，為了使之具有更大的寄生電容必須 藉由將離間距離設定在6至7μ m左右之厚度以緩和寄生電、 容。採用聚醯亞胺層係基於其具有較低之導電率，以及可 形成一定厚度之性質。 為確保1 0V左右之耐壓及良好之肖特基特性，而將肖 特基連接領域3 1 a设於1 · 3x 1 〇 17c m ~輕度之η型蟲晶層2 3 上。另一方面，為降低導出電阻而將電阻電極2 8設置在藉 由台面#刻而露出之η+型磊晶層22之表面。此外，於η = 型蠢晶層22之下層形成高濃度之GaAs基板21，並設置電阻 電極28之AuGe/Ni/Au以做為背面電極，而成為可 板背面接出電極之機型。 …田暴 第1 0圖，顯示傳統之化合物半導體之肖特基屏障一 體之平面圖。 ^ 在晶片之大約中央位置之η型磊晶層23上形成肖特芙313891.ptc Page 10 Case No. 9Π17740 1284419 Revision 、5, invention description (2) Special connection field 3 1 a on the anode side 篦9 think people β p Π1 Sister 2 layer metal layer called Schottky electrode 3, the special electrode 31 may also be the bottom electrode of the green electro-electrode layer forming the anodic bonding pad, so that the solid enthalpy of the two are completely overlapped. In addition to the contact between the two layers of the metal layer and the resistive electrode, Λ ΤΤ ^ ^ BL becomes the bottom electrode of the third layer of the AU electric clock layer of the cathode bonding pad, and Pan Yang engages the tongue Tian Gan # L ^ % The same, the pattern of the two is completely rich. Based on the Schottky electrode 3 1, the spleen must be placed on the mountain ^ ^ ^ ^ ^ ^ ^ 乂 4 to position the pattern end on the second, imine layer, and in the Schottky connection area around the 3ia i6 " m The cathode side is polished and patterned. The substrate other than the Schottky junction is a cathode potential, and a polyimide layer 30 for insulating is provided at the intersection of the anode electrode 34 and the GaAs forming the cathode potential. The area of the intersection becomes 3 0 0 / z m, and in order to have a larger parasitic capacitance, it is necessary to set the thickness of the separation distance to a thickness of about 6 to 7 μm to alleviate the parasitic capacitance. The polyimine layer is based on its low electrical conductivity and the ability to form a certain thickness. In order to ensure the withstand voltage of about 10 V and good Schottky characteristics, the Schottky connection field 3 1 a is set on the 1 · 3 x 1 〇 17 c m ~ mild η type worm layer 2 3 . On the other hand, in order to lower the lead-out resistance, the resistive electrode 28 is placed on the surface of the n + -type epitaxial layer 22 which is exposed by the mesa #. Further, a GaAs substrate 21 having a high concentration is formed under the η = type stray layer 22, and AuGe/Ni/Au of the resistor electrode 28 is provided as a back electrode, and the electrode is formed on the back side of the board. ...Field Storm Figure 10 shows a plan view of a Schottky barrier of a conventional compound semiconductor. ^ Forming Schottf on the n-type epitaxial layer 23 at approximately the center of the wafer
313891.ptc 第11頁 1284419 案號 修正 五、發明說明（3) 連接領域3 1 a。該領域為直徑約丨〇 # m之圓形，於露出η型 蠢晶層2 3的肖特基接觸孔2 9上依序沈積形成第2層之金屬 層之Ti/Pt/Au。圍住圓形之肖特基連接領域313之外圍以 設置第1層之金屬層之電阻電極2 8。電阻電極2 8，係依序 沈積AuGe/Ni/Au而形成，而被設置在將近晶片之一半的領 域上。此外，為導出電極，而使第2層之金屬層與電阻電 極接觸，以形成底部電極。 陽極側以及陰極側之底部電極係為第3層之Au電鍍層 而设置。在陽極側方面’係設置於與肖特基連接領域3 1 a 部分進行接合時所需之最低限度之領域，而陰極側，則進 行圖案化使之形成可圍住圓形之肖特基連接領域3丨a之外 圍的形狀。此外’為降低形成南頻特性之因素的電减成 分，而必須安裝固定多數之接合線，因此，乃將約佔晶片 之半數面積之領域做為接合領域。 另外，設置Au電鍍層使之與底部電極重疊。在此係藉 由針腳式接合固定接合線，而導出電極。陽極接合墊部^ 4 0x 6 0# m2，而陰極接合墊部為240x 70# m2。藉由針腳式 接合進行連接時，可以一次之接合連接2條接合線，因此" 即使接合面積小’亦能夠降低形成高頻特性之參數之 成分，而有助於南頻特性之提昇。 $313891.ptc Page 11 1284419 Case No. Amendment V. Description of invention (3) Connection area 3 1 a. The field is a circle having a diameter of about 丨〇 #m, and Ti/Pt/Au of the metal layer of the second layer is sequentially deposited on the Schottky contact hole 209 exposing the n-type stray layer 23. The periphery of the circular Schottky connection field 313 is surrounded to provide a resistive electrode 28 of the metal layer of the first layer. The resistive electrode 28 is formed by sequentially depositing AuGe/Ni/Au, and is disposed on the vicinity of one half of the wafer. Further, in order to derive the electrode, the metal layer of the second layer is brought into contact with the resistance electrode to form a bottom electrode. The bottom electrode on the anode side and the cathode side is provided as a Au plating layer of the third layer. In terms of the anode side, it is disposed in the minimum area required for bonding to the 3 1 a portion of the Schottky connection field, and the cathode side is patterned to form a Schottky connection that can surround the circle. The shape of the periphery of the field 3丨a. Further, in order to reduce the electroconducting component which forms a factor of the south frequency, it is necessary to mount a fixed number of bonding wires, and therefore, a field occupying about half of the area of the wafer is used as a bonding field. In addition, an Au plating layer is provided to overlap the bottom electrode. Here, the electrodes are led by stitching to fix the bonding wires. The anodic bonding pad portion is 4 0x 6 0# m2, and the cathode bonding pad portion is 240x 70# m2. When the connection is made by the stitch type bonding, the two bonding wires can be joined at one time, so that even if the bonding area is small, the component which forms the parameter of the high frequency characteristic can be lowered, which contributes to the improvement of the south frequency characteristic. $
第1 1圖至第1 5圖係顯示傳統之肖特基屏障二極體之 造方法。 I 附Figures 11 through 15 show the fabrication of a conventional Schottky barrier diode. I attached
在第1 1圖中，係藉由台面蝕刻露出„+型磊晶層22並 著以第1層之金屬層以形成電阻電極2 8。 曰 WIn Fig. 1, the „+ type epitaxial layer 22 is exposed by mesa etching and the metal layer of the first layer is formed to form the resistance electrode 28. 8 曰 W
修正 1284419 五、發明說明（4) 換a之’係在n + G a A s基板2 1上層晶D 『曰層22( 5x 1〇18cm-3)後’再於其上/::左二二型蟲 之η型磊晶層23( 1·3χ ΙΟΑπτ，。之接、、力/ 35〇〇A左右 面，並進行光微影程序以選擇性地洞二，化膜25包覆全 上的阻劑f。之後，再以該阻劑層做==之電阻電極28 電阻電極28部分之氧化膜25,此;卜=罩以蚀刻預定之 之台面姓刻以露出n+型蟲晶層22。另進行η型蟲晶層23 接著，依序沈積並層疊第1層之金展 之3層。之後將阻劑層去除而將金屬芦=之AuGe/Nl/Au 極28部分。㈣再藉由合金化熱處理二預定之電阻電 成電阻電極28。 ^在n+型蟲晶们2上形 在第12圖中，形成肖特基接觸孔㈡。t面形成新的阻 =丄並進行光微影程彳以選擇性地洞開預定之肖特基連 接㈣31a部分。於㈣所露出之氧化膜25後去除 =成露出預U肖特基連接領域3la部之〇型蟲晶層此 肖特基接觸孔2 9。 第13圖顯示’形成用以絕緣之聚醯亞胺層3〇。數次於 全面敷層聚醯亞胺，以設置厚層之聚醯亞胺層3〇。於全面 形成全新之阻劑層，以進行選擇性洞開之光微影程序而留 下預定之聚醯亞胺層30部分。之後再藉由濕性蝕刻去除所 路出之聚醯亞胺。接著去除阻劑層並硬化聚醯亞胺層3 〇使 之具有6至7// m之厚度。 9 第1 4圖，係#刻露出於肖特基接觸孔2 9内的n型蠢晶 層23,而形成含有肖特基連接領域31a之肖特基電極I/。3Amendment 1284419 V. Inventive Note (4) Change a' to the n + G a A s substrate 2 1 upper layer crystal D 曰 layer 22 (5x 1 〇 18cm-3) after 'on the other /:: left two The n-type epitaxial layer 23 of the second type insect (1·3χ ΙΟΑπτ, the junction, the force / 35〇〇A left and right, and the light lithography procedure to selectively hole 2, the film 25 is covered Resistor f. Thereafter, the resistive layer is used to make the oxide film 25 of the resistive electrode 28 portion of the resistive electrode 28, and the mask is etched to etch the predetermined surface of the countertop to expose the n+ type crystal layer 22. Further, the η-type worm layer 23 is further deposited, and the third layer of the gold layer of the first layer is sequentially deposited and laminated, and then the resist layer is removed to remove the AuGe/Nl/Au pole portion of the metal ru ru = (4) The alloying heat treatment has two predetermined resistances to form the resistance electrode 28. ^In the n+ type insect crystal 2, the shape is shown in Fig. 12, and the Schottky contact hole (2) is formed. The t surface forms a new resistance = 丄 and performs photolithography Cheng Yu selectively opens the predetermined Schottky junction (4) part 31a. After (4) exposed oxide film 25 is removed = exposed to the pre-U Schottky connection field 3la portion of the worm-type layer of the Schottky contact hole 2 9. Figure 13 shows 'formation of the polyimine layer 3 用以 for insulation. Several times the full layer of polyimide, to form a thick layer of polyimine layer 3 〇. The layer of the agent is subjected to a selective aperture photolithography process to leave a portion of the predetermined polyimine layer 30. The removed polyimine is then removed by wet etching, followed by removal of the resist layer and hardening. The polyimide layer 3 has a thickness of 6 to 7 / / m. 9 Figure 14 shows the n-type stray layer 23 exposed in the Schottky contact hole 2 9 Schottky electrode I/.3 of the special connection field 31a
313891.ptc 第13頁 案號 91117740313891.ptc Page 13 Case No. 91117740
1284419 修正 五、發明說明（5) 以肖特基接觸孔2 9周圍的氧化膜2 5做為遮罩而蝕刻n 型蠢晶層23。如前H ’在接觸29形成後，直接在露 出η型磊晶層23表面之情況下形成聚醯亞胺層3〇。肖特基 連接，必須於乾淨的GaAs表面上形成，因此乃於形成肖特 基電極前蝕刻η型磊晶層23表面。此外，在動作層方面， 為確保其最加厚度之2 5 0 0Α而在精密控制溫度以及時間下 進行濕性蝕刻使3 5 0 0Α左右之厚度變為25〇〇人之厚度。 二依序沈積Ti/Pt/Au，以形成含有與型磊晶層 之、、土連接領域3 1 a，兼做陽極電極之底部電極之肖 特基電極3 1以及陽極電極3 5用之底部電極。 在第1 5圖中係形成成為陽極電極3 4以及陰極電極3 5 之Au電鍍層。 露出預定之陽極電極34以及陰極電極35部分之底部電 f % : : Γ劑層覆蓋其他部分後，進行電解電鍍。此時的 ^别層成為遮罩，而僅在露出底部電極的部分附著以Au電 二搞而=極電極34,陰極電極35。係於全面設置底部 —11 ，、’在去除阻劑後，進行由Ar電漿所致之離子銑削， 以切削未施以Au電鍍部分之底部電極，並將 極以及陰極電極34, 35之形狀。此時，Au電二 =切削’但因具有6“左右之厚度之故而不致產生“ 入令ΐί卢ΐ行背面磨光，依序沈積AuGe/Ni/Au，並施以 σ金化熱處理，以形成背面之電阻電極2 8。 化合物半導體肖特基屏障二極體，在完成前一步驟後1284419 MODIFICATION 5. DESCRIPTION OF THE INVENTION (5) The n-type stray layer 23 is etched by using the oxide film 25 around the Schottky contact hole 2 9 as a mask. After the formation of the contact 29 as in the front H', the polyimine layer 3 is formed directly on the surface of the n-type epitaxial layer 23. The Schottky junction must be formed on a clean GaAs surface so that the surface of the n-type epitaxial layer 23 is etched before the Schottky electrode is formed. Further, in terms of the action layer, wet etching was performed at a precisely controlled temperature and time to ensure a thickness of 2,500 Å, and the thickness of about 3,500 Å was changed to a thickness of 25 Å. Secondly, Ti/Pt/Au is sequentially deposited to form a bottom portion of the Schottky electrode 3 1 and the anode electrode 3 5 which are combined with the epitaxial layer and the soil connection region 31 1 a, which serves as the bottom electrode of the anode electrode. electrode. In Fig. 15, an Au plating layer which becomes the anode electrode 34 and the cathode electrode 35 is formed. The bottom portion of the predetermined anode electrode 34 and the cathode electrode 35 is exposed to electricity f % : : After the coating layer covers the other portions, electrolytic plating is performed. At this time, the layer is a mask, and only the portion where the bottom electrode is exposed is attached with the Au electrode and the electrode electrode 34 and the cathode electrode 35. The system is fully equipped with a bottom--11, 'after the removal of the resist, ion milling by Ar plasma is performed to cut the bottom electrode which is not applied to the Au plating portion, and the shape of the pole and cathode electrodes 34, 35 . At this time, Au electric 2 = cutting 'but because there is a thickness of about 6", it does not cause "replacement", and the AuGe/Ni/Au is deposited in sequence, and σ gold heat treatment is applied to A resistive electrode 28 on the back side is formed. Compound semiconductor Schottky barrier diode, after completing the previous step
第14頁 1284419 案號 91117740 修正 五、發明說明（6) 即移至進行組裝之後一步驟處理。切割晶圓狀之半導體晶 片，使之分割為個別之半導體晶片，將該半導體晶片固定 於框架（無圖例）後，利用接合線連接半導體晶片之陽極 與陰極接合墊以及預定之引線（無圖例）。接合線係使用 金細線，而藉由一般所知之針腳式接合進行連接。之後， 再進行移轉模塑以實施樹脂封裝。 [發明所欲解決之課題] 傳統之斑特基屏障二極體的基板構造，為了能夠對應 多用途之機種，而形成同時可自背面導出陰極電極的構 造，並形成在n+型GaAs基板上設置n+型磊晶層，且為確保 預定之特性，而於其上層設置1. 3x 1 0 17c m _3左右之η型蟲晶 層之構造。 肖特基電極基於確保預定之特性之需要，而露出η型 蠢晶層之清淨表面並沈積金屬，以形成肖特基連接。電阻 電極為降低導出電阻，而於其下層之η+型磊晶層形成電阻 連接。 在此，有關傳統之構造，具有以下之問題點。第1， 為形成電阻電極2 8必須形成台面並露出η+型磊晶層2 2。而 η型磊晶層23具有約350 0Α之厚度，為了露出其下層之η + 型磊晶層2 2，必須進行台面蝕刻。基板表面設有用以保護 基板之氧化膜2 5，台面蝕刻係於其表面設置光阻劑所致之 遮罩而進行蝕刻，但在氧化膜2 5表面與阻劑之密接性上卻 會產生偏差。在該狀況下進行濕性#刻時，將使#刻過度 朝橫向擴張，而蝕刻到必要之氧化膜25，而一旦露出GaAsPage 14 1284419 Case No. 91117740 Amendment V. Invention Description (6) Move to the first step after assembly. Cutting a wafer-shaped semiconductor wafer into individual semiconductor wafers, and fixing the semiconductor wafer to a frame (without legend), connecting the anode and cathode bonding pads of the semiconductor wafer and the predetermined leads (without legend) by bonding wires . The bonding wires are made of gold thin wires and are joined by generally known stitch bonding. Thereafter, transfer molding is performed to carry out resin encapsulation. [Problems to be Solved by the Invention] The substrate structure of the conventional Batter-type barrier diode is formed in a structure in which a cathode electrode can be derived from the back surface in order to be compatible with a multi-purpose type, and is formed on an n+ type GaAs substrate. The structure of the n+ type epitaxial layer, and the η type crystal layer of about 1. 3x 1 0 17c m _3 is disposed on the upper layer to ensure a predetermined characteristic. The Schottky electrode exposes the clean surface of the n-type stray layer and deposits metal to form a Schottky junction based on the need to ensure predetermined properties. The resistive electrode reduces the lead-out resistance and forms a resistive connection to the underlying n+-type epitaxial layer. Here, regarding the conventional construction, there are the following problems. First, in order to form the resistance electrode 28, it is necessary to form a mesa and expose the n+ type epitaxial layer 2 2 . The n-type epitaxial layer 23 has a thickness of about 350 Å, and in order to expose the underlying η + -type epitaxial layer 2 2, mesa etching must be performed. An oxide film 25 for protecting the substrate is provided on the surface of the substrate, and the mesa is etched by a mask formed by providing a photoresist on the surface thereof, but the adhesion between the surface of the oxide film 25 and the resist is deviated. . When the wetness is performed under this condition, the #etch is excessively expanded toward the lateral direction, and the necessary oxide film 25 is etched, and once the GaAs is exposed,
313891.pic 第15頁 1284419 --案號91117740 为年/」月/7日 偬m___ 五、發明說明（7) 將導致台面形狀之不安定。因此，連帶設於台面之開口部 之電阻電極2 8形成時之光阻劑，亦會在周端部之形狀上產 生鬆弛現象，導致光阻劑所致之電阻電極2 8之形狀劣化， 且GaAs被蝕刻至肖特基連接附近，而產生對特性帶來不良 影響之問題。313891.pic Page 15 1284419 -- Case No. 91117740 For the year / month / 7th 偬m___ V. Invention description (7) will cause the shape of the table to be unstable. Therefore, the photoresist which is formed when the resistive electrode 28 provided in the opening portion of the mesa is formed may also have a slack in the shape of the peripheral end portion, resulting in deterioration of the shape of the resistive electrode 28 due to the photoresist, and GaAs is etched to the vicinity of the Schottky connection, causing problems that adversely affect the characteristics.
第2 ’陽極電極3 4其大部分係設置在形成陰極電位之 GaAs上’在此會產生寄生電容增大的問題。由於交叉部分 的面積為1 3 0 0// in乏故，必須以較厚之層間絕緣膜降低寄 生$容。為了掩蓋台面使之形成較厚之層間絕緣膜，而必 須汉置6至7// m之聚醯亞胺層3 〇。為導出肖特基連接領域 3 1^之電極而在聚醯亞胺層3〇設置開口部，但基於厚聚醯 亞胺層3 0之钱刻’及聚醯亞胺層3 〇上之電極之段差部被覆 ^ ^ 而在该開口部設置斜面。但是，因聚醯亞胺層3 0 貝、之不均句’或是聚醯亞胺層3 0與阻劑之密接性不 臭；^ ^使Π亥斜面之角度產生3 0至4 5度之大幅偏差。因此， 考* ’動作領域之肖特基連接領與電阻 ?間離距離必須確保在左右。但是，由於 ‘大护二之？，距離係有助於串聯電阻，因此當間離距離 原因。守阻礙尚頻特性，並形成無法發展晶片之小型化的Most of the second 'anode electrode 3 4 is disposed on the GaAs which forms the cathode potential. Here, there is a problem that the parasitic capacitance increases. Since the area of the intersection portion is 1 30,000, it is necessary to reduce the escaping with a thick interlayer insulating film. In order to cover the mesa to form a thick interlayer insulating film, it is necessary to place a 6 to 7 m/m polyimine layer 3 〇. An opening is provided in the polyimide layer 3〇 for extracting the electrode of the Schottky connection field, but the electrode is based on the thick polyimine layer 30 and the polyimide layer 3 The step portion is covered by ^ ^ and a slope is provided in the opening portion. However, due to the polyimine layer 30 0, the inhomogeneous sentence 'or the polyimine layer 30 and the resist is not odorous; ^ ^ makes the angle of the 斜 slope of 30 to 45 degrees Great deviation. Therefore, the distance between the Schottky connection and the resistance of the test field must be ensured to the left and right. However, because of the ‘Big 2? The distance system contributes to the series resistance, so when the distance is off. Obstructing the frequency characteristics, and forming a miniaturization that cannot develop wafers
故 緣 因 ， 因肖特立基連接與電阻連接附近形成有斜面之 '脫基屏障二極體之動作領域附近無法保持層間絕 。、# m的厚度，而造成寄生電容增加，特性惡化之原Therefore, the reason why the Schottky connection and the resistance connection are formed near the vicinity of the action field of the 'de-base barrier diode' can not be maintained. , the thickness of #m, causing an increase in parasitic capacitance, the original deterioration of characteristics
第16頁 1284419 案號 91117740 力年"月/ 7曰 修正 五、發明說明（8) 第4，層間絕緣膜係採用聚醯亞胺，而形成配線以及 電極之導出之接合墊則採用Au電鍍，因此造成無法降低成 本之主因。 此外，傳統之製造方法具有以下問題。 第1，肖特基連接，係在最上層之η型磊晶層2 3進行肖 特基連接，但基於動作層之耐壓以及電阻之考量而為確保 最佳厚度之2 5 0 0Α，而由3 5 0 0Α左右之η型磊晶層23蝕刻 形成為2 5 0 0 Α。此時所進行之蝕刻為濕性蝕刻之故，在時 間，溫度以及蝕刻液内之晶圓的振幅，振動速度等控制上 極為困難，因此必須在指定之鮮度保持時間内使用蝕刻 液。因此，藉由該方法所製造之各晶圓將產生差異，並具 有動作領域之特性之重現性以及高頻特性之提昇極為不易 的問題。 第2，由於採用台面構造，導致必須進行耗費步驟程 序之台面蝕刻，同時因阻劑與氧化膜之間的密接性的偏差 而產生不良現象。此外，由於必須同時進行做為層間絕緣 膜之用之聚醯亞胺層形成步驟，及在聚醯亞胺層上設置電 極導出部之Au電鍍形成步驟，而造成製造流程複雜化，及 不具時間效率之問題。 由於化合物半導體其基板價格本身昂貴之故，為求價 格之合理化，必須縮小晶片規格以控制成本。亦即，晶片 規格之縮小勢所難免，而材料本身之成本亦需降低。同 時，更要求高頻特性之進一步之改善。此外，製造步驟之 簡化及效率化亦成為重要之課題。Page 16 1284419 Case No. 91117740 Year of the Force "Monthly / 7曰 Amendment 5, Invention Description (8) Fourth, the interlayer insulating film is made of polyimide, and the bonding pads forming the wiring and the electrode are Au plating. Therefore, it is the main cause of the inability to reduce costs. Further, the conventional manufacturing method has the following problems. First, the Schottky connection is performed by the Schottky connection of the n-type epitaxial layer 23 in the uppermost layer. However, based on the withstand voltage and resistance of the operation layer, it is necessary to ensure an optimum thickness of 2,500 Å. The n-type epitaxial layer 23 of about 3,500 Å is etched to form 2,500 Å. The etching performed at this time is wet etching, and it is extremely difficult to control the temperature, the amplitude of the wafer in the etching liquid, and the vibration speed in time, and therefore it is necessary to use the etching liquid for the specified freshness retention time. Therefore, the wafers produced by the method will have a difference, and the reproducibility of the characteristics of the field of action and the improvement of the high-frequency characteristics are extremely difficult. Secondly, due to the use of the mesa structure, it is necessary to carry out the mesa etching which is a step of the procedure, and at the same time, a defect occurs due to the deviation of the adhesion between the resist and the oxide film. In addition, since the polyimine layer forming step for the interlayer insulating film must be simultaneously performed, and the Au plating forming step of providing the electrode lead-out portion on the polyimide layer, the manufacturing process is complicated and time is not available. The problem of efficiency. Since compound semiconductors are expensive in terms of substrate prices, in order to rationalize prices, it is necessary to reduce wafer specifications to control costs. That is, the shrinking of the wafer specifications is inevitable, and the cost of the materials themselves needs to be reduced. At the same time, further improvements in high frequency characteristics are required. In addition, the simplification and efficiency of manufacturing steps have become an important issue.
313891.ptc 第17頁 1284419 案號 91117740 修正 五、發明說明（9) [用以解決課題之手段] 本發明，係鑑於上述課題而創作發明，其特徵係具 備··化合物半導體基板；設置於基板上之平坦之一導電型 磊晶層；穿透磊晶層而設置之一導電型高濃度離子注入領 域；與高濃度離子注入領域電阻連接之第1電極；以及與 磊晶層形成肖特基連接且作為電極導出部之第2電極，藉 由在基板表面之高濃度離子注入領域表面設置電阻電極， 可實現化合物半導體之平面型肖特基屏障二極體，並縮減 動作部分之面積，因此可藉由晶片規格之小型化及成本之 削減，或是寄生電容及電阻之降低，而有助於高頻特性之 提昇。 此外，本發明係提供一種可實現製造步驟之簡化以及 效率化，並提昇高頻特性之肖特基屏障二極體之製造方 法，其特徵係具備：於一導電型之磊晶層表面形成一導電 型之高濃度離子注入領域之步驟；形成與高濃度離子注入 領域表面電阻連接之第1電極之步驟；設置於磊晶層表面 形成肖特基連接之金屬層，使該金屬層延伸以形成作為電 極導出用之第2電極，同時藉由金屬層形成第1電極之導出 用電極之步驟。 參照第1圖至第8圖，以詳細說明本發明之實施形態。 本發明之肖特基屏障二極體，係由：化合物半導體基 板1 ;向濃度蠢晶層2，蠢晶層3，向濃度離子注入領域7， 第1電極8 ;以及第2電極1 1所構成。 第1圖，顯示動作領域部分之剖面圖。313891.ptc Page 17 1284419 Case No. 91117740 Revision 5 (Description of the Invention) The present invention has been made in view of the above problems, and is characterized in that it has a compound semiconductor substrate and is provided on a substrate. a flat conductive epitaxial layer; a conductive high-concentration ion implantation field penetrating the epitaxial layer; a first electrode electrically connected to the high-concentration ion implantation field; and a Schottky layer formed with the epitaxial layer The second electrode connected to the electrode lead-out portion is provided with a resistive electrode on the surface of the high-concentration ion implantation region on the surface of the substrate, thereby realizing a planar Schottky barrier diode of the compound semiconductor and reducing the area of the operation portion. The high-frequency characteristics can be improved by miniaturization of the chip specifications and cost reduction, or reduction of parasitic capacitance and resistance. In addition, the present invention provides a method for manufacturing a Schottky barrier diode which can realize simplification and efficiency of a manufacturing step and improve high frequency characteristics, and is characterized in that: a surface of an epitaxial layer of a conductivity type is formed a step of forming a high-concentration ion implantation field; forming a first electrode connected to a surface resistance of a high-concentration ion implantation field; forming a Schottky-connected metal layer on the surface of the epitaxial layer, and extending the metal layer to form As a second electrode for electrode extraction, a step of forming a first electrode lead electrode by a metal layer is also provided. Embodiments of the present invention will be described in detail with reference to Figs. 1 to 8. The Schottky barrier diode of the present invention is composed of: a compound semiconductor substrate 1; a concentration doping layer 2, a dope layer 3, a concentration ion implantation region 7, a first electrode 8; and a second electrode 1 1 Composition. Fig. 1 is a cross-sectional view showing a part of the action field.
313891.ptc 第18頁 1284419 案號 91117740 五、發明說明（ίο)313891.ptc Page 18 1284419 Case No. 91117740 V. Description of invention (ίο)
17 B 修正 化合物半導體基板1，為無摻雜之GaAs基板，係於其 上層疊5 0 0 0A之高濃度蠢晶層2 ( 5x 1〇18cm-3)及25〇u之 η型磊晶層3 ( 1 · 3x 1 0 17cm 3)。各層均未形成台面，而呈 現平坦之基板構造。 咼濃度離子注入領域7，係由電阻電極8之下方之1^型 爲晶層3表面分佈至η +蟲晶層2。係沿著圓形之肖特基連接 領域11 a外圍設置，與電阻電極呈大致重疊狀，而形成至 少包圍肖特基連接領域1 1 a的部分係由電阻電極8露出之設 置。肖特基連接領域1 la與高濃度離子注入領域7之間離= 離為1// m。換言之，係取代傳統之台面構造，直接採用維 持平面構造而於表面設置高濃度離子注入領域7之構造， 可不設置台面而實現電阻連接。 ^ *第1電極之電阻電極8，係接觸高濃度離子注入領域7 之第1層之金屬層。依序沈積AuGe/Ni/Au，並將肖特基 接附近圖案化使之形成貫穿為圓形之形狀。與鄰接之" 基連接領域1 1 a之間離距離為2// m。 、 第2電極，為肖特基連接領域！ la到達陽極接合墊工u 為止之陽極電極1卜係在覆蓋GaAs表面之氮化膜5上設 直徑為1 0// m之圓形肖特基接觸孔，且依序沈積τ = 之第2層之金屬層，並藉由與η型磊晶層3形成肖 u 以形成肖特基連接領域丨丨a。此外，使該金屬層延至 成電極之導出部之接合線固定領域以設置陽極接合墊y lib。換言之，與_磊晶層3形成肖特基連接之;2 屬層與形成該電極導出部之配線及陽極接合 夕:庶 ! i 1 b之金屬17 B The compound semiconductor substrate 1 is an undoped GaAs substrate on which a high concentration dope layer 2 (5 x 1 〇 18 cm -3 ) of 25 Å and a 〇 - type epitaxial layer of 25 〇 u are laminated thereon. 3 ( 1 · 3x 1 0 17cm 3). Each of the layers did not form a mesa, but a flat substrate structure. The erbium concentration ion implantation field 7 is formed by the surface of the crystal layer 3 distributed to the η + worm layer 2 by the type below the resistance electrode 8. The peripheral portion of the circular Schottky connection region 11a is disposed so as to be substantially overlapped with the resistive electrode, and the portion that surrounds the Schottky connection region 11a at least is exposed by the resistive electrode 8. The Schottky junction field 1 la is separated from the high concentration ion implantation field 7 by 1//m. In other words, instead of the conventional mesa structure, the structure in which the high-concentration ion implantation field 7 is provided on the surface by directly maintaining the planar structure can be realized, and the resistance connection can be realized without providing the mesa. ^ The resistive electrode 8 of the first electrode is in contact with the metal layer of the first layer of the high-concentration ion implantation field 7. AuGe/Ni/Au is sequentially deposited, and the Schottky is patterned nearby to form a circular shape. The distance from the adjacent " base connection field 1 1 a is 2//m. , the second electrode, for the Schottky connection field! The anode electrode 1 up to the anodic bonding pad is provided with a circular Schottky contact hole having a diameter of 10 / / m on the nitride film 5 covering the surface of the GaAs, and sequentially depositing τ = the second A metal layer of the layer is formed by forming a Schottky with the n-type epitaxial layer 3 to form a Schottky connection field 丨丨a. Further, the metal layer is extended to the bonding wire fixing region of the lead-out portion of the electrode to provide the anodic bonding pad y lib. In other words, it forms a Schottky connection with the _ epitaxial layer 3; the genus layer is bonded to the wiring and the anode which forms the electrode lead-out portion: 庶: i 1 b metal
313891.ptc313891.ptc
第19頁 1284419 荼號 911177, 五、發明說明（11) 層，係為同一沈積金屬層以 領域之η型…3為達到耐壓乍===用。形成動作 2 5 0 0Α，由於可省略過去1疋之特性而形成最佳之 蝕刻步驟，因此可形成呈 之用以控制動作層厚度之 化膜5而與電阻電極4 二極體。此外，係隔介氮 在陽極接合墊極電Λ之GaAs絕緣。 領域6(以下稱之為絕緣化：域;又置二：等而絕緣化之 基板為止的絕緣化領域6G A、^ 因到達無摻雜之GaAs π f u ^ ^ 負域6GaAs部分變為非陰極電位之故， Π:: 及氮化膜而直接將引線接合部固定 陰，電極15’同為第2層之Ti/pt/Au，係與電阻電極8 Ϊ : 5 ί设置成與陽極電極1 1相對之狀。帛2層之金屬層 延伸至陰極接合領域，而泌+认 苟曰Page 19 1284419 No. 911177, V. Description of the invention (11) The layer is the same deposited metal layer with the domain η type...3 for the withstand voltage ====. In the forming operation 2500, since the optimum etching step can be omitted by omitting the characteristics of the past one, the film 5 for controlling the thickness of the operating layer and the diode of the resistance electrode 4 can be formed. In addition, the GaAs insulation is electrically insulated from the anodic bonding pad. Field 6 (hereinafter referred to as Insulation: Domain; Place 2: Insulation in the field of insulation, 6G A, ^ due to reaching undoped GaAs π fu ^ ^ Negative domain 6 GaAs portion becomes non-cathode For the reason of the potential, Π:: and the nitride film directly fix the wire bonding portion, and the electrode 15' is the Ti/pt/Au of the second layer, and the resistance electrode 8 Ϊ : 5 ί is set to the anode electrode 1 1 relative shape. The metal layer of the 帛2 layer extends to the field of cathode bonding, and the secretion + 苟曰
Pfr & m ^ ^ ^ ^ 形成陰極接合墊1 5 b。電阻電極8 = ίΓΓ Ϊ子注入領域7以及n+型磊晶層2形成陰極 3之表面。° 。丢極接合墊1 5b，係直接固定於η型磊晶層 第2圖及第3圖’顯示本發明之化合物半導體之肖特基 ί Ϊ: 平面圖。第2圖為晶片圖案之概略圖，第调 ί動乍領域部分之放大圖。該圖為本發明之第1實施形 悲，係顯示肖特基連接為一個的情形。 依序沈積第2層之金屬層之Ti/pt/Au，以設置陽極電 Ϊ 1 ^極電極1 1 ’具有大致位於晶片巾央，並於η型磊 曰曰層3形成肖特基連接之肖特基連接領域iia。該領域為直Pfr & m ^ ^ ^ ^ forms a cathode bond pad 15b. Resistive electrode 8 = ΓΓ The rafter implantation field 7 and the n+ type epitaxial layer 2 form the surface of the cathode 3. ° . The drain pad 1 5b is directly fixed to the n-type epitaxial layer. Figs. 2 and 3' show the Schottky of the compound semiconductor of the present invention: a plan view. Figure 2 is a schematic diagram of the wafer pattern, and an enlarged view of the portion of the field. This figure is a first embodiment of the present invention, and shows a case where the Schottky connection is one. Ti/pt/Au of the metal layer of the second layer is sequentially deposited to provide an anode electrode. The 1^ electrode 1 1 ' has a substantially central portion of the wafer and forms a Schottky junction with the n-type layer 3. Schottky connects the field iia. The field is straight
313891.ptc 第20頁313891.ptc Page 20
1284419 _案號 91117740 五、發明說明（12) 徑約1 0// m之圓形，僅該圓形部分直接與GaAs接觸。另 外，延伸該金屬層以設置陽極接合墊1 1 b，並進行電極之 導出。 陽極接合塾1 1 b之下方設有注入B+離子之絕緣化領域 6。藉此，可省略絕緣膜之隔介而直接將陽極接合墊u b固 定於基板上，而降低接合時所產生之不良現象，並消除接 合墊部之寄生電容。 〃 虛線所示部分為電阻電極8。係包圍圓形之肖特基連 接領域1 la之外圍而與高濃度離子注入領域7 (無圖'例接 觸。電阻電極8為依序沈積Ti/Pt/Au而成之第1層之金屬 層。係被設置成大致與高濃度離子注入領域7重疊之狀， 另外，為導出電極而設置由第2層之沈積金屬 门並使之延伸以設置陰極接合塾…。陰極電： t ί f拉降低高頻特性之要因之電感成|，而必須固定 在Ξ i線，而將佔晶片半數之領域做為接合領域。 接a線，並=:3 f接合墊1 ib，15b上以針腳式接合固定 二陰極接合二;=;合墊1 lb部之面積為 致之連接，可以一-欠之技，積為18〇X 7〇//m。針腳接合所 接合面積較小@ a # 5連接2條接合線，因此即使是 成分：而有特低高頻特性之參數之電感 叉部Κ ΡΓ於所斜不線所陽極/極與形成陰極電位之GaAs之交 面積較之於傳统之丨=7員域，該部分之面積為1 〇 m2。該 傳統之m，可縮小至1/13左右，因此可1284419 _ Case No. 91117740 V. INSTRUCTIONS (12) A circle with a diameter of about 10/m, only the circular portion is in direct contact with GaAs. Further, the metal layer is extended to provide an anodic bonding pad 1 1 b, and the electrode is led out. Below the anodic junction 塾1 1 b is an insulating region 6 in which B+ ions are implanted. Thereby, the interlayer of the insulating film can be omitted and the anodic bonding pad u b can be directly fixed to the substrate, thereby reducing the occurrence of defects during bonding and eliminating the parasitic capacitance of the bonding pad portion.部分 The part shown by the dotted line is the resistance electrode 8. It surrounds the periphery of the circular Schottky connection field 1 la and is in contact with the high-concentration ion implantation field 7 (no picture is shown. The resistance electrode 8 is a metal layer of the first layer formed by sequentially depositing Ti/Pt/Au). It is arranged to substantially overlap with the high-concentration ion implantation field 7. In addition, a deposition metal gate of the second layer is provided for the derivation electrode and is extended to provide a cathode junction... Cathode: t ί f The inductance of the high-frequency characteristic is reduced to |, and must be fixed on the Ξ i line, and the area occupying half of the wafer is used as the bonding field. Connect a line, and =: 3 f bond pad 1 ib, 15b with pin type Bonding fixed two cathode joints; =; the area of the lb portion of the mat 1 is the connection, which can be one-off technique, the product is 18 〇 X 7 〇 / / m. The joint area of the stitch joint is small @ a # 5 Two bonding wires are connected, so even if it is a component: the inductance of the characteristic part of the low-frequency characteristic is the intersection of the anode/pole and the GaAs forming the cathode potential compared with the conventional one. = 7 member domain, the area of this part is 1 〇 m2. The traditional m can be reduced to about 1/13, so
第21頁 1284419 案號 91117740 修正 五、發明說明（13) 以較薄之氮化膜5代替層間絕緣膜之聚醯亞胺。 本發明之特徵在於：係藉由設置高濃度離子注入領域 7，並於GaAS表面設置肖特基連接領域1 la以及電阻電極 8 ’而貫現肖特基屏障二極體之平面構造。由於無須顧慮 台面形狀之不規則所致之接合偏差，因此可大幅降低肖特 基連接領域1 1 a與電阻電極8之間離距離。此外，在陽極電 極11下方，其大部分之領域設有絕緣化領域6，而形成陰 極電位之GaAs與陽極電極u之交叉部分面 2 左右，與傳統相較鈿小為1 / 1 3 。 ^ 之面積错由增加聚醯亞胺 之厗度（間離距離），即無須控制寄生電容， 薄之氮化膜5代替聚醯亞胺層，同時亦無須 17 乂 之斜面部分。 、号慮♦醯亞胺 藉此，具體而言，可祜4士 β 』使特基接合領域以；^ φ > 間離距離由7// m降低為2" m .L ^ ^ 及電阻電極之 7"m。此外，與向澧痒祕7 域7之間的間離距離為1 ，士一曲ώ辰度離子注入領 屏障之移動路徑，*致與電阻電極8具=入領域7為 先前相較之下其間離距離可降至1/7。由於其因此與 域1 1 a以及電阻電極8之間齙入士、月将基連接領 能縮小間離距離便能夠降 而科古 電 因此若 有助益。 鴻特性之提昇大 藉此，可助於晶片夕1… ^ β 之小型化，在晶片之葙故 為0.2 7x 0.31mm沃小之曰μ t ^ 〈規格上，過去 大小。在規格方面，基；^ ^ φ ^ ζ bx 〇 · 2 5mm乏 可處理之晶片大小之限制蓉 I性，及組合時 J 4因素，0.25m_係現狀下之最Page 21 1284419 Case No. 91117740 Amendment V. Description of Invention (13) The polyimide film of the interlayer insulating film is replaced by a thin nitride film 5. The present invention is characterized in that the planar structure of the Schottky barrier diode is realized by providing a high-concentration ion implantation region 7 and providing a Schottky connection region 1 la and a resistance electrode 8 ′ on the GaAS surface. Since there is no need to worry about the joint deviation caused by the irregularity of the shape of the mesa, the distance between the Schottky connection field 11a and the resistance electrode 8 can be greatly reduced. Further, under the anode electrode 11, most of the fields are provided with the insulating region 6, and the surface of the intersection of the GaAs and the anode electrode u forming the cathode potential is about 2, which is smaller than the conventional one by 1 / 13 . ^ The area error is increased by the density of the polyimide (distance), that is, without controlling the parasitic capacitance, the thin nitride film 5 replaces the polyimide layer, and the 17 斜 bevel portion is not required.号 醯 醯 醯 醯 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此 借此7"m of electrodes. In addition, the distance from the itch-to-skin 7 domain 7 is 1, and the path of the ion-injection barrier is shifted to the barrier, and the resistance electrode 8 has the input field 7 compared to the previous field. The distance between them can be reduced to 1/7. As a result, it can reduce the distance between the domain 1 1 a and the resistance electrode 8 and reduce the distance between the cells and the resistor electrode. The improvement of the characteristics of the singularity can help the miniaturization of the wafer eve 1...^β, which is 0.2 7x 0.31mm 小小小曰μ t ^ 〈 in the specification of the wafer, the past size. In terms of specifications, base; ^ ^ φ ^ ζ bx 〇 · 2 5mm lack of handleable wafer size limit I, and combination J 4 factor, 0.25m_ is the most
313891.ptc 第22頁 1284419 案號 91117740 五、發明說明（14) 修正 大限度，而在動作領域上， 程度，因此如後述一般，配 加。 由於可大幅縮小至1 / 1 0左右之 置動作領域之自由度將大幅增 此夕卜’ ^發明之陽極電極之特徵亦在於：其電極構造 係1僅延伸形成肖特基連接之金屬層之電極構造。由於 可以杈涛之T化膜代替聚醯亞胺，因此可在沈積金屬層實 現電極與配線，而有助於成本之降低。 第4圖，為本發明之第2實施形態，係顯示設置多數個 由陽極電極1 1所形成之肖特基連接領域i丨a。 在本發明之構造上，可設置多數之宵特基連接領域 1 la。例如’若依照第4圖之方式配置，即可使肖特基連接 領域1 1 a呈並列連接，而有助於降低電阻。 此外，縮小宵特基接觸孔之孔徑並配置數個時，相較 於整體之肖特基接觸孔面積相同且配置一個的情形，更能 夠降低肖特基接觸孔之中心與高濃度離子注入領域7之間 的間離距離，而使高濃度離子注入領域7之載體之捕集更 為有效。藉此，將使陰極電阻值變小，而呈并$ 高頻特性之優點。 〃 ^ ^ ^ 於第5圖至第8圖中詳細說明本發明 體之製m 〈为特基屏p羊一極 面到i ί:::二形成由預定之第1電極下的蟲晶層表 面到達间浪度絲日日層之一導電型之高濃度離子注入領域之313891.ptc Page 22 1284419 Case No. 91117740 V. INSTRUCTIONS (14) Amendment is limited, and in the field of action, the degree is therefore added as described later. Since the degree of freedom in the field of motion that can be greatly reduced to about 1 / 10 is greatly increased, the anode electrode of the invention is also characterized in that the electrode structure 1 only extends to form a metal layer of the Schottky connection. Electrode construction. Since the T-film of the Tao can be replaced by the polyimide, the electrode and the wiring can be realized in the deposited metal layer, which contributes to cost reduction. Fig. 4 is a view showing a second embodiment of the present invention, in which a plurality of Schottky connection fields i 丨 a formed by the anode electrode 1 1 are provided. In the construction of the present invention, a plurality of 宵 基 connection fields 1 la can be provided. For example, if configured in accordance with Fig. 4, the Schottky connection area 11a can be connected in parallel to help reduce the resistance. In addition, when the aperture of the 宵特基 contact hole is reduced and a plurality of holes are arranged, the center of the Schottky contact hole and the field of high-concentration ion implantation can be reduced in comparison with the case where the overall Schottky contact hole has the same area and one configuration. The distance between the 7 and the carrier of the high concentration ion implantation field 7 is more effective. Thereby, the cathode resistance value is made small, and the advantage of the high frequency characteristic is exhibited. 〃 ^ ^ ^ In detail in Fig. 5 to Fig. 8, the m of the body of the invention is formed by a special layer of the insect crystal layer under the predetermined first electrode. The surface reaches the field of high-concentration ion implantation in which one of the conductive layers of the daily wave layer
313891.ptc 肖特基屏障二極體’係由以下步驟所 =物”體基板上層疊一導電型之高濃度蠢晶層及： 第23頁 1284419 ~ -— 案號 91117740_年/ j 月 / 7 日__修丨下 ____ 五、發明說明（15) 步驟；形成與高濃度離子注入領域表面電阻連接之第1電 極之步驟；在被第1電極包圍外圍之磊晶層表面設置形成 肖特基連接之金屬層，延伸金屬層以形成作為電極導出部 之第2電極，同時利用金屬層形成第1電極之導出用電極之 步驟。 本發明之第1步驟，如第5圖所示，係在無掺雜之化合 物半導體基板1上層疊一導電型之高濃度磊晶層2及一導電 型之蠢晶層3，而形成由預定之第1電極8下的蠢晶層3表面 到達高濃度磊晶層2之一導電型之高濃度離子注入領域7。 本步驟，係形成本發明之特徵之步驟，係貫通形成預 定之電阻電極8之領域之下方的η型磊晶層3而形成到達η+' 型磊晶層2之高濃度離子注入領域7。 換吕之’係在無摻雜之GaAs基板1上，堆叠約入 左右之n+型蟲晶層2(5x l〇i«cm-3)，並在其上堆聶 之η型蟲晶層3( 13X 10ncnr3)。之後以氮化膜 面，並進行光微影程序以設置阻劑層並選擇性词I ^ 之絕緣化領域6上之阻劑層。接著，以該阻劑/门開預疋 離子注人Β.質而形成到達無摻雜GaA 二， 域6,以達到形成陰極電位之“As與陽極接合二二領 緣化。 文口势部11 b之絕 接著，進行光微影程序，以選擇性地 度離子注入領域7所形成之領域上的阻劑〗預疋之高▲ 阻劑層為遮罩，離子注入高濃度之n型雜^ 後，以該 iol8cm-轾度），貫通預定之電阻電極8下方之磊=層The 313891.ptc Schottky barrier diode is formed by laminating a conductive high-concentration stray layer on the substrate of the following steps: and page 23, 1284419 ~ - - Case No. 91117740_Year / J / 7th __修丨下 ____ V. Invention Description (15) Step; forming a first electrode connected to the surface resistance of the high-concentration ion implantation field; forming a surface on the surface of the epitaxial layer surrounded by the first electrode a step of forming a metal layer connected to the base, extending the metal layer to form a second electrode as the electrode lead-out portion, and forming the electrode for deriving the first electrode by the metal layer. The first step of the present invention is as shown in FIG. A high-concentration epitaxial layer 2 of a conductive type and a stray layer 3 of a conductive type are laminated on the undoped compound semiconductor substrate 1 to form a surface of the stray layer 3 under the predetermined first electrode 8 The concentration of the epitaxial layer 2 is one of the conductivity type high-concentration ion implantation fields. 7. This step is a step of forming the features of the present invention, which is formed by forming an n-type epitaxial layer 3 below the field of the predetermined resistive electrode 8. High concentration of eta+' type epitaxial layer 2 Sub-injection field 7. The change of Lu's is on the undoped GaAs substrate 1, stacking about the left and right n+ type worm layer 2 (5x l〇i«cm-3), and stacking it on the η Insecticide layer 3 (13X 10ncnr3). Then, the film surface is nitrided, and a photolithography process is performed to set a resist layer and a resist layer on the insulating field 6 of the selective word I ^. The agent/gate is preliminarily ion-injected to form an undoped GaA II, domain 6 to achieve the "potential and "anode bonding" of the cathode potential. The ventilating portion 11b is followed by a photolithography process to selectively implant the resistive agent in the field formed by the ion implantation field 7. The resist layer is a mask, and the ion implantation is high. After the n-type impurity ^, the iol 8cm-轾 degree), through the predetermined resistive electrode 8 below the Lei = layer
1284419 案號 91117740 修正 五、發明說明（16) 3，以形成到達n+型磊晶層2之高濃度離子注入領域7。 此時，離子注入，係以不同之條件分數次進行注入， 而高濃度離子注入領域7之雜質濃度則以儘可能往深度方 向均勻分佈之方式形成。 之後，去除阻劑層，並為用以退火而再度沈積氮化膜 5，而進行高濃度離子注入領域7以及絕緣化領域6之活性 化退火。 藉此，在預定之電阻電極8下，形成高濃度離子注入 領域7。於之後的步驟中，藉由在高濃度離子注入領域7之 表面，設置電阻電極8，而實現平面構造之宵特基屏障二 極體。藉此，可大幅降低肖特基連接領域，以及與電阻電 極進行相同作用之高濃度離子注入領域之間離距離，而形 成可降低串聯電阻且有助於高頻特性之提昇的肖特基屏障 二極體。 本發明之第2步驟，如第6圖所示，係在形成與高濃度 離子注入領域7表面電阻連接之第1電極8。 全面形成阻劑層，進行光微影程序，以選擇性地洞開 形成預定之電阻電極8之部分。去除由阻劑層所露出之氮 化膜5，依序真空沈積層疊第1層之金屬層之AuGe/Ni/A u之 三層。之後，藉由浮離去除阻劑層，而在預定之電阻電極 8之部分留下第1層之金屬層。接著藉由合金化熱處理在高 濃度離子注入領域7表面形成電阻電極8。 本發明之第3步驟，如第7圖以及第8圖所示，在第1電 極8中設置外圍受到圍覆並與磊晶層3表面形成肖特基連接1284419 Case No. 91117740 Amendment 5. Inventive Note (16) 3 to form a high concentration ion implantation field 7 that reaches the n+ type epitaxial layer 2. At this time, ion implantation is performed in a fractional order under different conditions, and the impurity concentration in the high-concentration ion implantation field 7 is formed so as to be evenly distributed in the depth direction as much as possible. Thereafter, the resist layer is removed, and the nitride film 5 is deposited again for annealing to perform activation annealing in the high-concentration ion implantation field 7 and the insulating field 6. Thereby, a high-concentration ion implantation field 7 is formed under the predetermined resistance electrode 8. In the subsequent step, the planar barrier yttrium barrier diode is realized by providing the resistive electrode 8 on the surface of the high-concentration ion implantation field 7. Thereby, the Schottky connection field and the distance between the high-density ion implantation fields having the same function as the resistance electrode can be greatly reduced, and a Schottky barrier which can reduce the series resistance and contribute to the improvement of the high-frequency characteristics can be formed. Diode. The second step of the present invention, as shown in Fig. 6, is to form the first electrode 8 which is connected to the surface resistance of the high-concentration ion implantation field 7. A resist layer is formed in its entirety, and a photolithography process is performed to selectively open a portion of the predetermined resistive electrode 8. The nitride film 5 exposed by the resist layer was removed, and three layers of AuGe/Ni/A u of the metal layer of the first layer were sequentially vacuum-deposited. Thereafter, the resist layer is removed by floating, and the metal layer of the first layer is left in a portion of the predetermined resistive electrode 8. Then, the resistance electrode 8 is formed on the surface of the high-concentration ion implantation field 7 by alloying heat treatment. In the third step of the present invention, as shown in Figs. 7 and 8, the periphery of the first electrode 8 is surrounded and a Schottky connection is formed with the surface of the epitaxial layer 3.
313891.ptc 第25頁 1284419 —--MMt 五、發明說明（π) 之金屬層，延 11，同時以金 本步驟為 再度於全面堆 之後於全面形 地洞開預定之 極電極1 5部分 層PR而形成露 之後’如 行光微影程序 1 5之圖案。全 AuGe/Ni/Au之 成陽極電極1 : 領域11 a之金』 時，形成與電 陰極電極1 5。 在傳統的 控制，而在進 度’以及姓刻 分困難之外， 刻液。但是， 制動作層厚度 肖特基連接， 優點。 91117740 電極導出部之第2電極 屬層形成苐1電極8之導出用電極工5 之步驟，首先，第7圖顯示， =50 0 0A左右的形成層間絕緣膜 成阻劑層PR，並進行光微影程序’ =^ 肖特基連接領域11a以及陽極接合墊nb，陰 。乾性蝕刻所露出之氮化膜 ^ 出η型蟲晶層3之接觸孔9 5並去除阻劑 第8圖所示，再度於全面設置阻劑層，並 面洞開陽極電極"以及曰陰 面性地依序真空沈積層疊第2層之金屬層 三層’並藉由浮離去除阻劑層pR。藉此曰 妥，其係將在η型蠢晶層3表面形成肖特基連接 I層延伸至陽極接合墊i i b而形成。在此同 阻電極8接觸，且被延伸至陰極接合墊i 5b 之後再對將背面進行背面磨光處理。 < 製造方法上，由於必須進行動作層之厚度 行該控制之GaAsl虫刻步驟中，除了時門 、 液内之晶圓之振幅’震盈速度等精密控制$ u必須在預定之鮮度保.夺日夺間内使 根據本發明之製造方法’由於可省略用以控 之蝕刻步驟，因此具有可形成重現性良好: 以及可製造特性安定之肖脫基屏障二極體之313891.ptc Page 25 1284419 —--MMt V. Inventive Note (π) The metal layer, extended 11, while the gold step is used to re-open the predetermined electrode in the full shape after the full stack. And after the formation of the dew, such as the pattern of the light lithography program 15. When the AuGe/Ni/Au is formed as the anode electrode 1: in the field of 11 a gold, the electrode electrode 15 is formed. In the traditional control, and in the progress 'and the surname is difficult to score, engraving. However, the thickness of the action layer is Schottky connection, which has the advantage. 91117740 The second electrode layer of the electrode lead-out portion forms a step 5 for deriving the electrode 1 of the 电极1 electrode 8. First, Fig. 7 shows that the interlayer insulating film is formed as a resist layer PR at about 500 0A, and light is emitted. The lithography program '=^ Schottky connection field 11a and the anodic bonding pad nb, yin. Dry etching exposes the nitride film to the contact hole 9 of the n-type crystal layer 3 and removes the resist as shown in Fig. 8. Once again, the resist layer is completely provided, and the anode electrode is opened and the surface is opened. The three layers of the metal layer of the second layer are sequentially vacuum deposited, and the resist layer pR is removed by floating. By this, it is formed by forming a Schottky junction I layer on the surface of the n-type doped layer 3 to extend to the anodic bonding pad i i b . Here, the back electrode 8 is contacted, and is extended to the cathode bonding pad i 5b, and then the back surface is subjected to back surface rubbing treatment. < In the manufacturing method, since the thickness of the action layer must be performed in the GaAs1 insect cutting step, the precision control $u of the amplitude of the wafer in the gate and the liquid in the liquid must be at the predetermined freshness. The manufacturing method according to the present invention is made to have a good reproducibility: and a Schottky barrier diode capable of producing stable characteristics can be omitted since the etching step for controlling can be omitted.
313891.ptc313891.ptc
第26頁 1284419 案號 91117740 Λ)年〇月,7日 修正 五、發明說明（18) 此外，陽極電極1 1以及陰極電極1 5，係藉由一般之浮 離法所形成之沈積金屬。此外，陽極電極1 1與電阻電極8 之層間絕緣膜為氮化膜5，而接合墊部亦可直接固定於基 板上，因此可省略聚醯亞胺層。藉此，由於可省略過去為 >在聚醯亞胺層上吸收聚醯亞胺之不均而設置之厚層配線 及接合墊之Au電鍍步驟。若能夠省略進行數次敷層之聚醯 亞胺之形成步驟以及Au電鍍步驟，便可簡化製造流程，而 有效地製造肖特基屏障二極體。 化合物半導體肖特基二極體在完成前步驟之後，便移 行至進行組裝的後步驟。切割晶圓狀之半導體晶片，以分 割為個別的半導體晶片’將該半導體晶片固定於框架（無 圖例）後，利用接合線連接半導體晶片之接合墊11 b，1 5b 及預定之引線（無圖例）。在接合線方面係使用金細線， 並藉由一般周知的針腳式接合進行連接。之後，再進行移 轉模塑以完成樹脂封裝。 [發明之效果] 依照本發明之構造，可獲得以下各種效果。 第1，藉由在GaAs表面，設置高濃度離子注入領域7， 並在GaAs表面設置肖特基連接領域1 1 a以及電阻電極8，即 可實現肖特基屏障二極體之平面構造。由於可控制台形之 不均所致之電阻電極形狀之不均以及特性之劣化，且無須 考慮接合之偏差，故可大幅降低肖特基連接領域11 a以及 電阻電極8之間離距離。由於肖特基連接領域1 1 a以及電阻 電極8之間離距離有助於串聯電阻之故，因此若能縮小間Page 26 1284419 Case No. 91117740 Λ) Year of the month, 7th Revision 5. Invention Description (18) In addition, the anode electrode 1 1 and the cathode electrode 15 are deposited metals formed by a general floating method. Further, the interlayer insulating film of the anode electrode 11 and the resistor electrode 8 is the nitride film 5, and the bonding pad portion can be directly fixed to the substrate, so that the polyimide layer can be omitted. Thereby, the Au plating step of the thick wiring and the bonding pad which were provided in the past for the absorption of the polyimine on the polyimide layer can be omitted. If the polyimine forming step and the Au plating step which are performed several times can be omitted, the manufacturing process can be simplified, and the Schottky barrier diode can be efficiently manufactured. The compound semiconductor Schottky diode is moved to the post-assembly step after completion of the pre-step. Cutting a wafer-shaped semiconductor wafer to be divided into individual semiconductor wafers. After the semiconductor wafer is fixed to a frame (not shown), the bonding pads 11b, 15b and predetermined leads of the semiconductor wafer are connected by bonding wires (no legend) ). Gold thin wires are used in the bonding wires, and are joined by generally known stitch bonding. Thereafter, transfer molding is performed to complete the resin encapsulation. [Effects of the Invention] According to the configuration of the present invention, the following various effects can be obtained. First, by providing a high-concentration ion implantation field 7 on the surface of the GaAs, and providing a Schottky connection field 11a and a resistance electrode 8 on the surface of the GaAs, the planar structure of the Schottky barrier diode can be realized. Since the shape of the resistor electrode due to the unevenness of the console shape is degraded and the characteristics are deteriorated, and the variation of the bonding is not required, the distance between the Schottky connection field 11a and the resistance electrode 8 can be greatly reduced. Since the distance between the Schottky connection field 1 1 a and the resistance electrode 8 contributes to the series resistance, if the series resistance is reduced,
31389].pic 第27頁 1284419 案號91117740 Θ年月，;7日 修正_ 五、發明說明（19) 離距離，便可進一步降低電阻。 第2，形成陰極電位之GaAs與陽極電極1 1之交叉部分 面積為1 0 0 // m 2左右，而能夠大幅降低寄生電容。基於此 此，而在陽極電極1 1下之大部分領域設置絕緣化領域6， 因此產生寄生電容之交叉部面積，與過去相較，僅肖特基 連接部分便可縮小為1 / 1 3。此外，因陽極接合墊1 1 b可直 接固定於GaAs之故，該部分將不會產生寄生電容，而得以 使整體之寄生電容大幅降低。傳統上，為控制寄生電容而 採用導電率較低之聚醯亞胺以設置厚層之層間絕緣膜，但 亦可以較薄之氮化膜代替。與聚醯亞胺相比，氮化膜之導 電率較高，但是若依照本發明之構造，則即使使用5 0 0 0 A 程度之氮化膜，較之於先前，依然可降低寄生電容。 第3，由於不使用厚層之聚醯亞胺，因此無須考慮形 成動作領域之聚醯亞胺開口部之斜面部分的距離，或是斜 面角度之不均。 基於上述說明，肖特基連接領域以及電阻電極之間離 距離，只需單純考慮其耐壓性以及遮罩重疊之精密度即 可。具體而言，肖特基連接領域以及電阻電極之間離距離 可由7// m降低至2// m。此外，與高濃度注入領域7之間的 間離距離為1 // m，在該情形下，高濃度離子注入領域7為 載體之移動路徑，具有與電阻電極8大致相同之效果，因 此相較於過去，可將間離距離降低到1 / 7。而藉由電阻之 大幅降低，寄生電容之大幅降低以及寄生電容不均之降 低，可對高頻特性之提昇產生莫大之助益。31389].pic Page 27 1284419 Case No. 91117740 Lunar New Year, 7th Revision _ V. Invention Description (19) The distance can be further reduced. Second, the area where the intersection of the GaAs and the anode electrode 1 1 forming the cathode potential has an area of about 1.00 m 2 , and the parasitic capacitance can be greatly reduced. Based on this, the insulating region 6 is provided in most of the area under the anode electrode 1, so that the intersection area of the parasitic capacitance is generated, and only the Schottky connection portion can be reduced to 1 / 13 as compared with the past. In addition, since the anodic bonding pad 1 1 b can be directly fixed to GaAs, this portion will not generate parasitic capacitance, and the overall parasitic capacitance can be greatly reduced. Conventionally, a polyimide having a low conductivity has been used for controlling the parasitic capacitance to provide a thick interlayer insulating film, but it may be replaced by a thin nitride film. The conductivity of the nitride film is higher than that of the polyimide. However, according to the configuration of the present invention, even if a nitride film of about 50,000 A is used, the parasitic capacitance can be reduced as compared with the prior art. Third, since a thick layer of polyimide is not used, it is not necessary to consider the distance of the bevel portion of the opening portion of the polyimide which forms the action field, or the unevenness of the slope angle. Based on the above description, the distance between the Schottky connection field and the resistance electrode can be simply considered in terms of the withstand voltage and the precision of the overlap of the mask. Specifically, the Schottky connection field and the distance between the resistance electrodes can be reduced from 7//m to 2//m. Further, the distance from the high-concentration injection field 7 is 1 // m. In this case, the high-concentration ion implantation field 7 is a moving path of the carrier, and has substantially the same effect as the resistance electrode 8, and thus In the past, the separation distance was reduced to 1 / 7. With the large reduction in resistance, the large reduction in parasitic capacitance and the reduction in parasitic capacitance unevenness can greatly contribute to the improvement of high-frequency characteristics.
313891.ptc 第28頁 1284419 案號 91117740 修正 五、發明說明（20) 第4，有利於晶片之小型化，晶片規格可由過去之 0 . 2 7x 0 . 3 1 m m之大小縮小為0 . 2 5x 0 . 2 5 m m之大小。在規 格上，基於配置接合墊之必要性，及組裝時可處理之晶片 大小之限制，而以0 . 2 5mm角為現狀之界限，而在動作領域 方面由於可大幅縮小至1 / 1 0之程度，故可大幅增加配置動 作領域之自由度。 第5，可藉由設置數個肖特基連接領域，進一步降低 電阻。縮小肖特基連接部之接觸孔徑並設置多數個，相較 於設置一個整體之肖特基接觸孔面積一致的肖特基連接領 域，更能降低電阻，並能有效地捕集高濃度離子注入領域 的載體，因此具有可進一步提昇高頻特性的優點。 第6，由於不必使用聚醯亞胺層，或金屬電鍍，而能 夠利用與形成肖特基連接之金屬相同之金屬層來實現陽極 電極，因此除了可降低材料費外，更可縮小晶片，並大幅 削減成本。 此外，根據本發明之製造方法，可獲得以下之效果。 第1，可形成安定之肖特基連接，因此可控制形成高 頻電路之重大課題的特性的不均。η型磊晶層形成最適於 動作層之2 5 0 0 A，而不再需要過去一般精密的G a A s姓刻控 制。換言之，可提昇良率，並製造具良好重現性，及安定 特性之肖特基屏障二極體。 第2，上述之肖特基屏障二極體之製造，可有效地實 現製造步驟的簡化。具體而言，為台面蝕刻步驟，肖特基 連接形成前之η型磊晶層蝕刻步驟，聚醯亞胺層形成步313891.ptc Page 28 1284419 Case No. 91117740 Revision 5, Invention Description (20) Fourth, it is conducive to the miniaturization of the wafer, the wafer size can be reduced from the previous 0. 2 7x 0 . 3 1 mm to 0. 2 5x 0 . 2 5 mm in size. In terms of specifications, based on the necessity of arranging the bonding pads and the limitation of the size of the wafers that can be handled during assembly, the angle of 0. 25 mm is the current limit, and the field of motion can be greatly reduced to 1 / 10 To the extent that the degree of freedom in the field of configuration actions can be greatly increased. Fifth, the resistance can be further reduced by setting several Schottky connection fields. Reducing the contact aperture of the Schottky connection and setting a plurality of them can reduce the resistance and effectively capture high-concentration ion implantation compared to the Schottky connection field in which the overall Schottky contact hole area is provided. The carrier of the field therefore has the advantage of further enhancing the high frequency characteristics. Sixth, since it is not necessary to use a polyimide layer or metal plating, the anode electrode can be realized by the same metal layer as the metal forming the Schottky connection, so that the wafer can be reduced in addition to the material cost, and Significant cost reductions. Further, according to the production method of the present invention, the following effects can be obtained. First, a stable Schottky connection can be formed, so that it is possible to control the variation in characteristics of a major problem that forms a high-frequency circuit. The n-type epitaxial layer forms the most suitable 2 5 0 A for the action layer, and the conventionally precise G a A s surname control is no longer needed. In other words, the yield can be improved and a Schottky barrier diode with good reproducibility and stability can be produced. Second, the manufacture of the Schottky barrier diode described above can effectively simplify the manufacturing steps. Specifically, in the mesa etching step, the Schottky junction is formed before the formation of the n-type epitaxial layer etching step, and the polyimide layer forming step
313891.ptc 第29頁 1284419 案號 91117740 年/2月，7曰 修正 五、發明說明（21) 驟，及Au電鍍步驟等。為了將聚醯亞胺層做成6至7// m的 厚度，而反覆進行數次之敷層。數次敷層聚醯亞胺層需耗 費相當之時間，並使製造流程複雜化。此外，若省略聚醯 亞胺層，則亦可省略Au電鍍層所致之電極。過去，為防止 銲錫實裝時所產生之熱度，及引線接合時因壓力所致之電 極的切斷與變形，而必須確保電極強度，並藉由厚層之Au 電鍍層形成陽極電極及陰極電極。但是既然可省略聚醯亞 胺層，便無須考慮其所致之影響。換言之，無須金屬電 鍍，而僅以T i /P t / Au之沈積金屬即可形成肖特基連接領 域，陽極電極以及陰極電極，並提昇可靠性。此外，由於 可消除過去導致良率降低之上述要因，故可提昇良率。 換言之，本發明係一種可大幅降低寄生電容，並降低 電阻，同時又可使高頻特性大幅提昇之商特基屏障二極 體，具有可提供實現製造步驟之簡單化與效率化之製造方 法之優點。313891.ptc Page 29 1284419 Case No. 91117740 / 2, 7曰 Amendment 5, invention description (21), and Au plating steps, etc. In order to make the polyimide layer a thickness of 6 to 7 / / m, the coating is repeated several times. It takes a considerable amount of time to apply the polyimine layer several times and complicates the manufacturing process. Further, if the polyimide layer is omitted, the electrode due to the Au plating layer may be omitted. In the past, in order to prevent the heat generated during solder mounting and the cutting and deformation of the electrode due to pressure during wire bonding, it is necessary to ensure the strength of the electrode, and the anode electrode and the cathode electrode are formed by a thick Au plating layer. . However, since the polyimide layer can be omitted, it is not necessary to consider the effect. In other words, metal plating is not required, and only the deposited metal of T i /P t / Au can form a Schottky junction, an anode electrode and a cathode electrode, and improve reliability. In addition, the yield can be improved by eliminating the above-mentioned factors that cause a decrease in yield in the past. In other words, the present invention is a stellite barrier diode which can greatly reduce parasitic capacitance and reduce electrical resistance while greatly improving high-frequency characteristics, and has a manufacturing method capable of providing simplification and efficiency in manufacturing steps. advantage.
313891.ptc 第30頁 1284419 案號 91117740 修正 圖式簡單說明 【圖面之簡單說明】 第1圖為說明本發明之半導體裝置的剖面圖。 第2圖為說明本發明之半導體裝置的上面圖。 第3圖為說明本發明之半導體裝置的上面圖。 第4圖為說明本發明之半導體裝置的上面圖。 第5圖為說明本發明之半導體裝置之製造方法的剖 面〇 第6圖為說明本發明之半導體裝置之製造方法的剖面 圖。 第7圖為說明本發明之半導體裝置之製造方法的剖面 圖。 第8圖為說明本發明之半導體裝置之製造方法的剖面 圖。 第9圖為說明傳統之半導體裝置的剖面圖。 第1 0圖為說明傳統之半導體裝置的上面圖。 第1 1圖為說明傳統之半導體裝置之製造方法的剖面 圖。 第1 2圖為說明傳統之半導體裝置之製造方法的剖面 圖。 第1 3圖為說明傳統之半導體裝置之製造方法的剖面 圖。 第1 4圖為說明傳統之半導體裝置之製造方法的剖面 圖。 第1 5圖為說明傳統之半導體裝置之製造方法的剖面313891.ptc Page 30 1284419 Case No. 91117740 Correction of the drawing [Simplified description of the drawing] Fig. 1 is a cross-sectional view showing the semiconductor device of the present invention. Fig. 2 is a top view showing the semiconductor device of the present invention. Fig. 3 is a top view showing the semiconductor device of the present invention. Fig. 4 is a top view showing the semiconductor device of the present invention. Fig. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device of the present invention. Fig. 6 is a cross-sectional view showing a method of manufacturing the semiconductor device of the present invention. Fig. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device of the present invention. Figure 8 is a cross-sectional view showing a method of manufacturing the semiconductor device of the present invention. Figure 9 is a cross-sectional view showing a conventional semiconductor device. Fig. 10 is a top view showing a conventional semiconductor device. Fig. 1 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device. Fig. 12 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device. Fig. 13 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device. Fig. 14 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device. Figure 15 is a cross section illustrating a method of fabricating a conventional semiconductor device
313891.ptc 第31頁 1284419 案號 91Π7740 年月，7曰 修正 圖式簡單說明 圖。 [元件符號之說明] 1 無摻雜GaAs 2卜 22 n+GaAs 3> 23 nGa As 5 氮化膜 6 絕緣化領域 7 高濃度離子注入領域 8> 28 電阻電極 9^ 29 肖脫基接觸孔 11a、 31a 肖脫基接合領域 η、3 4 陽極電極 lib 陽極接合墊 15' 35 陰極電極 15b 陰極接合墊 25 氧化膜 20、 30 聚醯亞胺層 31 肖脫基電極 IHH1 313891.ptc 第32頁313891.ptc Page 31 1284419 Case No. 91Π7740, 7曰 Correction Schematic description. [Description of Component Symbols] 1 Undoped GaAs 2b 22 n+GaAs 3> 23 nGa As 5 Nitride Film 6 Insulation Field 7 High Concentration Ion Implantation Field 8> 28 Resistive Electrode 9^ 29 Schottky Contact Hole 11a 31a Schottky bonding field η, 3 4 anode electrode lib anodic bonding pad 15' 35 cathode electrode 15b cathode bonding pad 25 oxide film 20, 30 polyimine layer 31 Schottky electrode IHH1 313891.ptc page 32
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| CN102456570A (en) * | 2010-10-22 | 2012-05-16 | 上海芯石微电子有限公司 | Manufacturing method for schottky diode |
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