KR100612189B1 - Schottky barrier diode and method of fabricating the same - Google Patents

Abstract

Conventionally, since there are mesa etching, a thick polyimide layer, and the like, miniaturization of the chip is not realized, and there is a distance between electrodes and the characteristics cannot be improved. Moreover, the etching control of the Schottky junction part was difficult by the manufacturing method.

By forming the n ⁺ type ion implantation region on the substrate surface, it is not necessary to form the mesa and the polyimide layer, and the planar Schottky barrier diode of the compound semiconductor can be realized. Since the distance between electrodes can be shortened, chip reduction is realized and high frequency characteristics are also improved. In addition, since GaAs is not etched when the Schottky junction region is formed, a Schottky barrier diode with good reproducibility can be manufactured.

Schottky barrier diode, compound semiconductor, high frequency characteristics, schottky junction

Description

Schottky Barrier Diodes and Method for Manufacturing the Same {SCHOTTKY BARRIER DIODE AND METHOD OF FABRICATING THE SAME}

1 is a cross-sectional view illustrating a semiconductor device of the present invention.

2 is a top view for explaining the semiconductor device of the present invention.

3 is a top view for explaining the semiconductor device of the present invention.

4 is a top view for explaining the semiconductor device of the present invention.

5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device of the present invention.

6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device of the present invention.

7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device of the present invention.

8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device of the present invention.

9 is a cross-sectional view illustrating a conventional semiconductor device.

10 is a top view for explaining the conventional semiconductor device.

11 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device.

12 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device.

13 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device.

14 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device.

15 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device.

<Explanation of symbols for the main parts of the drawings>

1: undoped GaAs

2: n ⁺ type GaAs

3: n-type GaAs

5: nitride film

6: insulation area

7: high concentration ion implantation zone

8: ohmic electrode

11: anode electrode

15: cathode electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky barrier diode of a compound semiconductor employed in a high frequency circuit and a method for manufacturing the same. Particularly, the Schottky barrier diode of a compound semiconductor and a method of manufacturing the same have a planar structure. It is about.

With the expansion of the global mobile phone market and the demand for digital satellite broadcasting receivers and the like, the demand for high frequency devices is increasing rapidly. Since the device handles high frequency, a field effect transistor using gallium arsenide (GaAs) is often used. Thus, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated, or a local oscillation FET Development is underway.

In addition, demand for GaAs Schottky barrier diodes is increasing rapidly for base stations.

9 is a cross-sectional view of an operating region portion of a conventional Schottky barrier diode.

on the n ⁺ type GaAs substrate (21), an n ⁺ epitaxial layer ^{(22) (5 × 10 18} ㎝ -3) the degree of stacking, and the operation layer is a n-type epitaxial layer 23 is again 6㎛ (1.3 × 10 ¹⁷ cm ^-3 ), for example, about 3500 kPa is deposited.

The metal layer of the 1st layer used as the ohmic electrode 28 is AuGe / Ni / Au which ohmic-joins to the n ⁺ type epitaxial layer 22. FIG. The metal layer of a 2nd layer is Ti / Pt / Au, and there are two types of patterns of this 2nd layer metal layer, an anode side and a cathode side. On the anode side, a Schottky junction is formed with the n-type epitaxial layer 23. The metal layer of the 2nd layer on the anode side which has this Schottky junction region 31a is called Schottky electrode 31 below. The Schottky electrode 31 also serves as a base electrode of the Au plating layer of the third layer forming the anode bonding pad, and the patterns of both are completely overlapped. The metal layer of the second layer on the cathode side is in contact with the ohmic electrode and serves as a base electrode of the Au plating layer of the third layer forming the cathode bonding pads, and likewise on the anode side, both patterns completely overlap. Since the Schottky electrode 31 needs to arrange the position of the end of the pattern on the upper surface of the polyimide layer, it is patterned by overlapping the 16 µm cathode side around the Schottky junction region 31a. Substrates other than the Schottky junction are at the cathode potential, and at the portion where the anode electrode 34 and the GaAs serving as the cathode potential intersect, the polyimide layer 30 is formed for insulation. Since the area of this intersection is about 1300 µm ² and has a large parasitic capacitance, it is necessary to reduce the parasitic capacitance by setting the thickness to about 6 to 7 µm as the separation distance. Polyimide is employed as an interlayer insulating layer because of its low dielectric constant and thick formability.

The Schottky junction region 31a is formed on the n-type epitaxial layer 23 of about 1.3 x 10 ¹⁷ cm ^{-3 in} order to secure a breakdown voltage of about 10V and good Schottky characteristics. On the other hand, the ohmic electrode 28 is formed on the surface of the n ⁺ type epitaxial layer 22 exposed by mesa etching in order to reduce the extraction resistance. In addition, the lower layer of the n ⁺ type epitaxial layer 22 is a GaAs substrate 21 having a high concentration, and AuGe / Ni / Au, which is an ohmic electrode 28, is formed as a back electrode, and is taken out from the back surface of the substrate. It is also possible to respond.

10 is a plan view of a Schottky barrier diode of a conventional compound semiconductor.

The Schottky junction region 31a is formed on the n-type epitaxial layer 23 near the center of the chip. This region is formed by sequentially depositing Ti / Pt / Au, which is the second metal layer, in the Schottky contact hole 29 having a circular shape having a diameter of about 10 μm and exposing the n-type epitaxial layer 23. The ohmic electrode 28 which is the metal layer of a 1st layer is formed surrounding the outer periphery of the circular Schottky junction area | region 31a. The ohmic electrode 28 is formed by sequentially depositing AuGe / Ni / Au and occupies an area close to half of the chip. In addition, in order to take out an electrode, the metal layer of a 2nd layer is contacted with the ohmic electrode 28, and it is set as a base electrode.

The base electrode on the anode side and the cathode side is formed for the Au plating layer serving as the third layer. The anode side is formed in the portion of the Schottky junction region 31a and the minimum region necessary for bonding, and the cathode side is patterned in a shape surrounding the outer periphery of the circular Schottky junction region 31a. In addition, in order to reduce the inductor component, which is a factor of high frequency characteristics, it is necessary to fix a lot of bonding wires, so that a region occupying about half of the chip is a bonding region.

In addition, an Au plating layer is formed to overlap with the base electrode. Here, the bonding wire is fixed by the stitch bond, and the electrode is taken out. The anode bonding pad portion is 40 × 60 μm ² , and the cathode bonding pad portion is 240 × 70 μm ² . In connection by stitch bonding, since two bonding wires can be connected by one bonding, even if the bonding area is small, the inductor component which is a parameter of a high frequency characteristic can be made small, and it contributes to the improvement of a high frequency characteristic.

11 to 15 show a conventional Schottky barrier diode manufacturing method.

In FIG. 11, the n ⁺ type epitaxial layer 22 is exposed by mesa etching, and the ohmic electrode 28 is formed by attaching the first metal layer.

That is, n ⁺ type GaAs substrate in the n ⁺ epitaxial layer ^{(22) (5 × 10 18} ㎝ -3) , and the degree of deposition, n-type epitaxial layer 23 thereon 6㎛ (1.3 × 10 (21) ¹⁷ cm ^-3 ) is deposited about 3500 mm ³ . Thereafter, the entire surface is covered with an oxide film 25, and a photolithography process for selectively windowing a resist layer on a predetermined ohmic electrode 28 is performed. Thereafter, the resist layer is used as a mask to etch the oxide film 25 of the portion of the predetermined ohmic electrode 28, and the mesa of the n-type epitaxial layer 23 so that the n ⁺ -type epitaxial layer 22 is exposed. Etching is performed.

Thereafter, three layers of AuGe / Ni / Au, which are metal layers of the first layer, are sequentially deposited by vacuum deposition. Thereafter, the resist layer is removed, leaving a metal layer on the predetermined ohmic electrode 28 portion. Subsequently, the ohmic electrode 28 is formed in the n ⁺ type epitaxial layer 22 by alloying heat treatment.

In FIG. 12, a schottky contact hole 29 is formed. A new resist layer is formed on the entire surface, and a photolithography process is performed to selectively window a predetermined Schottky junction region 31a. After the exposed oxide film 25 is etched, the resist is removed to form a Schottky contact hole 29 in which the n-type epitaxial layer 23 in the predetermined Schottky junction region 31a portion is exposed.

In FIG. 13, a polyimide layer 30 for insulation is formed. The polyimide is coated on the entire surface several times to form a thick polyimide layer 30. A new resist layer is formed on the entire surface, and a photolithography process is performed to selectively window the portion of the predetermined polyimide layer 30 to remain. Thereafter, the exposed polyimide is removed by wet etching. Thereafter, the resist layer is removed to cure the polyimide layer 30 to a thickness of 6 to 7 µm.

In Fig. 14, the n-type epitaxial layer 23 exposed in the Schottky contact hole 29 is etched to form a Schottky electrode 31 having a Schottky junction region 31a.

The n-type epitaxial layer 23 is etched using the oxide film 25 around the Schottky contact hole 29 as a mask. As described above, after the contact hole 29 is formed, the polyimide layer 30 is formed with the surface of the n-type epitaxial layer 23 exposed. It is essential that the Schottky junction is formed on a clean GaAs surface, and therefore the surface of the n-type epitaxial layer 23 is etched before the Schottky electrode is formed. In addition, in order to secure an optimum thickness of 2500 kV as the operating layer, the temperature and time are precisely controlled and wet etched to be 2500 kPa from a thickness of about 3500 kV.

After that, Ti / Pt / Au is vacuum deposited sequentially, and the Schottky electrode 31 having the Schottky junction region 31a with the n ⁺ type epitaxial layer 22 serves as the base electrode of the anode electrode, and The base electrode for the cathode electrode 35 is formed.

In FIG. 15, an Au plating layer serving as the anode electrode 34 and the cathode electrode 35 is formed.

The base electrode of the predetermined anode electrode 34 and the cathode electrode 35 portion is exposed and covered with another resist layer, followed by electrolytic plating. At that time, the resist layer is used as a mask, and Au plating is attached only to a portion where the base electrode is exposed, so that the anode electrode 34 and the cathode electrode 35 are formed. The base electrode is formed on the entire surface, and after removal of the resist, ion milling by Ar plasma is performed to cut the base electrode in a portion where Au plating is not performed and pattern the shape of the anode and cathode electrodes 34 and 35. In that case, although Au plating part is also somewhat cut | disconnected, if it is about 6 micrometers thick, there is no problem.

Further, the backside is back-laminated, AuGe / Ni / Au is sequentially deposited, and an alloying heat treatment is performed to form the ohmic electrode 28 on the backside.

When all the steps are completed, the compound semiconductor Schottky barrier diode proceeds to the subsequent step of performing assembly. The semiconductor chip on the wafer is diced, separated into individual semiconductor chips, and the semiconductor chip is fixed to a frame (not shown), and then the anode and cathode bonding pads of the semiconductor chip and predetermined leads (not shown) are bonded with a bonding wire. ). As a bonding wire, it is connected by well-known stitch bonding using a fine gold wire. Thereafter, it is transferred to a resin package.

A substrate of a conventional Schottky barrier diode is to respond to a frequently used type, and has a structure that from the can is also taken out of the cathode is, to form an n ⁺ type epitaxial layer on the n ⁺ type GaAs substrate, In order to secure predetermined characteristics, the upper layer has a structure in which an n-type epitaxial layer of about 1.3 × 10 ¹⁷ cm ^-3 is formed.

Since the Schottky electrode needs to secure certain characteristics, the clean surface of the n-type epitaxial layer is exposed to deposit a metal to form a Schottky junction. In order to reduce the extraction resistance, the ohmic electrode forms an ohmic junction in the underlying n ⁺ type epitaxial layer.

Here, the conventional structure has the following problems. First, in order to form the ohmic electrode 28, a mesa must be formed to expose the n ⁺ type epitaxial layer 22. The n-type epitaxial layer 23 has a thickness of about 3500 kPa, and mesa etching is essential in order to expose the n ⁺ type epitaxial layer 22 thereunder. An oxide film 25 for protecting the substrate is formed on the surface of the substrate, and mesa etching is performed by forming a mask with a photoresist on the surface thereof, but variations in the adhesion between the surface of the oxide film 25 and the resist occur. In such a situation, when wet etching, the etching is extended in the transverse direction more than necessary, and may be etched to the required oxide film 25. When GaAs is exposed, the shape of the mesa becomes unstable. For this reason, the photoresist at the time of forming the ohmic electrode 28 formed in the opening of the mesa also causes sagging to occur in the shape of the peripheral end. Etching to the vicinity of the Schottky junction may cause problems such as adversely affecting characteristics.

Secondly, the anode electrode 34 is formed on GaAs, the majority of which is at the cathode potential, so that the parasitic capacitance here becomes large. Since the area of the intersection is 1300 µm ² , it is essential to reduce the parasitic capacitance with a thick interlayer insulating film. In order to fill the mesa to form a thick interlayer insulating film, a polyimide layer 30 having a thickness of 6 to 7 µm must be formed. Openings are formed in the polyimide layer 30 to take out the electrodes of the Schottky junction region 31a, but step coverage of the electrodes on the polyimide layer 30 is further obtained by etching the thick polyimide layer 30. There is also an object to consider, the opening is tapered. However, the taper angle varies greatly by 30 to 45 degrees due to variations in the film quality of the polyimide layer 30 and variations in adhesion between the polyimide layer 30 and the resist. For this reason, the distance between the Schottky junction region 31a and the ohmic electrode 28, which is the operating region, needs to be about 7 µm in consideration of the taper. However, since the separation distance of each junction contributes to the series resistance, a large separation distance prevents the improvement of the high frequency characteristic and also causes the miniaturization of the chip.

Third, since the taper is formed in the vicinity of the Schottky junction and the ohmic junction, the thickness of the interlayer insulating film 6 µm cannot be maintained in the vicinity of the operating region of the Schottky barrier diode, which increases parasitic capacitance and deteriorates characteristics. There was a problem.

Fourth, since polyimide was used as the interlayer insulating film, or Au plating was used as the bonding pad for taking out the wiring and the electrode, the cost could not be reduced.

Moreover, according to the conventional manufacturing method, there existed the following problems.

First, although the Schottky junction is a Schottky junction to the uppermost n-type epitaxial layer 23, in order to secure an optimum thickness of 2500 kPa in consideration of the breakdown voltage and resistance of the operating layer, an n-type epitaxial layer of about 3500 kPa ( 23) is formed by etching until it becomes 2500 kPa. Since etching at this time is wet etching, it is very difficult to control time and temperature, the vibration width of the wafer in the etching liquid, the vibration speed and the like, and it is required to use the etching liquid within a predetermined freshness holding time. Therefore, according to this method, variations occur in each wafer, which makes it difficult to improve the reproducibility of the operating region characteristics and the high frequency characteristics.

Second, by employing a mesa structure, a mesa etching requiring a large number of steps is required, and a defect may occur due to a change in adhesion between the resist and the oxide film. Moreover, the polyimide layer formation process as an interlayer insulation film, the Au plating formation process for taking out an electrode on a polyimide layer, etc. are required simultaneously, and there existed a problem that a manufacturing flow was complicated and it was not efficient also in time.

Since compound semiconductors have a high price of the substrate itself, it is necessary to reduce the chip size and reduce costs in order to rationalize. In other words, it is inevitable to reduce the chip size and to reduce the cost of the material itself. At the same time, improvement of high frequency characteristics is also required. Moreover, it was also an important subject to simplify the manufacturing process and to improve the efficiency.

SUMMARY OF THE INVENTION The present invention has been made in view of these problems, and includes a compound semiconductor substrate, a flat one-conductive high-concentration epitaxial layer and a one-conducting epitaxial layer, and the epitaxial layer penetrating the high-concentration epitaxial layer. A highly conductive ion implantation region of one conductivity type reaching the shir layer, a first electrode that is ohmic-bonded to the surface of the high concentration ion implantation region, a circular Schottky junction region on the surface of the epitaxial layer surrounded by the first electrode, and And a second electrode for forming the epitaxial layer and the Schottky junction in the Schottky junction region and for extracting the electrode, wherein the ohmic electrode is formed on the surface of the high concentration ion implantation region formed on the substrate surface. By forming a planar Schottky barrier diode of a compound semiconductor is realized, Since the area can also be reduced, the chip size can be reduced, the cost can be reduced, and the parasitic capacitance and resistance can be reduced, thereby contributing to the improvement of the high frequency characteristics.

In addition, one conductivity type high concentration epitaxial layer and one conductivity type epitaxial layer are laminated on the undoped compound semiconductor substrate, and the conductivity reaches from the surface of the epitaxial layer under a predetermined first electrode to the high concentration epitaxial layer. In the step of forming a high concentration ion implantation region of a type, a step of forming a first electrode to be ohmic-bonded to the surface of the high concentration ion implantation region, and a circular Schottky junction region surrounded by an outer circumference of the first electrode. Forming a metal layer forming a Schottky junction with the surface of the tactical layer, extending the metal layer to form a second electrode for extraction of the electrode, and simultaneously forming an extraction electrode of the first electrode with the same metal layer as the metal layer; It characterized by including a process, the short to realize the simplification and efficiency of the manufacturing process, and further improve the high frequency characteristics The barrier diode is to provide a process for producing the same.

Embodiment of the Invention

An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 8.

The Schottky barrier diode of the present invention includes a compound semiconductor substrate 1, a high concentration epitaxial layer 2, an epitaxial layer 3, a high concentration ion implantation region 7, a first electrode 8, And the second electrode 11.

1 is a cross-sectional view of the operating region portion.

The compound semiconductor substrate 1 is an undoped GaAs substrate, on which a high concentration epitaxial layer 2 (5 × 10 ¹⁸ cm ⁻³ ) and a n-type epitaxial layer 3 (2500 × 3) (1.3 × 10) are placed thereon. ¹⁷ cm ^-3 ) are laminated. Mesas are not formed in any of the layers, but have a flat substrate structure.

The high concentration ion implantation region 7 is formed so as to reach the n ⁺ epitaxial layer 2 from the surface of the n-type epitaxial layer 3 under the ohmic electrode 8. It is formed along the outer periphery of the circular Schottky junction region 11a, and substantially overlaps the ohmic electrode 8, and protrudes from the ohmic electrode 8 at least at the portion surrounding the Schottky junction region 11a. The separation distance between the Schottky junction region 11a and the high concentration ion implantation region 7 is 1 μm. In other words, instead of adopting the conventional mesa structure, the high concentration ion implantation region 7 is formed on the surface while the planar structure is maintained, and ohmic bonding can be realized without forming a mesa.

The ohmic electrode 8 serving as the first electrode is the first metal layer which contacts the high concentration ion implantation region 7. AuGe / Ni / Au is sequentially deposited and patterned into a shape with a circular cutout near the Schottky junction. The separation distance from the adjacent Schottky junction region 11a is 2 micrometers.

The second electrode is the anode electrode 11 from the schottky junction region 11a to the anode bonding pad 11b. An n-type epitaxial layer 3 and the second metal layer in which a circular Schottky contact hole having a diameter of 10 µm was formed in the nitride film 5 covering the GaAs surface, and Ti / Pt / Au was sequentially deposited. The Schottky junction region 11a is formed by forming a Schottky junction. Further, the metal layer is extended to the bonding wire fixing area for taking out the electrode to form the anode bonding pad 11b. That is, the Schottky metal layer forming the n-type epitaxial layer 3 and the Schottky junction, and the metal layer forming the wiring and the anode bonding pad 11b for taking out the electrode are the same deposition metal layers as the anode electrode 11. It is. The n-type epitaxial layer 3 serving as the operating region is 2500 kPa, which is optimal for obtaining predetermined characteristics such as breakdown voltage, and the etching process for controlling the thickness of the operating layer required in the past can be omitted. A key junction can be formed and a Schottky barrier diode with stable characteristics can be obtained. In addition, the nitride film 5 is insulated from the ohmic electrode 8 or GaAs which is a cathode potential.

Under the anode bonding pad 11b, an insulating region 6 (hereinafter referred to as an insulating region) is formed by injecting boron or the like. Since the GaAs portion of the insulated region 6 reaching the undoped GaAs substrate does not become the cathode potential, the wire bonding portion can be directly fixed to the substrate without forming the polyimide and nitride film.

The cathode electrode 15 is also Ti / Pt / Au of the second layer and is formed in contact with the ohmic electrode 8 to face the anode electrode 11 with each other. The metal layer of the second layer extends to the cathode bonding region and becomes the cathode bonding pad 15b. The high concentration ion implantation region 7 and the n ⁺ type epitaxial layer 2 which the ohmic electrode 8 contacts become a cathode potential (electrode). The cathode bonding pad 15b is directly adhered to the n-type epitaxial layer 3 surface.

2 and 3 show plan views of the Schottky barrier diode of the compound semiconductor of the present invention. 2 is a schematic diagram of a pattern of a chip, and FIG. 3 is an enlarged view of an operation region portion. This figure shows the case of one Schottky junction as the first embodiment of the present invention.

The anode electrode 11 is formed by sequentially depositing Ti / Pt / Au, which is the second metal layer. The anode electrode 11 has a schottky junction region 11a which forms a Schottky junction with the n-type epitaxial layer 3 at about the center of the chip. This area is a circular shape having a diameter of about 10 mu m, and only the circular portion is in direct contact with GaAs. Further, the metal layer is extended to form the anode bonding pad 11b, and the electrode is taken out.

Under the anode bonding pad 11b, an insulation region 6 into which B ⁺ ions are implanted is formed. As a result, the anode bonding pad 11b can be directly fixed to the substrate without interposing the insulating film, thereby reducing defects in bonding and eliminating parasitic capacitance in the bonding pad portion.

The part shown with the broken line becomes the ohmic electrode 8. As shown in FIG. The outer circumference of the circular Schottky junction region 11a is contacted with the high concentration ion implantation region 7 (not shown). The ohmic electrode 8 is a metal layer of the first layer in which AuGe / Ni / Au is sequentially deposited. It is formed so as to overlap with the high concentration ion implantation region 7, and the cathode electrode 15 by the vapor deposition metal layer of the 2nd layer is formed for extraction of an electrode, and is extended and the cathode bonding pad 15b is formed. In order to reduce the inductor component, which is a factor of high frequency characteristics, extraction of the cathode electrode requires a large amount of bonding wires to be fixed. Therefore, a region occupying half of the chip is used as the bonding region.

Bonding wires are fixed to the anode and cathode bonding pads 11b and 15b by stitch bonding, and electrodes are taken out. The area of the anode bonding pad 11b portion is 60 × 70 μm, and the cathode bonding pad 15b portion is 180 × 70 μm. In connection by stitch bonding, since two bonding wires can be connected by one bonding, even if the bonding area is small, the inductor component which is a parameter of a high frequency characteristic can be made small, and it contributes to the improvement of a high frequency characteristic.

As shown in Fig. 3, the intersection between the anode electrode and GaAs serving as the cathode potential is only an area indicated by diagonal lines, and the area of this portion is about 100 mu m ² . Since this can be reduced to about 1/13 as compared with the conventional 1300 µm, the polyimide, which is an interlayer insulating film, can be substituted for the thin nitride film 5.

The feature of the present invention is to realize the planar structure of the Schottky barrier diode by forming the high concentration ion implantation region 7 and forming the Schottky junction region 11a and the ohmic electrode 8 on the GaAs surface. Since it is not necessary to consider the misalignment due to the change in the mesa shape, the separation distance between the Schottky junction region 11a and the ohmic electrode 8 can be greatly reduced. Insulating regions 6 are formed in most of the regions below the anode electrode 11, and the area of the portion where GaAs serving as the cathode potential and the anode electrode 11 cross each other is about 100 µm ² . Compared with the prior art, the area is 1/13. Since the parasitic capacitance does not need to be suppressed by increasing the polyimide thickness (separation distance), the polyimide layer can be substituted with a thin nitride film, and the tapered portion of the polyimide also does not need to be considered.

Thus, specifically, the separation distance between the Schottky junction region and the ohmic electrode can be reduced from 7 µm to 2 µm. In addition, the separation distance from the high concentration ion implantation region 7 is 1 占 퐉, and in this case, the high concentration ion implantation region 7 has the same effect as that of the ohmic electrode 8 as the carrier's movement path. The distance can be reduced to 1/7. Since the separation distance between the Schottky junction region 11a and the ohmic electrode 8 contributes to the series resistance, if the separation distance can be reduced, the resistance can be further reduced, which can greatly contribute to the improvement of the high frequency characteristics.

This contributes to the miniaturization of the chip, so that the chip size, which was conventionally 0.27 x 0.31 mm 2, can be reduced to 0.25 x 0.25 mm 2. As the size, there is a need to arrange bonding pads, but there is a limit of the chip size that can be handled at the time of assembly, so 0.25 mm2 is the limit in the current situation, but in the operating area can be significantly reduced to about 1/10, As will be described later, the degree of freedom in arranging the operation region is greatly increased.

The anode electrode of the present invention is also characterized in that it has an electrode structure as long as the metal layer forming the Schottky junction is extended. Since the polyimide can be substituted with a thin nitride film, the electrode and the wiring can be realized by the deposited metal layer, which can greatly contribute to the cost reduction.

FIG. 4 shows a case where a plurality of Schottky junction regions 11a formed by the anode electrode 11, which is the second embodiment of the present invention, are formed.

In the structure of the present invention, a plurality of Schottky junction regions 11a can be formed. For example, as shown in FIG. 4, the Schottky junction region 11a is connected in parallel, which can contribute to the reduction of resistance.

In addition, when a plurality of Schottky contact hole diameters are arranged in small numbers, the total Schottky contact hole areas are the same and compared to the case where one is arranged, the separation distance between the center of the Schottky contact hole and the high concentration ion implantation region 7 is reduced. It can further reduce, and the trapping of the carrier in the high concentration ion implantation region 7 becomes effective. As a result, the value of the cathode resistance is reduced, which has the advantage of further improving the high frequency characteristics.

5 to 8 show the manufacturing method of the Schottky barrier diode of the present invention in detail.

The Schottky barrier diode laminates a one conductivity type high concentration epitaxial layer and one conductivity type epitaxial layer on an undoped compound semiconductor substrate, and reaches a high concentration epitaxial layer from the surface of the epitaxial layer under a predetermined first electrode. Forming a highly conductive ion implantation region of one conductivity type, forming a first electrode to be ohmic-bonded to the surface of the high concentration ion implantation region, and forming a Schottky junction on the surface of the epitaxial layer surrounded by the first electrode Forming a metal layer, extending the metal layer to form a second electrode for taking out the electrode, and simultaneously forming a takeout electrode of the first electrode from the metal layer.

In the first step of the present invention, as shown in Fig. 5, a high conductivity epitaxial layer 2 and one conductivity type epitaxial layer 3 are laminated on an undoped compound semiconductor substrate 1, The high concentration ion implantation region 7 of one conductivity type that reaches the high concentration epitaxial layer 2 is formed from the surface of the epitaxial layer 3 under the predetermined first electrode 8.

This process is a feature of the present invention, in which high concentration ion implantation penetrates the n-type epitaxial layer 3 under the region where the predetermined ohmic electrode 8 is formed and reaches the n ⁺ type epitaxial layer 2. The region 7 is formed.

That is, n ⁺ type epitaxial layer 2 (5 x 10 ¹⁸ cm ^-3 ) is deposited on the undoped GaAs substrate 1 about 5000 m ³ , and the n type epitaxial layer 3 (1.3 x 10 ¹⁷ ) is deposited thereon. Cm- ³ ) is deposited at 2500Å. Thereafter, the entire surface is covered with a nitride film 5, a resist layer is formed, and a photolithography process for selectively windowing the resist layer on the predetermined insulating region 6 is performed. Then, using this resist layer as a mask, ion implantation of B ⁺ impurities is performed to form the insulating region 6 up to the undoped GaAs substrate 1, whereby GaAs and the anode bonding pad portion 11b serving as cathode potentials are formed. I insulate with and.

Next, a photolithography process is performed to selectively window the resist layer on the region where the predetermined high concentration ion implantation region 7 is to be formed. Thereafter, a high concentration of n-type impurities (Si ⁺ , about 1 x 10 ¹⁸ cm ^-3 ) is ion-implanted using the resist layer as a mask, and the n-type epitaxial layer 3 under the predetermined ohmic electrode 8 is formed. The high concentration ion implantation region 7 extending through the n ⁺ type epitaxial layer 2 is formed. At this time, the ion implantation is implanted a plurality of times under different conditions, so that the impurity concentration of the high concentration ion implantation region 7 is as uniform as possible in the depth direction.

Thereafter, the resist layer is removed, and the nitride film 5 is deposited again for annealing, and activation anneal of the high concentration ion implantation region 7 and the insulation region 6 is performed.

As a result, a high concentration ion implantation region 7 is formed under the predetermined ohmic electrode 8. By forming the ohmic electrode 8 on the surface of the high concentration ion implantation region 7 in a later step, a Schottky barrier diode having a planar structure is realized. As a result, the separation distance between the Schottky junction region and the high concentration ion implantation region having the same function as the ohmic electrode can be greatly reduced, resulting in a Schottky barrier diode that can greatly reduce the series resistance and contribute to the improvement of the high frequency characteristics. .

In the second step of the present invention, as shown in FIG. 6, the first electrode 8 to be ohmic-bonded to the surface of the high concentration ion implantation region 7 is formed.

A photolithography process is performed in which a resist layer is formed over the entire surface, and selectively windowed a portion for forming a predetermined ohmic electrode 8. The nitride film 5 exposed from the resist layer is removed, and three layers of AuGe / Ni / Au, which are the metal layers of the first layer, are sequentially deposited by vacuum deposition. Thereafter, the resist layer is removed by lift-off, leaving the metal layer of the first layer on the predetermined ohmic electrode 8 portion. Subsequently, the ohmic electrode 8 is formed on the surface of the high concentration ion implantation region 7 by alloying heat treatment.

In the third process of the present invention, as shown in FIGS. 7 and 8, a metal layer forming a Schottky junction is formed on the surface of the epitaxial layer 3 surrounded by the outer periphery of the first electrode 8, and the metal layer is extended. The 2nd electrode 11 used for extraction of an electrode is formed, and the extraction electrode 15 of the 1st electrode 8 is formed simultaneously with a metal layer.

This step is a feature of the present invention. First, in Fig. 7, a nitride film, which becomes an interlayer insulating film, is deposited on the entire surface of about 5000 kPa. Thereafter, the resist layer PR is formed on the entire surface, and a photolithography process is performed to selectively window portions of the predetermined Schottky junction region 11a, the anode bonding pad 11b, and the cathode electrode 15. The exposed nitride film 5 is dry etched, and the resist layer PR is removed to form a contact hole 9 in which the n-type epitaxial layer 3 is exposed.

Then, as shown in FIG. 8, a resist is again formed on the whole surface, and the photolithography process of selectively creating the pattern of the anode electrode 11 and the cathode electrode 15 is performed. Three layers of Ti / Pt / Au, which are the metal layers of the second layer, are sequentially deposited on the entire surface by vacuum deposition, and the resist layer PR is removed by lift-off. Thereby, the anode electrode 11 which extends the metal layer which forms the schottky junction region 11a to the anode bonding pad 11b on the surface of the n-type epitaxial layer 3 is formed. At the same time, the ohmic electrode 8 is contacted to form the cathode electrode 15 which extends to the cathode bonding pad 15b. Thereafter, the back surface is subjected to back lapping treatment.

In the conventional manufacturing method, since the control of the thickness of the operating layer is required, precise control such as the time and temperature, the vibration width of the wafer in the etching solution, the vibration speed, etc. in the GaAs etching step is very difficult. It is required to use within a predetermined freshness holding time. However, according to the manufacturing method of the present invention, if the epitaxial layer 3 of 2500 kPa which is optimal as the operating layer is formed in advance, the etching step for controlling the thickness of the operating layer can be omitted, so that the reproducibility is short. The key junction can be formed, which has the advantage of producing a Schottky barrier diode with stable characteristics.

In addition, the anode electrode 11 and the cathode electrode 15 are vapor deposition metals formed by the normal lift-off method. In addition, the interlayer insulating film between the anode electrode 11 and the ohmic electrode 8 is the nitride film 5, and the bonding pad portion can also be directly fixed to the substrate, so that the polyimide layer can be omitted. Thereby, the Au plating process of wiring and bonding pad formation thickly formed in order to absorb the problem of polyimide on a polyimide layer can be skipped conventionally. If the polyimide layer formation process and Au plating process which perform several coating can be skipped, a manufacturing flow can be simplified and a Schottky barrier diode can be manufactured efficiently.

When the whole process is completed, the compound semiconductor Schottky barrier diode proceeds to the subsequent step of assembling. The semiconductor chip on the wafer is diced, separated into individual semiconductor chips, and the semiconductor chip is fixed to a frame (not shown), and then the bonding pads 11b and 15b of the semiconductor chip and predetermined leads are bonded with a bonding wire. (Not shown). As a bonding wire, it is connected by well-known stitch bonding using a fine gold wire. Thereafter, it is transferred to a resin package.

According to the structure of the present invention, numerous effects described below can be obtained.

First, the planar structure of the Schottky barrier diode can be realized by forming the high concentration ion implantation region 7 on the GaAs surface and forming the Schottky junction region 11a and the ohmic electrode 8 on the GaAs surface. The change in the shape of the ohmic electrode and the deterioration of the characteristics due to the change in the mesa shape can be suppressed, and the misalignment need not be taken into account, so that the separation distance between the schottky junction region 11a and the ohmic electrode 8 can be greatly reduced. . Since the separation distance between the Schottky junction region 11a and the ohmic electrode 8 contributes to the series resistance, the resistance can be further reduced if the separation distance can be reduced.

Second, the area where the GaAs serving as the cathode potential and the anode electrode 11 intersect is about 100 µm ² , and parasitic capacitance is greatly reduced. This is because the insulating region 6 is formed in most of the areas under the anode electrode 11, whereby the area of the intersection generating parasitic capacitance can be reduced to 1/13 only by the Schottky junction portion as compared with the prior art. It becomes possible. In addition, since the anode bonding pad 11b can also be directly fixed to GaAs, the parasitic capacitance in this portion does not occur, and the overall parasitic capacitance can be greatly reduced. Conventionally, although a parasitic capacitance must be suppressed and polyimide with low dielectric constant is used to form a thick interlayer insulating film, it can be substituted by a thin nitride film. The nitride film has a higher dielectric constant than that of polyimide, but according to the structure of the present invention, even when a nitride film of about 5000 kPa is used, the parasitic capacitance can be reduced compared with the conventional one.

Third, since the thick polyimide is not used, it is not necessary to consider the distance of the tapered portion of the polyimide opening to be the operating region and the variation of the taper angle.

In view of the above, the separation distance between the Schottky junction region and the ohmic electrode only needs to consider the breakdown voltage and the mask matching accuracy. Specifically, the separation distance between the Schottky junction region and the ohmic electrode can be reduced from 7 μm to 2 μm. In addition, since the separation distance from the high concentration ion implantation region 7 is 1 μm, in this case, the high concentration ion implantation region 7 has the same effect as that of the ohmic electrode 8 as a carrier movement path. It can be reduced to 1/7. Therefore, significant reduction in resistance, significant reduction in parasitic capacitance, and reduction in variation in parasitic capacitance can greatly contribute to the improvement of high frequency characteristics.

Fourth, by contributing to the miniaturization of the chip, the chip size was conventionally 0.27 x 0.31 mm 2, but can be reduced to 0.25 x 0.25 mm 2. As the size, 0.25 mm2 is the limit in the present situation because there is a need to arrange a bonding pad or a chip size that can be handled during assembly. However, since the operating area can be significantly reduced to about 1/10, The degree of freedom for arranging regions is greatly increased.

Fifth, resistance can be further reduced by forming a plurality of Schottky junction regions. When a plurality of Schottky junctions are formed with a small contact diameter, the resistance is further reduced compared to the case where one Schottky junction region having the same Schottky contact area is formed, thereby trapping the carrier trap in the high concentration ion implantation region. Since it can be effective, it has the advantage that a high frequency characteristic improves more.

Sixth, since the anode electrode can be realized with the same metal layer as the metal layer forming the Schottky junction without using a polyimide layer or gold plating, the material cost can be reduced, the chip is reduced, and the cost is greatly reduced. do.

Moreover, according to the manufacturing method of this invention, the effect disclosed below can be acquired.

First, since it becomes possible to form a stable Schottky junction, it is possible to suppress fluctuations in characteristics, which is a very important task in a high frequency circuit. The n-type epitaxial layer is formed at an optimum 2500 kV as the operating layer, so that precise GaAs etching control as in the prior art is unnecessary. In other words, the yield is improved, the reproducibility is good, and the production of the Schottky barrier diode having stable characteristics is possible.

Second, the above-described production of the Schottky barrier diode can be efficiently realized and the manufacturing process can be simplified further. Specifically, it is a mesa etching process, an n-type epitaxial layer etching process before a Schottky junction formation, a polyimide layer forming process, Au plating process, etc. Since the polyimide layer has a thickness of 6 to 7 µm, a plurality of coatings are repeatedly formed. Coating the polyimide layer several times takes time and the manufacturing flow is complicated. Moreover, when polyimide becomes unnecessary, the electrode by Au plating layer also becomes unnecessary. Conventionally, in order to prevent breakage or deformation of the electrode due to heat during solder mounting or stress during wire bonding, it is necessary to secure the strength of the electrode, and an anode electrode and a cathode electrode are formed by a thick Au plating layer. However, if the polyimide layer is not necessary, the influence does not need to be considered. In other words, the gold-plated electrode becomes unnecessary, and the Schottky junction region, the anode electrode, and the cathode electrode can be formed only by the deposition metal of Ti / Pt / Au, thereby improving the reliability. In addition, since the above-mentioned factors which have caused the lowering of the conventional yield are eliminated, the yield is also improved.

That is, the Schottky barrier diode which can greatly reduce the parasitic capacitance and can significantly improve the high frequency characteristics by reducing the resistance, has an advantage of providing a manufacturing method which can simplify the manufacturing process and improve the efficiency.

Claims (13)

delete A compound semiconductor substrate, A flat one conductivity type high concentration epitaxial layer and one conductivity type epitaxial layer formed on the substrate; A high concentration ion implantation region of one conductivity type penetrating the epitaxial layer and reaching the high concentration epitaxial layer; A first electrode which is ohmic-bonded to the surface of the high concentration ion implantation region, A second Schottky junction region on the surface of the epitaxial layer surrounded by the first electrode, and a Schottky junction in the Schottky junction region, and for extracting the electrode Schottky barrier diode comprising a. The method of claim 2, The Schottky barrier diode which forms the electrode for taking out the said 1st electrode from the metal layer used as a said 2nd electrode. The method of claim 2, And the compound semiconductor substrate is a undoped GaAs substrate. The method of claim 2, The Schottky barrier diode between the second electrode and the high concentration ion implantation region is between 1 μm and 5 μm. The method of claim 2, A Schottky barrier diode for forming a plurality of Schottky junction regions in which the second electrode is formed. The method of claim 2, The high concentration ion implantation region protrudes from the first electrode. delete One conductivity type high concentration epitaxial layer and one conductivity type epitaxial layer are laminated on an undoped compound semiconductor substrate, and the one conductivity type reaching the high concentration epitaxial layer from the surface of the epitaxial layer under a predetermined first electrode. Forming a high concentration ion implantation region, Forming a first electrode which is ohmic-bonded to the surface of the high concentration ion implantation region, In a circular Schottky junction region surrounded by the first electrode, a metal layer forming a Schottky junction with the surface of the epitaxial layer is formed, and the metal layer is extended to form a second electrode for extraction of the electrode. And simultaneously forming an extraction electrode of the first electrode from the same metal layer as the metal layer. Schottky barrier diode manufacturing method comprising a. The method of claim 9, And the second electrode is formed by sequentially depositing a multilayer metal layer of Ti / Pt / Au. The method of claim 9, And forming bonding pads of the first and second electrodes with the metal layer, respectively. The method of claim 2, The second electrode extends on the first electrode to intersect the first electrode through an insulating film. The method of claim 9, And the second electrode extends on the first electrode to intersect the first electrode via an insulating film.

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