TWI267193B - Schottky barrier diode and process therefor - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
Description
12671931267193
發明說明Q) [發明所屬之技術領域] 特基屏障二二ί關一種採用高頻電路之化合物半導體的肖 造而實現動作二3其衣&方1 ’尤其有關藉由形成平面構 障二極體及化的化合物半導體肖特基屏 [先前技術] 南頻裝置隨著全球行動電話市場擴大, 星收送訊機之+、卡担古^ 4秘:::和因應數位衛 女务接用/而未k问急乓。元件由於要處理高頻, 斤用鎵.坤(GaAs)之電場效果電晶體,並隨之進 仃開叙珂述開關電路本身積體化之單石微 =之進 (MMIC),和局部振盪用FET。 積體電路 长。且,GaAs肖特基屏障二極體亦因基地局用等而增加需 第9圖表示習知之肖特基屏障二極體動作區 剖視圖。 '^ ^ 在Π+型GaAs基板上方21,將Π+型磊晶層22(5x 1〇lfcm ,積層大約6/z m,進一步將當作動作層之n型磊晶層2 3x 1 0 Am _3)例如堆積大約35 0 0A。 · 形成歐姆電極(仏1!1卜616(^1*0(16)28的第1層金屬声 在n+型蠢晶層22歐姆接合之AuGe/Ni/Au。第2層金屬層曰為 Ti/Pt/Au,該第2層金屬層的圖案為陽極側和^極側2曰種‘\ 在陽極側和η型蠢晶層2 3形成肖特基接合。以下將具歹 肖特基接合區域31a的陽極側之第2層金屬層稱為肖特美^ 極31。肖特基電極31亦當作形成陽極焊塾的第3層錄 之基底電極,雙方的圖案完全重疊。陰極側的第2層金^[Explanation of the Invention] Q) [Technical Field to Be Invented by the Invention] The special-based barrier is used to realize the action of a compound semiconductor using a high-frequency circuit, and the action 2 is particularly related to the formation of a planar structure. Polar body and compound semiconductor Schottky screen [Prior technology] With the expansion of the global mobile phone market, the satellite transmission and delivery machine +, Kadangu ^ 4 secret::: and in response to the digital female service Use / without k questioning. Due to the high frequency of the components, the electric field effect transistor of GaN is used, and the monolithic micro-integration (MMIC) and local oscillation of the switching circuit itself are introduced. Use FET. The integrated circuit is long. Further, the GaAs Schottky barrier diode is also increased by the base station, etc., and Fig. 9 is a cross-sectional view showing the conventional Schottky barrier diode operating region. '^ ^ Above the Π+-type GaAs substrate, 21, Π+-type epitaxial layer 22 (5x 1〇lfcm, layered approximately 6/zm, further as the n-type epitaxial layer of the action layer 2 3x 1 0 Am _3 For example, stacking about 355 A. · Form an ohmic electrode (仏1!1 616 (^1*0(16)28 of the first layer of metal sound in the n+ type stray layer 22 ohmically bonded AuGe/Ni/Au. The second layer of metal layer 曰 is Ti /Pt/Au, the pattern of the second metal layer is the anode side and the second side of the metal layer, and the Schottky junction is formed on the anode side and the n-type doped layer 23. The following will be a Schottky junction. The second metal layer on the anode side of the region 31a is referred to as a Schottky electrode 31. The Schottky electrode 31 is also used as a base electrode for forming a third layer of the anodized electrode, and the patterns on both sides are completely overlapped. 2nd layer of gold ^
案號 91116690 1267193 修」 五、發明說明(2) 層和歐姆電極接觸,進一步當作形成陰極焊墊的第3層艘 Au層之基底電極,和陽極側同樣地,冑方的圖荦完全重 疊。肖特基電=31=必須將該圖案端的位置配設在聚醯 亞胺層上面’ 0此在肖特基接合區域3U周邊形成重疊 在16" m陰極側之圖案。肖特基接合部以外的基板為陰極 電位,陽極電極34和陰極電位之⑽交又部分設有用於絕 緣的聚鉍亞胺層30。该父叉部分面積形成大約i3〇〇#…, 由於有很大的寄生容量’必須將該間隔距離形成大約6至7 // m的厚度以緩和寄生容量。聚醯亞胺因該低介電常數和 可厚形成之性質’而被採用當作層間絕緣膜。 肖特基接合區域3 1 a為了碟保大約1 〇 v的耐壓和良好的 肖特基特性’設在大約1 · 3x 1 〇 _磊晶層2 3上方。 另一方面,歐姆電極2 8為了減少輸出電阻,設在藉由平台 蝕刻(mesa etching)而露出之n+型磊晶層22表面。且,n + 型蠢晶層22的下層為高濃度GaAs基板2 1,設有歐姆電極μ 之A u G e / N i / A u當作裡面電極,亦可對應從基板裡面輸出的 機種。 第1 0圖表示習知之化合物半導體肖特基屏障二極體之 俯視圖。 在晶片大約中央,η型磊晶層2 3上方形成肖特基接合 區域3 1 a。該區域為直徑大約丨m的圓形,係將第2層金 屬層之Ti/Pt/Au順序澱積且形成在露出_磊晶層23的肖 特基接觸孔2 9。第1層金屬層之歐姆電極2 8係設成包圍圓 形的肖特基接合區域3丨a之外周。歐姆電極2 8為依序澱積 AuGe/N 1 /Au之構件,設在大約晶片一半之區域。且,為了Case No. 91116690 1267193 Revision 5. V. Inventive Note (2) The layer is in contact with the ohmic electrode, and is further used as the base electrode of the Au layer of the third layer of the cathode pad. As with the anode side, the pattern of the square is completely overlapped. . Schottky electricity = 31 = the position of the pattern end must be disposed on the polyimine layer. Here, a pattern overlapping the 16" m cathode side is formed around the Schottky junction region 3U. The substrate other than the Schottky junction is a cathode potential, and the anode electrode 34 and the cathode potential (10) are further provided with a polyimide layer 30 for insulation. The area of the parent fork portion is formed to be approximately i3 〇〇 #..., due to the large parasitic capacity 'the distance must be formed to a thickness of about 6 to 7 // m to alleviate the parasitic capacity. Polyimine is used as an interlayer insulating film due to the low dielectric constant and the property of being thickly formed. The Schottky junction region 3 1 a is provided with a withstand voltage of about 1 〇 v and a good Schottky property for a disk of about 1 · 3 x 1 〇 _ epitaxial layer 2 3 . On the other hand, in order to reduce the output resistance, the ohmic electrode 28 is provided on the surface of the n + -type epitaxial layer 22 exposed by mesa etching. Further, the lower layer of the n + -type stray layer 22 is a high-concentration GaAs substrate 2 1, and A u G e / N i / A u having an ohmic electrode μ is used as a back electrode, and may also correspond to a model output from the inside of the substrate. Fig. 10 shows a plan view of a conventional compound semiconductor Schottky barrier diode. At about the center of the wafer, a Schottky junction region 31a is formed over the n-type epitaxial layer 23. This region is a circle having a diameter of about 丨m, and Ti/Pt/Au of the second metal layer is sequentially deposited and formed in the Schottky contact hole 29 of the exposed epitaxial layer 23. The ohmic electrode 28 of the first metal layer is provided so as to surround the outer circumference of the circular Schottky junction region 3a. The ohmic electrode 28 is a member in which AuGe/N 1 /Au is sequentially deposited, and is disposed in a region approximately half of the wafer. And, in order
313892.ptc 第11頁 _案號 91116690 1267193313892.ptc Page 11 _ Case No. 91116690 1267193
五、發明說明(3) 電極之輪出,使第2層金屬層 底電極。 人姆毛極2 8接觸,當作基 陽極側及陰極側之基底電極 裝設。陽極側設在和肖特基接人二 s之鍍Au層而 須的最小範圍區域,陰極側形二二3 1 a。卩刀:):干接時所必 域周形狀之圖案。且】,升為成了包二圓賴特基接合區 應件成刀,必須固設多條焊接線,因此將佔 素之感 半的區域當作焊接區域。 ’ 日日片大約— “ : 1卜々以和基底電極重疊的方式裝設鍍域。此产 猎由針腳式接合固設焊接線,且輸出電極。 ^, 4 Ox 6 0// m2,陰極焊墊部為2 〇 7 〇 2 ^ 干墊口P為 -Γ | △υχ ’m2。藉由針腳式拉人 連接日守,由於1次焊接可連接2條焊接線,即使焊接面 的構:亦可減少高頻特性參數之感 ^ 高頻特性。 β刀瓦钕歼 製造二i1圖至第15圖中’表示習知之肖特基屏障二極體之 第11圖中,藉由平台蝕刻露出n+型磊晶層22,並附 第1層金屬層形成歐姆電極2 8。 即’在n + GaAs基板21將n+型磊晶層22(5x HPfcm -¾隹積 大約6// m,在該上方將麵磊晶層23(ΐ 3χ 1〇^ _3)堆積大 約350 0A厚。然後將氧化膜25覆蓋全面,再將預定的歐姆 電極28上方之抗触層進行選擇性開窗之光蝕刻法。然後, 用該抗钮層當作遮罩,將預定的歐姆電極28部分之氧化膜 25餘刻,進一步進行n型磊晶層23之平台蝕刻而露出n+型、 蠢晶層2 2。V. INSTRUCTIONS (3) The electrode is turned out to make the second layer of the metal layer bottom electrode. The human hair electrode is contacted by 2 8 and is installed as a base electrode on the anode side and the cathode side. The anode side is located in the minimum range area required for the Au layer plating with the Schottky junction, and the cathode side is 22 1 a. Sickle:): The pattern of the shape of the perimeter of the field when dry. And, it has been upgraded into a two-ring Wright base joint. The parts must be formed into a knife, and a plurality of weld lines must be fixed. Therefore, the area where the sense of sensation is half is regarded as the welded area. '日日片约— " : 1 Diwax is equipped with a plating field in such a way as to overlap with the base electrode. This production is fixed by a stitch-type bonding wire and output electrodes. ^, 4 Ox 6 0// m2, cathode The pad portion is 2 〇7 〇2 ^ The dry pad P is -Γ | △υχ 'm2. By connecting the pin to the day, the welding line can be connected by one welding, even if the welding surface is constructed: It is also possible to reduce the sense of high-frequency characteristic parameters. High-frequency characteristics. β 刀 钕歼 钕歼 二 i i i i i ' ' ' ' ' ' ' ' 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第An n+ type epitaxial layer 22 is attached with a first metal layer to form an ohmic electrode 28. That is, 'the n + type epitaxial layer 22 is deposited on the n + GaAs substrate 21 (5 x HPfcm -3⁄4 is accumulated by about 6 // m, in the The epitaxial layer 23 (ΐ 3χ 1〇^ _3) is stacked on the upper side to be about 350 0 A. Then, the oxide film 25 is covered, and the anti-contact layer above the predetermined ohmic electrode 28 is selectively fenestrated. Then, using the anti-button layer as a mask, the oxide film of the predetermined portion of the ohmic electrode portion 28 is left for further, and the platform of the n-type epitaxial layer 23 is further advanced. Engraved exposed n + type polycrystalline layer 22 stupid.
313892.ptc 第12頁 1267193 , a r _案號91Π6690_年9月S曰 修正_ 五、發明說明(4) 然後,將第1層金屬層之A u G e / N i / A u三層順序真空殿 積並積層。然後,除去抗蝕層,在預定的歐姆電極2 8部分 留下金屬層。接著,藉由合金化熱處理在η +形磊晶層2 2形 成歐姆電極2 8。 第1 2圖中,形成肖特基接觸孔2 9。在全面形成新的抗 蝕層,且將預定的肖特基接合區域31 a部分,進行選擇性 開窗之光蝕刻法。將露出的氧化膜2 5蝕刻後除去抗蝕劑, 形成露出預定的肖特基接合區域3 1 a部之η型磊晶層2 3的肖 特基接觸孔2 9。 第1 3圖中,形成用於絕緣之聚醯亞胺層3 0。將聚醯亞 胺數次鍍膜在全面,設厚聚醯亞胺層3 0。全面形成新的抗 蝕層,且進行選擇性開窗之光蝕刻法而留下預定的聚醯亞 胺層3 0部分。然後,藉由濕式蝕刻除去露出的聚醯亞胺。 然後除去抗蝕層,使聚醯亞胺層3 0硬化,形成6至7/z m的 厚度。 弟1 4圖中’將露出在为特基接觸孔2 9内部之η型蠢晶 層2 3钱刻,形成具有肖特基接合區域3 1 a的肖特基電極 3卜 使用肖特基接觸孔2 9周圍的氧化膜2 5當作遮罩,將η 型蠢晶層2 3#刻。如前述,接觸孔2 9形成後,就在η型蠢 晶層2 3表面露出之狀態,形成聚醯亞胺層3 0。肖特基接合 必須形成在乾淨的GaAs表面,因此須在肖特基電極形成前 將η型磊晶層2 3表面蝕刻。此外,為了確保當作動作層之 最適當厚度2 5 0 0 A,須精密地控制溫度及時間,從大約 3 5 Ο 0A的厚度濕式蝕刻成2 5 Ο ΟA。313892.ptc Page 12 1267193, ar _ Case No. 91Π6690_ September S曰 Amendment _ V. Invention Description (4) Then, the first layer of metal layer A u G e / N i / A u three-layer order The vacuum is accumulated and layered. Then, the resist layer is removed, leaving a metal layer in a portion of the predetermined ohmic electrode 28. Next, an ohmic electrode 28 is formed in the η + -type epitaxial layer 2 2 by alloying heat treatment. In Fig. 22, a Schottky contact hole 29 is formed. A photolithography method of selective windowing is performed by completely forming a new resist layer and a predetermined portion of the Schottky junction region 31a. The exposed oxide film 25 is etched, and the resist is removed to form a Schottky contact hole 29 which exposes the n-type epitaxial layer 23 of the predetermined Schottky junction region 31a. In Fig. 13, a polyimine layer 30 for insulation is formed. The polyimide was coated several times in a comprehensive manner, and a thick polyimine layer was set at 30. A new resist layer is formed in its entirety, and a selective windowing photolithography is performed to leave a predetermined portion of the polyimide layer 30. The exposed polyimine is then removed by wet etching. The resist layer is then removed to harden the polyimide layer 30 to a thickness of 6 to 7/z m. In the figure 14, the 'n-type stray layer 2 which is exposed inside the contact hole 29 is formed, and the Schottky electrode 3 having the Schottky junction region 3 1 a is formed to use the Schottky contact. The oxide film 25 around the hole 2 9 is used as a mask, and the n-type stray layer 2 3 is engraved. As described above, after the contact hole 29 is formed, the polyimine layer 30 is formed in a state where the surface of the n-type doped layer 23 is exposed. The Schottky junction must be formed on a clean GaAs surface, so the surface of the n-type epitaxial layer 23 must be etched before the Schottky electrode is formed. In addition, in order to ensure the optimum thickness of the action layer of 2,500 A, the temperature and time must be precisely controlled to be wet etched to a thickness of about 3 5 Ο 0 A to 2 5 Ο Ο A.
313892.ptc 第13頁 1267193313892.ptc Page 13 1267193
將預定的陽極電極34及陰極電極35部分之基底電極* 二抗蝕層覆蓋其他後,進行電解鍍金。此時抗蝕層: ,僅基底電極露出之部分附著鍍^, ϋ銑削,、;肖除未施行鑛Au部分之基底電極, 極電極34、35形狀之圖案。此時,陶分 題”曰被遣除,但因為有大約k m的厚度,π會造成問 杆人2仆t二裡面背面磨光,且依序殿積AuGe/Ni/Au,施 B …处理,形成裡面的歐姆電極2 8。 務棘2 ί物Γ S體*特基屏障二極體完成前段步驟時,即 宝丨彳n w Μ ί ΐ 2之後段步驟。切割晶圓形半導體晶片,分 告J個別的半導體晶片,a定# 士、蓄 - VA pe ^片 將δ亥丰蜍體晶片固設在框架(不圖 々道a r又闰-、牛¥體日日片的陽極及陰極焊墊和預定 之導線(不圖不)連接。用 知之針腳式接合連:。;二屬細線當作焊接線,以眾所週 妾 …、、後,施行傳送模塑法而將樹脂包 封〇 發明所之 習知之肖特基屏障-托舰 ^ 的機種之方式,形成亦;從構造,以可對應繁忙 _ J J攸理面輸出陰極電極的構造,在After the predetermined anode electrode 34 and the base electrode of the cathode electrode 35 portion are covered with the second resist layer, electrolytic gold plating is performed. At this time, the resist layer: only the portion where the base electrode is exposed is adhered to the plating, the boring is milled, and the pattern of the shape of the base electrode of the Au portion of the ore and the electrode electrodes 34 and 35 is not removed. At this time, the pottery title "曰 is removed, but because there is a thickness of about km, π will cause the back of the servant 2 servant 2 to polish the back, and sequentially accumulate AuGe/Ni/Au, apply B ... , forming the ohmic electrode 2 8 inside. The thorns 2 ί Γ S body * special barrier diodes complete the previous step, that is, the steps of the 丨彳 丨彳 nw Μ ί ΐ 2. Cutting the circular semiconductor wafer, Advise J's individual semiconductor wafers, a fixed #士, 储- VA pe ^ film to fix the δ海丰蜍 body wafer in the frame (not 々 ar ar 闰 、 、 、 、 、 、 、 、 、 、 、 、 The pad is connected to the predetermined wire (not shown). It is connected by a pin-and-pin type: the second wire is used as a welding wire, and the resin is wrapped by a transfer molding method. The method of the conventional Schottky barrier-to-ship type of the invention is formed, and the structure of the cathode electrode is outputted in accordance with the busy _JJ 面 surface.
313892.ptc 第14頁 1267193 _ 案號 91116690 五、發明說明(6) 年?月爹曰 修正 η +型G a A s基板上方設η +型蠢晶層’該上層形成設有大約1. 3χ 1 0 Am _的η型磊晶層之構造,用以確保所定特性。 肖特基電極由於必須確保預定之特性,因此露出η型 磊晶層乾淨的表面且澱積金屬,形成肖特基接合。歐姆電 極為了減少輸出電阻,在該下層η+型磊晶層形成歐姆接 合0 此處,習知之構造中,有以下所示問題。第1,為了 形成歐姆電極2 8,必須形成平台且露出η+型磊晶層2 2。η 型磊晶層23具有大約3 5 0 0人的厚度,為了露出該下方之η + 型磊晶層2 2而必須台面蝕刻。基板表面設有用於保護基板 的氧化膜2 5,平台蝕刻係在該表面設光阻劑之遮罩而蝕 刻,但和氧化膜2 5表面會發生光阻劑密接性不均。在該狀 況中濕式蝕刻時,蝕刻會朝橫向擴張至必要以上,可能會 蝕刻到必要的氧化膜25,如果露出GaAs則平台形狀會不安 定。因此,設在平台開口部的歐姆電極2 8形成時之光阻 劑,周端部形狀亦將發生變形等,結果可能因為剝離造成 歐姆電極28的形狀惡化,或GaAs餘刻至肖特基接合附近, 而發生對特性造成不良影響之問題。 第2 ’陽極電極3 4該大部分係設在形成陽極電位之 GaAs上方,會有此處的寄生容量變大之問題。由於交叉部 分面積為1 3 0 0// m 2,必須以厚層間絕緣膜減少寄生容量。 為了埋入平台當作厚層間絕緣膜,必須裝設6至7// in的聚 醯亞胺層3 0。為了輸出肖特基接合區域3 1 a之電極而在聚 醯亞胺層3 0設有開口部,但因為厚聚醯亞胺層3 0之蝕刻, 且以考慮聚醯亞胺層3 0上方電極之階段式覆蓋率為目的,313892.ptc Page 14 1267193 _ Case No. 91116690 V. Announcement (6) Year? The 爹曰 + type G a A s substrate is provided with an η + type stray layer. The upper layer is formed with a structure of an n type epitaxial layer of about 1.3 Å 1 0 Am _ to ensure a predetermined characteristic. Since the Schottky electrode must ensure a predetermined characteristic, the clean surface of the n-type epitaxial layer is exposed and metal is deposited to form a Schottky junction. The ohmic power extremely reduces the output resistance, and the η+ type epitaxial layer forms an ohmic junction 0. Here, the conventional structure has the following problems. First, in order to form the ohmic electrode 2 8, it is necessary to form a land and expose the n + -type epitaxial layer 2 2 . The n-type epitaxial layer 23 has a thickness of about 3,500 people, and it is necessary to mesa etching in order to expose the underlying η + -type epitaxial layer 2 2 . An oxide film 25 for protecting the substrate is provided on the surface of the substrate. The etching of the substrate is performed by masking the photoresist on the surface, but unevenness of photoresist adhesion occurs on the surface of the oxide film 25. In the case of wet etching in this case, the etching may be laterally expanded to more than necessary, and the necessary oxide film 25 may be etched, and if GaAs is exposed, the shape of the stage may be unstable. Therefore, the photoresist which is formed when the ohmic electrode 28 of the opening portion of the stage is formed, the shape of the peripheral end portion is also deformed, etc., and as a result, the shape of the ohmic electrode 28 may be deteriorated due to peeling, or the GaAs is left to Schottky junction. Nearby, there is a problem that adversely affects the characteristics. Most of the second 'anode electrode 3 4 is provided above the GaAs forming the anode potential, and there is a problem that the parasitic capacitance here becomes large. Since the cross-sectional area is 1 300 / m 2 , the parasitic capacitance must be reduced by a thick interlayer insulating film. In order to embed the platform as a thick interlayer insulating film, a 6 to 7//in polyimine layer 30 must be provided. An opening is provided in the polyimide layer 30 for outputting the electrode of the Schottky junction region 3 1 a, but because of the etching of the thick polyimide layer 30, and considering the polyimine layer 30 The stage coverage of the electrode is the purpose,
313892.ptc 第15頁 案號 91116690 1267193313892.ptc Page 15 Case No. 91116690 1267193
五、發明說明(7) _ :在該開口部形成推拔。但因為 均,或聚醯亞胺層30和光阻劑之资亞胺層30之膜質不 會形成30至45度之嚴重不均二因=接性不均,該推拔角度 合區域31a和歐姆電極28之間隔距’動作區域之肖特基接 確保大約7// m。但,因為該各接人’若考慮推拔則必須 電阻,因此間隔距離大就會阻礙二^間隔距離有助於串聯 為晶片小型化不進展之原因。鬲^員特性之提昇,且亦成 第3,由於肖特基接合及 因此肖特基屏障二極體之動作 s的附近形成推拔, 嗅的μ轉度,亦有成為使寄=無法保持層間絕緣 原因之問題。 里增加,使特性惡化的 第4,由於採用聚醯亞胺當作声 Au當作配線及電極輸出之曰0、,、巴緣膜,或採用鍍 因。 而成為無法減少成本的要 本高:因此方:AS基板°又Ω+型蠢晶層及η型蠢晶層的晶圓成 承问,因此亦有阻礙減少成本之問題。 且,依據習知之製造方法會有以下問題。 23 了肖#特基接合係使肖特基接合在最上層_磊晶層 ㈣仁為了確保考慮動作層的耐壓及電阻之最適當厚度 ^㈣=,而=大約3 5 0 0入的η型,晶層2施刻到成為25〇〇 於此日守的蝕刻係濕式蝕刻,因此除了時間和溫度, ,且蝕刻液内的晶圓振蘯幅[振動速度等控制都非常困 f之外’並要求將姓刻液在所定鮮度保持時間内使用。因 叙从广Γ从t 曰智生不均,而有非常難以謀求 動作區域犄性之重現性及提昇高頻特性之問題。V. INSTRUCTION OF THE INVENTION (7) _ : Pushing is formed in the opening. However, since the film quality of the polyimide layer 30 and the imide layer 30 of the photoresist does not form a serious unevenness of 30 to 45 degrees = unevenness, the push angle is combined with the region 31a and the ohmic The spacing of the electrodes 28 from the Schottky junction of the 'action zone is ensured to be approximately 7 // m. However, since the respective contacts are required to have resistance in consideration of pushing, the large separation distance hinders the distance between the two to contribute to the fact that the series is not progressing in miniaturization of the wafer. The improvement of the characteristics of the 鬲^ member is also the third. Since the Schottky junction and thus the action of the Schottky barrier diode s are pushed and pulled, the sniffering degree of the squeak also becomes The cause of interlayer insulation. The fourth increase is due to the use of polyimine as the acoustic Au as the wiring and electrode output of the 曰0, ,,, or the plating. However, it is a high cost that cannot be reduced. Therefore, the wafers of the AS substrate and the Ω+ type stray layer and the η type stupid layer are inherited, and thus there is a problem that the cost is hindered. Moreover, according to the conventional manufacturing method, there are the following problems. 23 Shaw #特基接接接接介基基在第一上层_ Epitaxial layer (四)仁 In order to ensure the most appropriate thickness of the operating layer withstand voltage and resistance ^ (4) =, and = about 3 5 0 0 into the η Type, the crystal layer 2 is engraved into the etched wet etching of 25 〇〇, so in addition to time and temperature, and the wafer vibrating amplitude in the etching liquid [vibration speed and other controls are very difficult Outside' and require the surname to be used for the specified freshness retention time. Because of the inconsistency of the Γ 从 from the vast ,, it is very difficult to seek the reproducibility of the action area and the high frequency characteristics.
第16頁 III·· 1267193 , Q ( _案號91116690 年?月5曰 修正_ 五、發明說明(8) 第2,依據採用平台構造的方式,必須用步驟數很多 的平台餘刻,會因為光阻劑和氧化膜之密接性不均而發生 不良狀況。且,必須同時具有當作層間絕緣膜之聚醯亞胺 層形成步驟,和在聚醯亞胺層上方設電極之輸出的鍍Au形 成步驟等,會有製造流程複雜化,時間性效率不佳之問 題。 由於化合物半導體該基板本身的價格高,為了合理 化’必須縮小晶片尺寸抑制成本。即,減少晶片尺寸為不 可避免,且希望削減材料本身的成本。同時亦要求進一步 改善高頻特性。此外,謀求製造步驟簡化和效率化亦為重 要課題。 [發明内容] 本發明係鑑於相關問題而研發者,其特徵為,具備化 合物半導體基板、設在基板上方的一種導電型離子植入區 域、設成鄰接在離子植入區域的一種導電型高濃度離子植 入區域、和高濃度離子植入區域形成歐姆接合的第1電 極、和離子植入區域形成肖特基接合的第2電極和當作第1 及第2電極之輸出的金屬層,藉由在設在基板表面的高濃 度離子植入區域表面設歐姆電極的方式,實現化合物半導 體之平面型肖特基屏障二極體,亦可減少動作部分之面 積。且因為可用離子植入形成全部動作區域,因此亦可大 幅地削減晶圓本身的成本,而可實現削減肖特基屏障二極 體之成本。而藉由減少寄生容量及電阻的方式,可有助於 提昇高頻特性。 且,本發明提供一種肖特基屏障二極體之製造方法,Page 16 III·· 1267193, Q ( _ Case No. 91116690? Month 5曰 Amendment _ V. Invention Description (8) No. 2, according to the platform construction method, it is necessary to use a lot of steps for the platform, because The adhesion between the photoresist and the oxide film is uneven and a problem occurs. Moreover, it is necessary to simultaneously have a polyimine layer forming step as an interlayer insulating film, and a Au plating having an output of an electrode above the polyimide layer. In the formation step, etc., there is a problem that the manufacturing process is complicated and the time efficiency is not good. Since the price of the compound semiconductor itself is high, in order to rationalize, it is necessary to reduce the size of the wafer to suppress the cost. That is, reducing the wafer size is unavoidable, and it is desired to reduce it. The cost of the material itself is also required to further improve the high-frequency characteristics. In addition, the simplification and efficiency of the manufacturing process are also important issues. [Invention] The present invention has been made in view of the related problems, and is characterized in that it has a compound semiconductor substrate. a conductive ion implantation region disposed above the substrate, and a conductive type high concentration adjacent to the ion implantation region The first ion-implanted region and the high-concentration ion implantation region form an ohmic junction first electrode, and the ion implantation region forms a Schottky-bonded second electrode and a metal layer serving as an output of the first and second electrodes. By providing an ohmic electrode on the surface of the high-concentration ion implantation region provided on the surface of the substrate, a planar Schottky barrier diode of the compound semiconductor can be realized, and the area of the action portion can also be reduced. Since all the operating regions can greatly reduce the cost of the wafer itself, the cost of the Schottky barrier diode can be reduced, and the high frequency characteristics can be improved by reducing the parasitic capacitance and the resistance. Moreover, the present invention provides a method of manufacturing a Schottky barrier diode,
3]3892.ptc 第17頁 12671933]3892.ptc Page 17 1267193
系观 3111b⑽UDepartment view 3111b(10)U
五、發明說明(9) 實現簡化及效率化的製造步驟,並古 徵為,具備在平坦的化合物半 =呵頒特性,其特 型離子植入區·,且形成鄰::;表面形成-種導電 型高濃度離子植入區域之步 匕種導電 面形成歐姆接合的第丨電極之步 If度離子植入區域表 表面形成肖特基接合的第2電極之步驟成 電極及第2電極接觸的金屬層之牛 7成刀別和第i [實施方式] 曰厂、 ^照第i圖至第8圖,詳細地表示本發明之 本發明之肖特基屏障二極雜 、❿1悲。 雜工^ t _ 早—極肢1 ’具備化合物半導俨1、 恭桎1 1 ΐ 3、南濃度離子植人區域7、第1電極8、第2 私極11和金屬層1 4、1 5。 0 ^ 2 第1圖表示動作區域部分之剖視圖' 不形成平台 形 化合物半導體丨為無參雜GaAS基板, 成平坦的基板構造。 -二子植入區'或3為子植入區土或,設在圓形肖特美 包極11下方的半導體基板1表 合 角特基 之動作區域。 表面田作為特基屏障二極體 Α Λ Γ〉辰度離子植入區域7在歐姆電極8下方的基板表面裝 和離子植入區域3鄰接。設成沿著圓形的肖特基電極 周’和歐姆電極8大致重疊,至少在包圍肖特基電極 +的。Ρ分,设成超出歐姆電極8。肖特基電極1 1和高濃度 离^ :植入區域7的間隔距離為1" m。即,以仍然保持平面 才、造的方式形成在表面設高濃度離子植入區域7之構造, 代替習知之採用平台構造,可實現不設置平台之歐姆接V. Description of the invention (9) The manufacturing steps to achieve simplification and efficiency, and the ancient levy, with a flat compound half-characteristic characteristic, its special ion implantation zone, and forming a neighbor::; surface formation - Step of the conductive high-concentration ion implantation region, the conductive surface forming the ohmic junction of the second electrode, and the step of forming the Schottky-bonded second electrode on the surface of the ion implantation region, the step of forming the electrode and the second electrode The metal layer of the cow is 7% and the first embodiment [Embodiment] The factory, according to the first to eighth figures, shows the Schottky barrier of the present invention in detail. Handyman ^ t _ early - polar limb 1 'has compound semi-conducting 俨 1, gong 桎 1 1 ΐ 3, south concentration ion implanted area 7, first electrode 8, second private pole 11 and metal layer 1 4, 1 5 . 0 ^ 2 Fig. 1 shows a cross-sectional view of the portion of the action region. 'The plateau is not formed. The compound semiconductor is a non-doped GaAS substrate and has a flat substrate structure. - The two sub-implantation zone ' or 3 is a sub-implantation zone or the semiconductor substrate 1 disposed under the circular Schottme package pole 11 is an action region of the corner group. The surface field serves as a special barrier diode. The ion implantation region 7 is adjacent to the ion implantation region 3 on the surface of the substrate below the ohmic electrode 8. It is disposed so as to substantially overlap the ohmic electrode 8 along the circular Schottky electrode circumference, at least surrounding the Schottky electrode +. The enthalpy is set to exceed the ohmic electrode 8. The Schottky electrode 1 1 and the high concentration are: the implantation distance of the implanted region 7 is 1 " m. That is, the structure in which the high-concentration ion implantation region 7 is formed on the surface is formed in such a manner as to maintain the plane, and instead of the conventional platform structure, the ohmic connection without the platform can be realized.
第18頁 案號 1267193 修正 、發明說明(ίο) 五 合。 離子i 姆電極8係第1層金屬層,接觸在高濃度 離子植 £或7。順序澱積AuGe/Ni/Au,且將肖特x接人 附近形成挖空成圓形形& t R安。$ % #且將A特基接合 之間隔距離為Μ 和鄰接的肖特基電極Η ♦面^電化極膜之基電極11係第2層金屬層,在覆蓋Us 表面勺虱匕馭^又为特基接觸孔,且 形成直徑10// _圓來图安0 ^ ^斤叔積Ti/Pt/Au, 某接入。者I ^圖案,且形成和離子植入區域3肖特 暴接口 田做動作區域之齙;始λ p a。 置,用於獲得耐壓等所定::植”域3以最適當條件設 美带極1 1开彡占4 A 4所特由於以氮化膜覆蓋至肖特 2接合。 則,因此可獲得高品質、高精確度之肖特 極15ΐ 層陽,具備形成陽極電極14及陰極電 觸,延伸至陽極焊接£域开電/'14和肖特基電極11接 化膜5和歐姆電極8=二成陽極焊塾“a。且介以氮 P+ Μ入「/戈陰電t ^離子植入區域3及高濃 度離子植入區域7絕緣。陽炻抨 辰Page 18 Case No. 1267193 Amendment, invention description (ίο) Wuhe. The ion i electrode 8 is the first metal layer that is contacted at a high concentration of ions or at a pH of 7. The AuGe/Ni/Au is sequentially deposited, and the Schott x is joined to form a hollow shape into a circular shape & t R amp. $ % # and the distance between the joints of the A and the base is Μ and the adjacent Schottky electrode ♦ ♦ the surface of the base electrode of the galvanic electrode film is the second metal layer, which is covered by the surface of the Us surface. The special base contacts the hole, and forms a diameter of 10 / / _ circle to map 0 ^ ^ kg unpredictable Ti / Pt / Au, some access. I ^ pattern, and the formation and ion implantation area 3 Schott storm interface field to do the action area; start λ p a. Set, for obtaining the pressure resistance, etc.:: Planting field 3 is set to the most suitable condition. The band is 1 1 opening 彡 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 High-quality, high-precision Schottky 15ΐ layered anode with anode electrode 14 and cathode electrical contact, extending to the anode soldering field / '14 and Schottky electrode 11 bonding film 5 and ohmic electrode 8 = 20% anodized 塾 "a. And through the nitrogen P + into the " / Ge Yin electric t ^ ion implantation area 3 and high concentration ion implantation area 7 insulation. Yangshuo Chen
GaAs基板!為半絕缘,ί,墊14f接固設在基板1。 芙柄而不^ / 此可將連線焊接部直接固設在 基板而不頊裝設聚醯亞胺及氮化膜。 隹 縮陰H極15係設成和陽極電極14相對,且和歐姆電極 極麵ϋ圖^第3圖表示本發明化合物半導體肖特基屏障二 。-冑現圖。第2圖為晶片圖案之概略圖,第3圖為動;GaAs substrate! For the semi-insulating, ί, the pad 14f is fixed to the substrate 1. The handle is not fixed. / This allows the wire soldering portion to be directly attached to the substrate without the polyimine and nitride film. The 缩-negative H-pole 15 is disposed opposite to the anode electrode 14 and to the ohmic electrode. Fig. 3 shows the compound semiconductor Schottky barrier 2 of the present invention. -胄图. Figure 2 is a schematic diagram of a wafer pattern, and Figure 3 is a motion;
313892.ptc 第19頁 極8接觸的高濃产離子拮A成陰極^塾15a。歐姆電 極焊塾域7形成陰極電位_。陰 丁斤 』置接囡5又在+絕緣性基板1。313892.ptc Page 19 The high concentration of ions in the contact of the pole 8 is a cathode. The ohmic electrode pad field 7 forms a cathode potential _. The yin jin is placed on the 绝缘5 and on the + insulating substrate 1.
1267193 曰 〜修正 五、發明說明(12) ^ 少高頻特性參數之感應件成分,有助於接曰二 如第3圖所示,陽極+托立y 、铋汁南頻特性。 味極電極和形成陰極 叉部分,僅斜線表示之區域,位的GaAs之交 立妒習知之·ηηπ ^ 刀面積為大約100// m。 其車乂白夫之1 3 0 0“时縮小至大約工/ j 3, m 膜5代替層間絕緣膜之聚醯亞胺。 口此可用溥乳化 本毛明之特彳政為設高濃度離子植入區域7,且 肖特基電極11及歐姆電極8設在GaAs表面的方式,^現字 特基屏P早二極體之平面構造。由於不須考庹平a开> 狀肖 均造成的偏離,因此可大幅地減少肖特基 極8的間隔距離。且,陽極電極1 4及陰極蕾把^ > 电 ,, 电極下方該大郁 分為半絕緣性GaAs基板1。即,形成陰極番a r λ 1 _ _ ι位的GaAs和陽 極電極14父叉部分的面積為大約100// 與習知1267193 曰 ~ Amendment 5, invention description (12) ^ Less high-frequency characteristic parameters of the sensing component, help to connect the second, as shown in Figure 3, anode + erection y, 铋 juice south frequency characteristics. The taste electrode and the portion forming the cathode fork, only the area indicated by the oblique line, the intersection of the GaAs of the position, the conventional ηηπ ^ knife area is about 100 / / m. Its car 乂白夫1 1 0 0 "when it is reduced to about work / j 3, m film 5 replaces the interlayer insulating film of polyimine. This can be used for emulsification of this hairy special 彳 为 for the high concentration ion implant Into the region 7, and the Schottky electrode 11 and the ohmic electrode 8 are arranged on the surface of the GaAs, and the planar structure of the early second pole body of the P-type screen P is not required to be considered as a flat opening. The deviation of the Schottky pole 8 can be greatly reduced, and the anode electrode 14 and the cathode bud are electrically divided, and the underlying electrode is divided into a semi-insulating GaAs substrate 1. That is, The area of the parent yoke portion of the GaAs and anode electrode 14 forming the cathode ar λ 1 _ _ ι is about 100 / / and conventional
成1 / 1 3之面積。藉由將聚醯亞胺厚度(間 乂 ’ I 式,由於不須抑制寄生容量,因此可用1距離+ )加大的方 亞胺層,亦不須考慮聚醯亞胺之推拔部分氣化膜代替聚酿 因此,具體而言,肖特基接合區域 距離可從M ra減少至2# m。此外,和it &姆電極的間隔 7的間隔距離為1 // m,此時高濃度離早又 植入區域 移動路徑,具有和歐姆電極8大致同樣的效果,因此子之 知之間隔距離可減少至丨/7。肖特基電極n及歐姆 間隔距離有助於串聯電阻,因此若能 包極8白、、 丄,+ 右此&小間隔距離則争η 減少電阻,可對提昇高頻特性極有幫助。 則更3 因此,有助於晶片小裂化,晶片尺; 0. 31_乏尺寸,但可縮小至〇. 25x 〇 25mra 3 配設焊墊之必要性,和組裝時可操作 田於有 _ 4日日片尺寸有限制, 1267193 Ati, f η c 案號 91116690 _年 7 _ 一--—---- 五、發明說明(13) 因此0 · 2 5mm角為現狀之限制’但因為動作區域可 小至大約1 / 1 0,因此如後述,配設動作區域之I ^地縮 曰田度變得 非常大。 依據本發明,由於在無參雜GaAs基板藉由離子植入裝 設動作區域,因此比裝設有磊晶層的習知構造之晶圓,可 大鴨地減少晶圓成本。 第4圖為本發明之第2實施型態,表示裝設有多數個形 成肖特基電極之肖特基接合區域。 本發明之構造中,亦可裝設多數個肖特基電極1 1。例 如,若依據圖中之配設,宵特基電極11係並列地連接,可 有助於減少電阻。 如果將肖特基接觸孔徑縮小且配設多數個,比用相同 的肖特基接觸孔總面積配設1個時,更可減少肖特基接觸 孔中心和高濃度離子植入區域7的間隔距離,高濃度離子 $入區域7之載子捕集會更有效。因此,具有陰極電阻值 可進一步提高高頻特性之優點。 制 第5圖至第8圖詳細地表示本發明肖特基屏障二極體之 衣造方法。 久 肖特基屏障二極體具備在平坦的無參雜化合物半導體 务2反表面形成一種導電型離子植入區域,且在預定的第1 電I方’在和離子植入區域鄰接的基板表面形成一種導 ί ^ ^濃度離子植入區域之步驟;在高濃度離子植入區域 ^ 形成歐姆接合的第1電極之步驟;形成被第1電極包圍 之;/且和離子植入區域表面形成肖特基接合的第2電極 驟’和形成分別和第1電極及第2電極接觸的金屬層之 1267193 修正 _案號 91116690 五、發明說明(14) 步驟。 如第5圖所示,本發明之第1步驟係,在平坦的無參雜 化合物半導體基板1表面形成一種導電型離子植入區域3, 且在和離子植入區域3鄰接的基板表面1形成一種導電型高 濃度離子植入區域7。 本步驟係成為本發明特徵之步驟,形成當作動作區域 之η形離子植入區域3 ’且在形成預定的歐姆電極8的區域 下方之基板表面,形成高濃度離子植入區域7。 即,在無參雜GaAs基板1以氮化膜5被覆全面,再將裝 設有抗蝕層且當作動作區域之預定的η型離子植入區域3所 形成的區域上方之抗蝕層,進行選擇性開窗之光蝕刻法。 然後,用該抗蝕層當作遮罩,將η型雜質(S i +,大約1. 3χ 1 0 Am _3)離子植入,在預定的肖特基電極下方之基板1表 面,形成η型離子植入區域3。此時,由於η型離子植入區 域3成為肖特基屏障二極體之動作區域,因此以動作區域 可獲得最適當特性之濃度狀態的條件離子植入。 除去抗蝕劑後,進一步將形成預定的高濃度離子植入 區域7的區域上方之抗蝕層,進行選擇性開窗之光蝕刻 法。然後,用該抗蝕層當作遮罩,將高濃度η型雜質 (S i +,大約1. 3χ 1 0 Am,離子植入,在預定的歐姆電極8 下方之基板1表面,形成高濃度離子植入區域7。且,一部 分重疊鄰接區域,形成和η型離子植入區域3沒有間隔部 分0 然後除去抗蝕層,為了退火用而再次澱積氮化膜5, 施行η型離子植入區域3及高濃度離子植入區域7之活性化Into the area of 1 / 1 3 . By increasing the thickness of the polyimine (intermediate 乂' I type, because there is no need to suppress the parasitic capacity, the distance of 1 by +) can be increased, and the partial vaporization of the polyimine is not considered. The film replaces the brewing. Thus, in particular, the Schottky junction area distance can be reduced from λ to 2#m. In addition, the distance between the gaps of the it&m electrodes is 1 // m. At this time, the high concentration is implanted in the region moving path earlier, and has substantially the same effect as the ohmic electrode 8, so that the distance between the sub-electrodes can be Reduce to 丨/7. The Schottky electrode n and the ohmic separation distance contribute to the series resistance. Therefore, if the package is 8 white, 丄, + right, this small spacing distance is used to reduce the resistance, which is very helpful for improving the high frequency characteristics. Then more 3, therefore, help the chip to crack small, wafer ruler; 0. 31_ lack of size, but can be reduced to 〇. 25x 〇 25mra 3 need to be equipped with solder pads, and can be manipulated when assembled _ 4 The size of the daily film is limited, 1267193 Ati, f η c Case number 91116690 _ year 7 _ I------- V. Invention description (13) Therefore 0 · 2 5mm angle is the limit of the status quo 'But because of the action area It can be as small as about 1 / 1 0. Therefore, as will be described later, the I ^ ground reduction degree in which the operation region is disposed becomes extremely large. According to the present invention, since the operation region is provided by ion implantation on the non-doped GaAs substrate, the wafer cost can be reduced by the wafers of the conventional structure in which the epitaxial layer is mounted. Fig. 4 is a view showing a second embodiment of the present invention, showing a plurality of Schottky junction regions in which a Schottky electrode is formed. In the structure of the present invention, a plurality of Schottky electrodes 11 may be mounted. For example, according to the arrangement in the figure, the 宵-based electrodes 11 are connected in parallel to help reduce the electric resistance. If the Schottky contact aperture is reduced and a plurality of holes are provided, the spacing between the center of the Schottky contact hole and the high-concentration ion implantation region 7 can be further reduced when the total area of the same Schottky contact hole is set to one. Distance, high concentration ion into zone 7 carrier trapping will be more effective. Therefore, having a cathode resistance value can further improve the advantages of high frequency characteristics. The fifth to eighth drawings show in detail the method of making the Schottky barrier diode of the present invention. The long Schottky barrier diode has a conductive ion implantation region formed on the flat surface of the undoped compound semiconductor 2, and the substrate surface adjacent to the ion implantation region at a predetermined first electric region Forming a step of depositing a concentration ion implantation region; forming a first electrode of the ohmic junction in the high concentration ion implantation region; forming a surface surrounded by the first electrode; and forming a surface with the ion implantation region The second electrode step 't jointed with the second base and the metal layer formed to be in contact with the first electrode and the second electrode, respectively, 1267193 _____________________________________________________________________________________________________________________________________________________________ As shown in Fig. 5, in the first step of the present invention, a conductive type ion implantation region 3 is formed on the surface of the flat non-doped compound semiconductor substrate 1, and is formed on the substrate surface 1 adjacent to the ion implantation region 3. A conductive high concentration ion implantation region 7. This step is a step of the feature of the present invention, forming an n-type ion implantation region 3' as an action region and forming a high concentration ion implantation region 7 on the surface of the substrate below the region where the predetermined ohmic electrode 8 is formed. In other words, the non-doped GaAs substrate 1 is covered with the nitride film 5, and the resist layer is formed over the region formed by the predetermined n-type ion implantation region 3 in which the resist layer is provided as the operation region. A photolithography method for selective windowing is performed. Then, the resist layer is used as a mask, and an n-type impurity (S i +, about 1.3 χ 1 0 Am _3) is ion-implanted to form an n-type on the surface of the substrate 1 under the predetermined Schottky electrode. Ion implantation region 3. At this time, since the n-type ion implantation region 3 becomes an operation region of the Schottky barrier diode, conditional ion implantation in the concentration state of the most appropriate characteristics can be obtained in the operation region. After the resist is removed, a resist layer over a region of a predetermined high concentration ion implantation region 7 is further formed, and a photo-etching method of selective windowing is performed. Then, using the resist layer as a mask, a high concentration of n-type impurity (S i +, about 1.3 μm, implanted, ion implanted on the surface of the substrate 1 below the predetermined ohmic electrode 8 to form a high concentration The ion implantation region 7. Moreover, a portion overlaps the adjacent region, and the n-type ion implantation region 3 is formed without a spacer portion 0, and then the resist layer is removed, and the nitride film 5 is deposited again for annealing, and the n-type ion implantation is performed. Activation of Zone 3 and High Concentration Ion Implantation Zone 7
313892.ptc 第23頁 1267193 案號 91116690 修正 五、發明說明(15) 退火。 因此,在當作動作區域之預定的肖特基電極1 1下方, 形成η型離子植入區域3,且在預定的歐姆電極8下方,形 成高濃度離子植入區域7。其後之步驟中,藉由在η型離子 植入區域3表面裝設肖特基電極1 1,在高濃度離子植入區 域7表面設歐姆電極8的方式,實現平面構造之肖特基屏障 二極體。因此,肖特基接合區域,和與歐姆電極進行相同 動作的高濃度離子植入區域之間隔距離,可大幅地減少, 形成一種可減少串聯電阻,極有助於提昇高頻特性之肖特 基屏障二極體。 如第6圖所示,本發明之第2步驟係在高濃度離子植入 區域7表面形成歐姆接合的第1電極8。 全面形成抗蝕層,且將形成預定的歐姆電極8部分, 進行選擇性開窗之光蝕刻法。除去從抗蝕層露出的氮化膜 5,將第1層金屬層之AuGe/Ni/Au三層,順序殿積且積層。 然後,藉由剝離除去抗蝕層,在預定的歐姆電極8部分留 下第1層金屬層。接著藉由合金化熱處理,在高濃度離子 植入區域7表面形成歐姆電極8。 如第7圖所示,本發明之第3步驟係形成第2電極11, 被第1電極8包圍外周,且和離子植入區域3表面形成肖特 基接合。 本步驟係成為本發明特徵之步驟,首先,第7圖(A) 中,將抗蝕層PR形成在全面,且將預定的肖特基電極1 1部 分,進行選擇性開窗之光蝕刻法。將露出的氮化膜5乾式 蝕刻,形成露出離子植入區域3的肖特基接觸孔9。313892.ptc Page 23 1267193 Case No. 91116690 Amendment V. Description of invention (15) Annealing. Therefore, under the predetermined Schottky electrode 1 1 as the action region, the n-type ion implantation region 3 is formed, and below the predetermined ohmic electrode 8, a high concentration ion implantation region 7 is formed. In the subsequent step, by providing the Schottky electrode 11 on the surface of the n-type ion implantation region 3, the ohmic electrode 8 is disposed on the surface of the high-concentration ion implantation region 7, thereby realizing the Schottky barrier of the planar structure. Diode. Therefore, the distance between the Schottky junction region and the high-concentration ion implantation region that performs the same operation as the ohmic electrode can be greatly reduced, and a Schottky which can reduce the series resistance and contribute to the improvement of the high-frequency characteristics can be formed. Barrier diode. As shown in Fig. 6, the second step of the present invention forms the first electrode 8 which is ohmically bonded to the surface of the high-concentration ion implantation region 7. A resist layer is formed in its entirety, and a predetermined portion of the ohmic electrode 8 is formed, and a photo-etching method of selective windowing is performed. The nitride film 5 exposed from the resist layer is removed, and the AuGe/Ni/Au three layers of the first metal layer are sequentially stacked and laminated. Then, the resist layer is removed by lift-off, and the first metal layer is left in the predetermined ohmic electrode portion 8. Then, an ohmic electrode 8 is formed on the surface of the high concentration ion implantation region 7 by alloying heat treatment. As shown in Fig. 7, in the third step of the present invention, the second electrode 11 is formed, the outer periphery of the first electrode 8 is surrounded, and the Schottky junction is formed on the surface of the ion implantation region 3. This step is a step of the features of the present invention. First, in FIG. 7(A), the resist layer PR is formed in a comprehensive manner, and a predetermined portion of the Schottky electrode 11 is selectively fenestrated by photolithography. . The exposed nitride film 5 is dry etched to form a Schottky contact hole 9 exposing the ion implantation region 3.
313892.ptc 第24頁 1267193 月 9111RR〇n 修正 五、發明說明(16) 然7圖⑻所示,將第2層金屬層之Μ — :f ’依序真工澱積且積層在全面、然後,藉由剝離除去 Ϊ : = ί離子植入區域3表面形成肖特基接合,當作 土特基電極n。GaAs表面以氮化膜覆蓋至形成“寺基田接作 。,可在GaAs表面良好的狀態形成肖特基接合。、土 的曰】:Ϊ ^ Ϊ方法中’除了時間和溫度,甚且蝕刻液内 要Ϊ將蝕ΐ : ί 盪速度等精密控制非常困難之外,並 :::鮮度保持時間内使用。但,依據本發 子植乂區城t S以動作區域最適當的條件形成η型離 ρ ^ ιιs p可省略習知必要的,用於控制動作声厚 ί之=的姓刻步驟,因此可形成重現性良好的肖“接 二出特:安定的㈣基屏障二極體= 15’分別接觸在第i電極8及第2電極n。 ^成至屬層14、 緣膜ί ί : 1成為本發明特徵之步驟,首先,將當作層、 ί 土的氮化膜5再次澱積在全面。形成抗: 焊塾15a部分,進行選擇性開窗之光二Γ s 、 膜5餘刻。除去抗蝕劑後,進一步設新的γ飩 層,將所要的陽極電極14、 性開窗之光蝕刘♦。扭τ · / 圖案,進行選擇 離形成陽極電㉟i 4及險極.二順序歲積在全面’藉由剝 成之:極電極“及陰極電極15係以-般的剝離法形 缘膜^ 屬。此外,陽極電極U及陰極電極15之層間絕 緣膜為鼠化膜5,由於焊塾部亦可直接固設在基板,曰因門此巴 案號 jjll6690 ^ j 1___月 ^ Ά. 修正 1267193 五、發明說明(17) 可省略聚醯亞胺層。因此,町省略習知在聚醯亞胺層上 方,為了吸收聚醯亞胺之不良情況而設的配線及焊墊形成 之鍍Au步驟。若能省略進行數次鍍膜之聚醯亞胺層形成步 驟及鍵A u步驟,則能簡化製造流程,有效地製造肖特基屏 障二極體。 化合物半導體肖特基屏障二極體完成前段步驟時,即 轉移至進行組裝的後段步驟。將晶圓形半導體晶片切割, 且分割成個別的半導體晶片,將該半導體晶片固設在框架 (不圖示)後,以焊接線將半導體晶片之焊墊1 4a、1 5a和所 定導線(不圖示)連接。使用金屬細線當作焊接線,以眾所 週知之針腳式接合(stitch bonding)連接。然後,施行傳 遞模塑法(transfer molding)之樹脂包封。 [發明之功效] 依據本發明之構造可獲得以下所不各種效果。 第1,藉由在GaA s表面設高濃度離子植入區域7,且將 肖特基電極1 1及歐姆電極8設在GaAs表面的方式,可實現 肖特基屏障二極體之平面構造。由於可抑制平台的不均造 成歐姆電極形狀不均和特性惡化,而不須考慮偏離,因此 可大幅地減少肖特基電極1 1和歐姆電極8的間隔距離。且 肖特基電極1 1及歐姆電極8的間隔距離有助於串聯電阻, 因此愈縮小間隔距離,愈可減少電阻。 第2,陰極電位之GaAs和陽極電極1 4交叉部分的面積 為大約1 0 0 // m 2,寄生容量大幅地降低。此係陽極電極1 4下 方大部分區域設有絕緣化區域6,因此使發生寄生容量之 交叉部面積,與習知比較,僅肖特基接合部分即可減少至313892.ptc Page 24 1267193 Month 9111RR〇n Amendment 5, Invention Description (16) However, as shown in Figure 8 (8), the second layer of metal layer : - : f ' is actually deposited and laminated in a comprehensive manner, then By removing the Ϊ : = ί ion implantation region 3 surface to form a Schottky junction, as a soil-based electrode n. The surface of GaAs is covered with a nitride film to form "Temple Foundation. It can form a Schottky junction in a good state on the surface of the GaAs. 土 Ϊ Ϊ Ϊ Ϊ ' ' ' ' ' ' ' 除了 除了 除了 除了 除了 除了 除了 除了 除了 除了 除了 除了 除了 除了 除了It is very difficult to control the inside of the liquid: ί 速度 等 等 等 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The type ρ ^ ιιs p can omit the necessary engraving steps for controlling the thickness of the action sound, so that a reproducible Shaw can be formed: the stable (four) base barrier diode = 15' is in contact with the i-th electrode 8 and the second electrode n, respectively. The formation of the layer 14 and the film ί ί : 1 is a step of the feature of the present invention. First, the nitride film 5 as a layer and a layer is again deposited in a comprehensive manner. Formation resistance: Part 15a of the soldering iron, selective light-emitting window Γ, film 5 for more than a moment. After the resist is removed, a new γ layer is further provided, and the desired anode electrode 14 and the open window are etched. Twist τ · / pattern, select to form the anode electricity 35i 4 and the dangerous pole. The second order is accumulated in the whole 'by stripping: the pole electrode' and the cathode electrode 15 are based on the general peeling method In addition, the interlayer insulating film of the anode electrode U and the cathode electrode 15 is a mouse film 5, and the soldering portion can be directly fixed on the substrate, and the door is in the case of jjll6690^j1___month^ Ά. Amendment 1267193 V. DESCRIPTION OF THE INVENTION (17) The polyimine layer can be omitted. Therefore, the Au plating step of wiring and pad formation for absorbing the defects of polyimine is known. If the polyimine layer formation step and the key Au step for performing several coatings can be omitted, the manufacturing process can be simplified, and the Schottky barrier diode can be efficiently fabricated. The compound semiconductor Schottky barrier diode completes the front stage. In the step, the process is transferred to the subsequent step of assembling. The wafer-shaped semiconductor wafer is cut and divided into individual semiconductor wafers, and after the semiconductor wafer is fixed on a frame (not shown), the semiconductor wafer is soldered. Solder pads 1 4a, 15a and A wire (not shown) is connected. A metal wire is used as a bonding wire, and a well-known stitch bonding connection is used. Then, a resin molding of transfer molding is performed. [Effect of the invention] According to the configuration of the present invention, the following various effects can be obtained. First, by providing a high-concentration ion implantation region 7 on the surface of the GaA s and providing the Schottky electrode 11 and the ohmic electrode 8 on the GaAs surface, The planar structure of the Schottky barrier diode can be realized. Since the unevenness of the ohmic electrode shape and the deterioration of the characteristics can be suppressed by suppressing the unevenness of the platform, the Schottky electrode 11 and the ohmic electrode can be greatly reduced. The separation distance of 8 and the spacing distance between the Schottky electrode 11 and the ohmic electrode 8 contribute to the series resistance, so that the smaller the separation distance, the more the resistance can be reduced. Second, the cathode potential GaAs and the anode electrode 14 intersection portion The area is about 10 // m 2 , and the parasitic capacitance is greatly reduced. This is the region where most of the anode electrode 14 is provided with an insulating region 6, so that the intersection of parasitic capacitance occurs. Area, compared with conventional, only the Schottky junction portion can be reduced to
111^· 3]3892.ptc 第26頁 _SS_91116690111^· 3]3892.ptc Page 26 _SS_91116690
1267193 五、發明說明(18) 1/13。且因為陽極焊墊14 a亦可直接固a 部分不會發生寄生容量,可大幅地減少GaAs,因此兮 知,採用低介電常數的聚醯亞胺設厚岸二寄生容量。、 制寄生容量,但可用薄氮化膜代替。^ =絕緣膜,用以 介電常數高,但依據本發明之構造,&祺比聚醯亞 p 化膜仍可比習知之寄生容量減少。 大約5〇〇〇a的!1 第3,由於不採用厚聚醯亞胺,因 氣 均 區域的聚醯亞胺開口部之推拔部分距離亦不須考慮動 ·, ,和推拔角度不乍 依據以上所述,肖特基電極和歐姆♦ 單純地考慮耐壓和遮罩重合精確度即可二極的間隔钜離 基接合區域和歐姆電極的間隔距離具體而言,堇 此外,和高濃度離子植入區域7的間隔成^成7/Z岐2/特 高濃度離子植入區域7為載子之移動路彳①雖為k „,此^ 極8有相同效果,因此可比習知之間隔ς離^致和歐姆^ 此,電阻大幅地減少、寄生容量大幅地離减少至丨/匕 均減^,可極有助於提昇高頻特性。 夕及寄生容量 第4,有助於晶片小型化,晶片尺 不 • 3 1 mm乏尺寸,但可縮小到〇 . 2 & 〇 -習知之〇 · 2 慮配设烊墊之必要性,和組裝時可操作曰。尺寸由於 因此0· 25mm角為現狀中之限制,伸因Λ ^曰曰片尺寸限制 縮小至大約1/1〇,因此配設動作區域:大L 第5,由於可在GaAs基板藉由離子植入形H件後大。 域,而不必裝設磊晶層,有助於減低成本。具體作^區 習知之晶圓在無參雜GaA_板裝設^型磊晶層=比 1267193 案號 91Π6690 乜年1月《曰 修正 五、發明說明(19) 層,可實現無參雜GaAs之晶圓,因此晶圓價格可大幅地減 少成1 / 4至1 / 5。 第6,藉由裝設多數個形成肖特基電極的肖特基接合 部,可進一步減低電阻。若將肖特基接合部的接觸徑縮小 且裝設多數個,比裝設1個肖特基接觸總面積相同的肖特 基電極時,更可降低電阻,有效地進行高濃度離子植入區 域之載子捕集,因此具有更提昇高頻特性之優點。 第7,由於不使用聚醯亞胺層和鍍金,除了可減少材 料費之外,尚可縮小晶片,實現減少成本。 依據本發明之製造方法,可獲得以下所示效果。 第1,由於可形成安定的肖特基接合,而可抑制對高 頻電路非常重要的問題之特性不均。如果用氮化膜覆蓋η 型離子植入區域至形成肖特基接合之前,再將氮化膜蝕刻 並澱積T i /P t / Au,即可在完全無污染的結晶面肖特基接 合,獲得高品質、高精確度之肖特基接合。而且,η型離 子植入區域形成當作動作區域之最適當濃度狀態,不要如 習知之複雜的GaAs餘刻控制。即,可製造出良品率提高、 重現性良好、具有安定特性的肖特基屏障二極體。 第2,上述肖特基屏障二極體之製造效率良好,並可 實現簡化的製造步驟。具體而言,即平台蝕刻步驟、肖特 基接合形成前的η型磊晶層蝕刻步驟、聚醯亞胺層形成步 驟、鍍Αιι步驟等。為了使聚醯亞胺層形成6至7# m厚度, 須反覆數次鍍膜形成。而將聚醯亞胺層數次鍍膜,既費時 且製造流程複雜。而且,若不要聚醯亞胺,則亦不要鍍Au 層之電極。習知為了防止焊料安裝時的熱度和連線焊接時1267193 V. Description of invention (18) 1/13. Further, since the anode pad 14a can be directly fixed to a portion without parasitic capacitance, GaAs can be greatly reduced, and therefore, a low dielectric constant polyimine is used to provide a thick parasitic capacity. , Parasitic capacity, but can be replaced by a thin nitride film. ^ = Insulating film for high dielectric constant, but according to the configuration of the present invention, & 祺 醯 醯 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 。 。 。 。 。 。 。 。 About 5〇〇〇a! 1 No. 3, since the thick polyimine is not used, the distance of the push-out part of the opening of the polyimine in the gas-average region does not need to be considered, and the angle of pushing is not as described above. Base electrode and ohm ♦ simply consider the withstand voltage and mask overlay accuracy. The spacing between the two poles can be separated from the base joint region and the ohmic electrode. Specifically, in addition, the interval between the high concentration ion implantation region 7 and The formation of the 7/Z岐2/extra-concentration ion implantation region 7 is a moving path of the carrier, although k „, this electrode 8 has the same effect, so it can be separated from the conventional ohms and ohms ^ As a result, the resistance is greatly reduced, the parasitic capacitance is greatly reduced, and the 丨/匕 is reduced, which can greatly improve the high-frequency characteristics. The fourth and the parasitic capacity are fourth, which contributes to the miniaturization of the wafer, and the wafer size is not included. 1 mm is small, but it can be reduced to 〇. 2 & 〇-习知〇· 2 Consider the necessity of arranging the mattress, and it can be operated during assembly. The size is therefore limited by the current angle of 0·25mm. Stretching Λ ^The size limit of the film is reduced to about 1/1 inch, so the action area is set. Large L No. 5, because it can be implanted into the GaAs substrate by ion implantation of the H-shaped part, without having to install an epitaxial layer, which helps to reduce the cost. _ plate mounted ^ type epitaxial layer = than 1267193 case number 91 Π 6690 January 曰 "曰 五 、, invention description (19) layer, can achieve wafers without GaAs, so the wafer price can be greatly reduced 1 / 4 to 1 / 5. In the sixth aspect, by installing a plurality of Schottky junctions forming Schottky electrodes, the resistance can be further reduced. If the contact diameter of the Schottky junction is reduced, a large number of contacts are provided. When the Schottky electrode having the same total area of contact with one Schottky contact is installed, the electric resistance can be further reduced, and the carrier collection in the high-concentration ion implantation region can be efficiently performed, so that the high-frequency characteristics are further improved. In the seventh aspect, since the polyimine layer and the gold plating are not used, in addition to the reduction in the material cost, the wafer can be reduced and the cost can be reduced. According to the manufacturing method of the present invention, the following effects can be obtained. Forming a stable Schottky junction that inhibits high frequency circuits The characteristics of the often important problem are not uniform. If the n-type ion implantation region is covered with a nitride film until the Schottky junction is formed, the nitride film is etched and deposited with T i /P t / Au, which is complete. Non-polluting crystal face Schottky bonding for high-quality, high-accuracy Schottky bonding. Moreover, the n-type ion implantation region forms the most appropriate concentration state as the action region, and is not as complex as conventional GaAs. Incision control, that is, a Schottky barrier diode having improved yield, reproducibility, and stability characteristics can be manufactured. Second, the Schottky barrier diode described above is efficient in manufacturing and can be simplified. The manufacturing step, specifically, the stage etching step, the n-type epitaxial layer etching step before the Schottky junction formation, the polyimide layer forming step, the plating step, and the like. In order to form the polyimide layer to a thickness of 6 to 7 #m, it is necessary to form a coating several times. The coating of the polyimide layer several times is time consuming and complicated in the manufacturing process. Also, do not plate the electrode of the Au layer if it is not polyimide. In order to prevent heat during soldering and soldering during soldering
313892.ptc 第28頁 1267193 _案號 91116690 五、發明說明(20) 修正 的壓力造成電極中斷和變形而必須確保電極強度,藉由厚 鍍Au層形成陽極電極及陰極電極。但,若不要聚醯亞胺 層,則亦不必考慮該影響。即,不要鍍金電極,僅以 T i / P t / A u之澱積金屬即可形成陽極電極及陰極電極,並提 高可靠性。此外,由於引起習知之良品率低落的上述因素 消徐,因此亦將提高良品率。313892.ptc Page 28 1267193 _ Case No. 91116690 V. INSTRUCTIONS (20) The corrected pressure causes the electrode to be interrupted and deformed, and the strength of the electrode must be ensured. The anode electrode and the cathode electrode are formed by thick Au plating. However, if you do not want to concentrate on the imide layer, you do not have to consider this effect. That is, do not plate the gold electrode, and only the metal deposited by T i / P t / A u can form the anode electrode and the cathode electrode, and improve reliability. In addition, the above factors, which cause the low yield of the conventional products, will also increase the yield.
即,本發明之優點為,一方面係一種肖特基屏障二極 體,可大幅地減少寄生容量,進一步可降低電阻而大幅地 提昇高頻特性,一方面可提供謀求製造步驟簡化和效率化 之製造方法。That is, the present invention has an advantage that, on the one hand, it is a Schottky barrier diode, which can greatly reduce parasitic capacitance, further reduce resistance and greatly improve high-frequency characteristics, and on the other hand, can provide simplification and efficiency in manufacturing steps. Manufacturing method.
313892.ptc 第29頁 1267193 _案號 91116690 圖式簡單說明 修正 [圖面之簡單說明] 第1圖為說明本發明半導體裝置之剖視圖。 第2圖為說明本發明半導體裝置之俯視圖。 第3圖為說明本發明半導體裝置之俯視圖。 第4圖為說明本發明半導體裝置之俯視圖。 第5圖為說明本發明半導體裝置製造方法之剖視圖。 第6圖為說明本發明半導體裝置製造方法之剖視圖。 第7圖(A )及(B )為說明本發明半導體裝置製造方法之 剖視圖。 第8圖為說明本發明半導體裝置製造方法之剖視圖。 第9圖為說明習知之半導體裝置之剖視圖。 第1 0圖為說明習知之半導體裝置之俯視圖。 第1 1圖為說明習知之半導體裝置製造方法之剖視圖。 第1 2圖為說明習知之半導體裝置製造方法之剖視圖。 第1 3圖為說明習知之半導體裝置製造方法之剖視圖。 第1 4圖為說明習知之半導體裝置製造方法之剖視圖。 第1 5圖為說明習知之半導體裝置製造方法之剖視圖。 化合物半導體基板 3 η型離子植入區域313892.ptc Page 29 1267193 _ Case No. 91116690 Brief description of the drawings Correction [Simple description of the drawing] Fig. 1 is a cross-sectional view showing the semiconductor device of the present invention. Fig. 2 is a plan view showing the semiconductor device of the present invention. Fig. 3 is a plan view showing the semiconductor device of the present invention. Fig. 4 is a plan view showing the semiconductor device of the present invention. Fig. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device of the present invention. Figure 6 is a cross-sectional view showing a method of manufacturing a semiconductor device of the present invention. Fig. 7 (A) and (B) are cross-sectional views showing the method of manufacturing the semiconductor device of the present invention. Figure 8 is a cross-sectional view showing a method of manufacturing a semiconductor device of the present invention. Fig. 9 is a cross-sectional view showing a conventional semiconductor device. Fig. 10 is a plan view showing a conventional semiconductor device. Fig. 1 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. Fig. 2 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. Fig. 1 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. Fig. 14 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. Fig. 15 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. Compound semiconductor substrate 3 η-type ion implantation region
氮化膜 7 高濃度離子植入區域 8 第1電極、歐姆電極 11 第2電極、肖特基電極 1 4 a陽極焊墊 1 5 a陰極焊墊 2 2 η +型蠢晶層 9、 29 肖特 基 接 觸 孔 14 金屬層、 陽 極 電 極 15 金屬層、 陰 極 電 極 21 n+GaAs基 板 23 η型蠢晶層Nitride film 7 High concentration ion implantation region 8 First electrode, ohmic electrode 11 Second electrode, Schottky electrode 1 4 a Anode pad 1 5 a Cathode pad 2 2 η + type stray layer 9, 29 Special contact hole 14 metal layer, anode electrode 15 metal layer, cathode electrode 21 n+ GaAs substrate 23 n-type stray layer
313892.ptc 第30頁 1267193 _案號 91116690 圖式簡單說明 2 5 氧化膜 31 肖特基電極 34 陽極電極 P R 抗姓層 修正 30 聚醯亞胺層 3 1 a肖特基接合區域 3 5 陰極電極313892.ptc Page 30 1267193 _ Case No. 91116690 Brief description of the diagram 2 5 Oxide film 31 Schottky electrode 34 Anode electrode P R Anti-surname layer Correction 30 Polyimine layer 3 1 a Schottky junction region 3 5 Cathode electrode
313892.pic 第31頁313892.pic第31页
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CN112289791B (en) * | 2020-10-12 | 2023-01-17 | 中国电子科技集团公司第十三研究所 | Schottky diode and semiconductor device for terahertz frequency band junction capacitance test |
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