JP2008192998A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively utilize an area on a chip to largely secure an operating region while maintaining desired withstanding characteristics by effectively utilizing a corner section to provide a conductive region in a terminal region for suppressing the expansion of a depletion layer. <P>SOLUTION: A semiconductor device is provided with the conductive region 30 in the corner section of the semiconductor substrate (chip) 10. The corner section is wider than a region along a chip side because a terminal region is formed in a pattern having a predetermined curvature in the corner section of the chip. Therefore, an area on the chip can be effectively utilized by utilizing the corner section of the chip, if the conductive region is provided inside the terminal region. In addition, mountability is improved even if an area (width) of the conductive region is small by a configuration such that an electrode provided on one principal plane of the substrate is to be a multilayered structure that is connected to an external connection electrode through a wiring layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a conductive region provided with a conductive region penetrating a substrate and penetrating a semiconductor substrate in which electrodes are integrated on one main surface side of the substrate.

  Many discrete semiconductor devices (semiconductor chips) are provided with electrodes connected to input terminals and output terminals on both main surfaces (front and back surfaces) of the chip respectively. A type that is provided on a surface and can be surface-mounted is also known.

  With reference to FIG. 9, a conventional semiconductor device of a surface mountable type will be described taking MOSFET as an example. 9A is a plan view, and FIG. 9B is a cross-sectional view taken along the line cc of FIG. 9A.

  An n− type semiconductor layer 111 is provided on an n + type semiconductor substrate 110, and a p type impurity layer 112 is provided. A trench 115 reaching from the surface of the p-type impurity layer 112 to the n − -type semiconductor layer 111 is formed, an inner wall of the trench 115 is coated with a gate insulating film 116, and a gate electrode 117 is embedded in the trench 115 to form a number of MOSFET cells. Is provided. An n + type source region 114 is formed on the surface of the p type impurity layer 112 adjacent to the trench 115. The trench 115 is covered with an interlayer insulating film 118.

  The source electrode 120 is provided in connection with the source region 114 of each cell. The gate pad electrode 121 a is connected to the gate electrode 117 by a metal gate wiring 121 and a polysilicon gate wiring 125. The drain electrode 122 is provided on the n + type region 123 in the one end side region of the chip. In addition, a conductive region 119 that reaches the n + type semiconductor substrate 110 from the surface of the n + type region 123 through the n − type semiconductor layer 111 is provided, and the conductive region 119 is in contact with the drain electrode 122.

Solder bumps 126 serving as external connection terminals are provided on the gate pad electrode 121a, the source electrode 120, and the drain electrode 122 (see, for example, Patent Document 1).
JP 2002-353252 A

  When the conductive region 119 is provided as described above, the region where the conductive region 119 is disposed is limited to a predetermined region.

  When a reverse bias is applied to the MOSFET, a depletion layer spreads from the MOSFET cell arrangement region (operation region) 127 toward the end of the chip. Considering the withstand voltage characteristics, it is desirable that the conductive region 119 be disposed avoiding the depletion layer formation region.

  A high concentration impurity termination region (n + type region) 123 that terminates the spread of the depletion layer is disposed around the chip. Therefore, the conductive region 119 is disposed inside the termination region 123. That is, the position of the conductive region 119 is limited to the termination region 123 provided outside the operation region 127 and is concentrated on one end side of the chip in consideration of the influence on the occupied area of the operation region 127. . At present, the chip size has been reduced, and how to secure the operation area is an important issue.

  It is sufficient that the termination region 123 has such a width that the depletion layer extending from the operation region 127 can be terminated and has a width in which the conductive region 119 can be disposed. Further, when the conductive region 119 is formed of a low-resistance metal layer, the resistance value can be greatly reduced. That is, by reducing the area of the conductive region 119, the width of the termination region 123 can also be reduced. If the termination region 123 is reduced, the operation region 127 having a larger area can be secured.

  However, in the configuration in which the drain electrode 122 (bump electrode) is disposed in the termination region 123 as shown in FIG. 9, when the termination region 123 and the conductive region 119 are reduced, the area of the operation region 127 that can be secured is increased or the chip size is reduced. Has its limits.

  The present invention has been made in view of such a problem. First, the semiconductor substrate, the operating region of the discrete semiconductor provided on the semiconductor substrate, and at least the corner of the semiconductor substrate on the outer periphery of the operating region, And a conductive region having a metal layer penetrating the semiconductor substrate.

  According to the present invention, first, it is possible to maintain a desired withstand voltage characteristic and to dispose a conductive region inside the termination region without enlarging the termination region more than necessary. In general, the chip is rectangular, and the corner portion of the termination region is formed with a pattern having a predetermined curvature. In the present embodiment, a conductive region is provided in the termination region for effectively using the corner portion to suppress the spread of the depletion layer.

  As a result, the area on the chip can be effectively utilized, a large operation region can be secured while maintaining a desired breakdown voltage characteristic, and the resistance component of the semiconductor device can be reduced by increasing the parallel connection of transistor cells. Alternatively, the cost can be reduced by shrinking the chip size.

  Second, since the conductive region is composed of a through hole and a metal layer and has low resistance, an increase in resistance of the conductive region can be avoided even when the conductive region is provided in a small ineffective region at the end region corner.

  Third, even if the semiconductor device has a structure in which all the electrodes are provided on one main surface side of the chip away from the high-concentration semiconductor substrate by disposing the conductive regions at the four corners of the chip, It is possible to uniformly distribute the current from four directions without biasing the current pulled up to the electrodes to be connected.

  Fourthly, the external connection electrodes can be provided in an arbitrary area and pattern (or arrangement) while maintaining a pattern that can effectively use the area on the chip. That is, in the present embodiment, various electrode layers such as a first electrode layer in an operation region, a second electrode in a conductive region, and a gate electrode provided on one main surface side of a chip (semiconductor substrate) are arranged such as a bump electrode by a wiring layer. A configuration for connecting to an external connection electrode is adopted.

  Since the area of the conductive region provided in the ineffective region of the corner portion (the area of the planar pattern on one main surface) is small, it is expected that it will be difficult to connect to external connection electrodes such as wire bonds and bump electrodes when mounting the chip. . However, in this embodiment, a wiring layer connected to various electrode layers such as an operation region, a conductive region, and a gate electrode in a multilayer structure is provided, and this is connected to the external connection electrode. Accordingly, the external connection electrodes can be provided in an arbitrary area and pattern (or arrangement) while maintaining a pattern that can effectively use the area on the chip.

  That is, it is possible to combine high performance or low cost by effective use of the chip area and improvement of mountability.

  Embodiments of the present invention will be described in detail with reference to FIGS.

  The semiconductor device of the present invention includes a semiconductor substrate, an operation region, and a conductive region, and discrete semiconductor elements are formed in the operation region.

  Here, the discrete semiconductor element of the present embodiment is an individual name, a single function, or a generic name of these composite elements. Examples include a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a field effect transistor (FET) typified by a junction type FET, a bipolar transistor, a diode, and a thyristor. Furthermore, the discrete semiconductor according to the present embodiment includes a composite element in which different discrete semiconductor operation regions such as MOSFET and SBD (Schottky Barrier Diode) are integrated on the same substrate (chip).

  First, a first embodiment of the present invention will be described with reference to FIGS. Note that any element may be provided in the operation region as described above, but a case of a MOSFET will be described as an example.

  FIG. 1 is a diagram illustrating a MOSFET 100 according to the present embodiment. MOSFET 100 has a multilayer (here, two layers) electrode structure. FIG. 1A is a schematic plan view showing a semiconductor substrate 10 and a first electrode (electrode layer) constituting a semiconductor chip. FIG. 1B is a schematic plan view illustrating the second layer electrode (wiring layer) and the external connection electrode.

  As shown in FIG. 1A, an operation region 20 (two) in which a large number of MOSFET cells are arranged, for example, by diffusing a desired impurity in the center of the semiconductor substrate (semiconductor chip) 10 on the first main surface Sf1 side. A dotted line is provided.

  The semiconductor substrate 10 is rectangular, and conductive regions 30 are arranged at the four corner portions, respectively. The conductive region 30 extends from the first main surface Sf1 of the semiconductor substrate 10 to the second main surface (not shown here), that is, is provided through the semiconductor substrate 10. The conductive region 30 has a structure in which a through hole 31 reaching the second main surface from the first main surface Sf <b> 1 of the semiconductor substrate 10 is provided, and at least the inner wall of the through hole 31 is covered with the metal layer 32.

  A source electrode layer 17 in contact with the operating region 20 and a drain electrode layer 18 in contact with the conductive region 30 are provided on the operating region 20. A gate electrode layer 19 connected to the gate electrode of the MOSFET is provided outside the operation region 20.

  Referring to FIG. 1B, as described above, the source electrode S, the drain electrode D, and the gate electrode G each have a multilayer structure. In FIG. 1B, the first layer electrode is indicated by a one-dot chain line, and the second layer electrode is indicated by a solid line. That is, the source electrode S includes a first source electrode layer 17 and a second source wiring layer 27. The drain electrode D includes a first drain electrode layer 18 and a second drain wiring layer 28. The gate electrode G includes a first gate electrode layer 19 and a second gate wiring layer 29.

  On the source wiring layer 27, the drain wiring layer 28, and the gate wiring layer 29, a source bump electrode 37, a drain bump electrode 38, and a gate bump electrode 39 that are external connection electrodes are provided as indicated by circles. The diameter of each bump electrode 37, 38, 39 is, for example, about 250 μm.

  1 shows a total of four bump electrodes 37, 38, and 39, the number and arrangement thereof are not limited to those shown in the figure.

  FIG. 2 is a cross-sectional view taken along the line aa in FIG.

  The semiconductor substrate 10 has a configuration in which an n− type semiconductor layer (for example, an n− type epitaxial layer) 2 is provided on an n + type silicon semiconductor substrate 1. A channel layer 4 which is a p-type impurity region is provided on the surface of the n − type semiconductor layer 2 which becomes the first main surface Sf 1, and the semiconductor substrate 10 below the channel layer 4 becomes the drain region 3.

  The trench 7 passes through the channel layer 4 and reaches the n − type semiconductor layer 2. The trench 7 is generally patterned in a lattice shape or a stripe shape in the plane pattern of the first main surface Sf1.

  A gate oxide film 11 is provided on the inner wall of the trench 7. The thickness of the gate oxide film 11 is about several hundreds of squares depending on the MOSFET driving voltage. In addition, a conductive material is buried in the trench 7 to provide the gate electrode 13. The conductive material is, for example, polysilicon, and n-type impurities, for example, are introduced into the polysilicon in order to reduce the resistance.

  The source region 15 is an n + type impurity region in which an n type impurity is implanted into the surface of the channel layer 4 adjacent to the trench 7. Further, a body region 14 which is a diffusion region of a p + type impurity is provided on the surface of the channel layer 4 between the adjacent source regions 15 to stabilize the substrate potential. As a result, a portion surrounded by the adjacent trenches 7 becomes one cell of the MOS transistor, and a large number of the cells are collected to constitute an operation region 20 of the MOSFET.

  A high-concentration p-type impurity region 21 is provided on the outer periphery of the cell arrangement region. The p-type impurity region 21 is a so-called guard ring region that relaxes the curvature of the end of the depletion layer extending from the channel layer 4 to the n − -type semiconductor layer 2 when a reverse bias is applied to the operation region 20. In this embodiment, for convenience, the cell arrangement area up to the guard ring area 21 will be described as the operation area 20 (two-dot chain line in FIG. 1).

  The gate electrode 13 is covered with an interlayer insulating film 16. The source electrode layer 17 is a metal electrode that is patterned into a desired shape by sputtering aluminum (Al) or the like. The source electrode layer 17 is provided on the first main surface Sf1 side of the semiconductor substrate 10 so as to cover the operation region 20 and is connected to the source region 15 and the body region 14 through contact holes between the interlayer insulating films 16.

  The gate electrode 13 is drawn onto the substrate by the connecting portion 13c and extends to the gate electrode layer 19 surrounding the periphery of the semiconductor substrate. Although illustration is omitted here, the gate electrode layer 19 extends to, for example, a protective diode (not shown) provided at the chip corner portion and is connected to one end thereof (see FIG. 1A). The other end of the protection diode is connected to the source electrode layer 17.

  On the second main surface Sf2 side of the semiconductor substrate 10, a drain back surface electrode 18r is provided.

  A conductive region 30 reaching the second main surface S2 from the first main surface S1 is provided at the end of the semiconductor substrate 10. The conductive region 30 is disposed at each corner of the rectangular semiconductor substrate 10 as shown in FIGS.

  The conductive region 30 is formed by providing a through hole 31 penetrating the semiconductor substrate 10 and embedding a metal layer (for example, copper) 32 therein. The conductive region 30 is in contact with the drain back electrode 18r on the second main surface S2, and is electrically connected to the operation region 20. Also on the first main surface Sf1, the drain electrode layer 18 and the drain wiring layer 28 for connection to the external connection electrode (drain bump electrode 38) are provided, and the conductive region 30 is in contact with the drain electrode layer 18.

  The current flowing from the source electrode layer 17 into the semiconductor substrate 10 through the channel of the MOSFET 100 reaches the drain electrode layer 18 through the conductive region 30 through the low-resistance drain back electrode 18r or the vicinity thereof. The metal layer 32 of the conductive region 30 may cover at least the inner wall of the through hole 31, but the resistance of the conductive region 30 can be reduced by forming the interior with the metal layer 32 as shown in FIG. 2.

  The conductive region 30 is arranged along two sides of the corner portion of the semiconductor substrate 10 (see FIG. 1), and a distance W1 from the end portion of the conductive region 30 to the end portion E of the semiconductor substrate 10 is, for example, 50 μm. The width W2 of the conductive region 30 is, for example, 40 μm.

  A termination region 22 is disposed on the outermost periphery of the semiconductor substrate 10, and the conductive region 30 is provided in the termination region 22. When a reverse bias is applied to the MOSFET, the depletion layer d (see the dotted line in FIG. 1A) spreads in the n − type semiconductor layer 2 as described above. The depletion layer d is terminated below the termination region 22 (drain electrode 18). More specifically, the termination is performed on the end E side of the semiconductor substrate 10 from the joint surface J between the termination region 22 and the n − type semiconductor layer 2 shown in FIG.

  Thus, the termination region 22 is a region that terminates the depletion layer d spreading on the outer periphery of the operation region 20, and is a so-called annular region in which high-concentration n-type impurities are diffused.

  That is, the conductive region 30 is provided, for example, 5 μm to 10 μm outside the junction surface J between the termination region 22 and the semiconductor substrate 10 and inside the end E of the semiconductor substrate 10 so that the depletion layer d does not reach the chip end E. It is done. Further, since the termination region 22 is a diffusion region provided on the first main surface Sf1 of the semiconductor substrate 10, the conductive region 30 penetrates through this and reaches the second main surface Sf2.

  In consideration of the withstand voltage characteristics, it is desirable that the conductive region 30 be disposed so as to avoid a region (see FIG. 1A) where the depletion layer d expands when a reverse bias is applied. Therefore, a termination region 22 that terminates the spread of the depletion layer d is provided, and the conductive region 30 is disposed inside the termination region 22.

  In the conventional structure, as shown in FIG. 9, in the structure in which the drain (bump) electrode is arranged outside the operation region, the high-concentration impurity region 123 is also ensured to be larger than the area necessary for its original function. There was a limit to the expansion of the area.

  Therefore, in this embodiment, the electrode structure is multilayered, the conductive region 30 is disposed in the invalid region of the termination region 22, and the utilization area of the operation region is expanded.

  In general, the shape of the semiconductor substrate 10 (semiconductor chip) is rectangular. For example, in the planar pattern of the first main surface Sf1, the p-type impurity region 21 and the termination region 22 provided on the outer periphery of the operation region 20 A pattern having a predetermined curvature is formed.

  The width W3 'of the termination region 22 provided along the side (chip side) of the semiconductor substrate 10 and the curvature at the corner are designed according to the characteristics of the semiconductor device. Since the termination region 22 is provided up to the end E of the semiconductor substrate 10, the width W3 of the termination region at the corner is wider than the width W3 ′ of the termination region 22 along the side of the semiconductor substrate 10, and the increment is This is an invalid area that does not affect the characteristics of the device.

  Therefore, in the present embodiment, the conductive region 30 is provided in the corner portion including the invalid region so as to effectively use the area on the chip. That is, the planar pattern of the conductive region 30 on the first main surface Sf1 is shaped so as to follow the corner portion of the semiconductor substrate 10, and specifically, for example, similar to or substantially similar to a triangle formed by two sides of the corner portion. It is formed with a similar triangular pattern. Then, the two sides of the conductive region 30 are arranged along the two sides of the corner portion of the semiconductor substrate 10 (see FIG. 1).

  The termination region 22 provided along the side of the semiconductor substrate 10 may have a width W <b> 3 ′ necessary and sufficient for suppressing the depletion layer spread as the termination region 22.

  In the present embodiment, the electrode connected to the operation region 20 has a two-layer structure, and the conductive region 30 is provided in the terminal region 22 at the corner portion of the semiconductor substrate 10 that becomes the ineffective region. Thereby, if the chip size is the same, the parallel connection of the transistor cells can be increased by expanding the operation region 20, and the resistance component of the MOSFET can be reduced. Alternatively, the cost can be reduced by shrinking the chip size.

  The corner portion including the invalid area is a relatively small area. However, since the conductive region 30 has a configuration in which the metal layer 32 is formed in the through hole 31, the resistance value of the conductive region 30 is low, and even if the width W2 of the conductive region 30 is small (for example, 40 μm), an increase in resistance can be avoided. .

  Further, by arranging the conductive region 30 at the corner portion of the semiconductor substrate 10, a current path for pulling up the current flowing through the semiconductor substrate 10 to the drain electrode 18 on the first main surface Sf 1 side is formed around the semiconductor substrate (semiconductor chip) 10. Evenly arranged. Therefore, uniform operability can be improved.

  Next, the electrode structure of the present embodiment will be described with reference to FIG.

  In the present embodiment, a multilayer structure in which the first source electrode layer 17, the drain electrode layer 18, and the gate electrode layer 19 provided on the first main surface Sf1 side of the semiconductor substrate 10 are connected to the external connection electrodes by the wiring layers, respectively. Adopt it.

  FIG. 3 is a cross-sectional view taken along the line bb of FIG. Since the configuration of the operation region 20 is the same as that shown in FIG.

  The source electrode layer 17 is in contact with the source region 15 in the operation region 20, and the drain electrode layer 18 is in contact with the conductive region 30 and is connected to the operation region 20 through the conductive region 30.

  A nitride film 23 is provided in a desired pattern on the source electrode layer 17, the drain electrode layer 18, and the gate electrode layer 19 that are the first layer, and the source wiring layer 27, the drain wiring layer 28, and the The illustrated gate wiring layer is formed in a desired pattern.

  For example, in FIG. 3, in the region a where the source wiring layer 27 is disposed on the source electrode layer 17, the nitride film 23 between them is opened. In the region b where the drain wiring layer 28 is disposed on the source electrode layer 17 and the gate electrode layer 19, these are insulated by the nitride film 23. Further, in the region c where the drain wiring layer 28 is disposed on the drain electrode layer 18, the nitride film between them is opened.

  Further, an insulating film (nitride film) 23 is provided on these to open a predetermined region, and an UBM (Under Bump Metal) 24 is provided. The UBM 24 is a metal layer in which nickel (Ni: thickness: 2.4 μm) and gold (Au: thickness: 500 mm) are laminated in this order from the lower layer by, for example, electroless plating. On the nitride film 23, a solder resist 25 from which the UBM 24 is exposed is provided, and a source bump electrode 37 is provided by screen printing using the UBM 24 as a base electrode. The diameter of the source bump electrode 37 is about 250 μm. 3 shows the case where the source bump electrode 37 is arranged at the end of the operation region 20 for convenience of explanation, but in actuality, the source bump electrode 37 is arranged so that the source potential is uniformly applied to the operation region 20.

  Similarly to the source bump electrode 37, the drain bump electrode 38 is provided on the drain wiring layer 28. Although illustration is omitted here, the gate electrode layer 19 is in a partial region and is in contact with the second gate wiring layer through the opening of the nitride film 23 as in the region a and the region b. Further, it is in contact with a gate bump electrode 39 provided in the same manner as the source bump electrode 37 (see FIG. 1B). Here, the bump electrode is described as an example of the external connection electrode, but a bonding wire or the like may be used.

  Since the area of the conductive region 30 (using the ineffective region at the corner portion of the semiconductor substrate 10) (the area of the planar pattern on the first main surface Sf1) is relatively small, when mounting, the outside of bonding wires, bump electrodes, etc. Connection with the connection electrode is difficult. However, in this embodiment, a source wiring layer 27, a gate wiring layer 29, and a drain wiring layer 28 that are connected to the source electrode layer 17, the gate electrode layer 19, and the drain electrode layer 18 in a multilayer structure are provided, and these are connected to the external connection electrodes ( Each bump electrode is connected. As a result, the MOSFET cell can be disposed below the drain electrode D (drain wiring layer 28), and the external connection electrode can be formed in an arbitrary area and pattern while maintaining a pattern in which the area on the semiconductor substrate 10 can be effectively utilized. (Or arrangement).

  As described above, in the present embodiment, the conductive region 30 serving as a current path for drawing out a current (for example, drain current) flowing through the semiconductor substrate 10 is disposed in the chip corner portion where the invalid region is widely left. Thereby, the path of the current flowing through the semiconductor substrate 10 can be secured without increasing the termination region area so much. Thereby, the effective use of the chip area can be achieved.

  Furthermore, by making the electrode structure a multi-layer structure, for example, in the case of a MOSFET, a MOSFET cell can be arranged below the drain electrode D (drain wiring layer 28). That is, even if the drain electrode D is arranged on the first main surface Sf1 side, the chip area can be effectively utilized.

  That is, it is possible to combine high performance or low cost by effective use of the chip area and improvement of mountability.

  It is also possible to design a desired pattern for the source electrode layer 17, the drain electrode layer 18, and the gate electrode layer 19 without providing each wiring layer, and to have a single-layer electrode structure that is directly connected to each bump electrode. is there. In that case, in the pattern as shown in FIG. 2, the drain electrode layer 18 is secured wide enough to form bumps. Therefore, in this case, the MOSFET cell is not disposed below the drain electrode layer 18, but the number of steps and the cost can be reduced.

  Next, another embodiment of the present invention will be described with reference to FIGS. The other embodiment is a case where the planar pattern on the first main surface Sf1 of the conductive region 30 is different from that of the first embodiment. That is, since the configuration of the operation region 20 and each electrode, wiring layer, and bump electrode connected thereto is the same as that of the first embodiment, the explanation and illustration are omitted, and a schematic plan view similar to FIG. Will be described.

  FIG. 4 shows a second embodiment.

  The second embodiment is another form in which the conductive region 30 is provided at each corner. 4A, the conductive region 30 is formed in an L shape in each of the four corner portions, and the two sides of the conductive region 30 are arranged along the two sides of the corner portion.

  FIG. 4B shows a case where the conductive region 30 is formed with a pattern composed of two sides and an arcuate portion. Two sides of the conductive region 30 are disposed along two sides of the corner portion of the semiconductor substrate 10, and the arc-shaped portion of the conductive region 30 is formed with a curvature that follows the shape of the corner portion of the termination region 22.

  Further, FIG. 4C shows a case where the conductive region 30 and the end E side of the semiconductor substrate 10 are formed to have a predetermined curvature.

  FIG. 5 shows a third embodiment.

  The third embodiment is a case where the conductive region 30 is also disposed in a region other than the corner portion. In FIG. 5A, a discontinuous conductive region 30 is disposed over the entire termination region 22 on the outer periphery of the operation region 20. In this case, each corner portion has an L-shaped pattern as shown in FIG. Alternatively, each corner portion may be the pattern of FIGS. 4B and 4C of the first embodiment or the second embodiment.

  In FIG. 5B, a conductive region 30 that is continuous over the entire termination region 22 is provided. Although FIG. 5 (B) shows a case of forming a rectangular shape, each corner portion may be the first embodiment or FIGS. 4 (B) and (C) of the second embodiment.

  FIG. 6 shows a fourth embodiment.

  In the fourth embodiment, a cylindrical conductive region 30 is provided at each corner portion. FIG. 6A shows a case in which one end region 22 is provided in each corner portion. FIGS. 6B to 6D show a plurality of cylindrical conductive regions 30 in each corner portion. FIGS. 6C and 6D show a case where a plurality of cylindrical conductive regions 30 are arranged so as to have the same pattern as in the second embodiment. FIG. 6E shows a case where the columnar conductive region 30 is arranged over the entire termination region 22.

  The pattern of the conductive region 30 in FIGS. 4 to 6 is merely an example, and may be a pattern disposed at least inside the terminal region 22 at the corner portion.

  In the present embodiment, since the source bump electrode 37 and the drain bump electrode 38 which are external connection electrodes are both provided on the first main surface Sf1 side, a back surface drain electrode 18r made of a metal layer is provided on the second main surface Sf2 side. However, the resistance can be further reduced if the back surface drain electrode 18r is provided as shown in FIG.

  As described above, in the present embodiment, the case where a MOSFET is formed in the operation region 20 has been described as an example. However, the present invention is not limited to this, and a discrete semiconductor such as an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, an SBD, or a pn junction diode. It may be a device. Further, even a semiconductor device in which a plurality of operation regions in which different elements such as SBDs and MOSFETs are arranged is integrated on the same chip (semiconductor substrate) can be similarly implemented. Since these elements are also provided with a termination region, the conductive region 30 is disposed at least in the corner portion of the semiconductor substrate 10 inside the termination region.

  Next, with reference to FIGS. 7 to 8, a method for manufacturing the semiconductor device will be described.

  First, as shown in FIG. 7A, a semiconductor substrate 10 in which an n− type semiconductor layer 2 is stacked on an n + type silicon semiconductor substrate 1 is prepared. The total film thickness T1 is about several hundred μm (for example, 600 μm). The operation region 20 is formed on the first main surface Sf1 side of the semiconductor substrate 10 by forming a desired impurity diffusion region by a known method.

Although the illustration of the operation region 20 is omitted here, an example in which a MOSFET is formed in the operation region 20 will be described with reference to FIG. The n − type semiconductor layer 2 is an epitaxial layer, for example, and is a low concentration layer having an impurity concentration of about 2E16 cm ⁻³ , for example. A p + type impurity region (guard ring region) 21 is formed by ion implantation (dose amount: 5.0E14 cm ⁻² , acceleration energy 50 KeV) and diffusion in a desired region by a mask. Thereafter, phosphorus is implanted and diffused at a high concentration in the outer peripheral portion of the semiconductor substrate 10 to form an n-type termination region (annular region) 22. Then, after forming an oxide film (not shown) on the surface, the oxide film in the channel layer formation region is etched to expose the surface of the substrate 10. Using this oxide film as a mask, for example, boron or the like is implanted over the entire surface at a dose of 5.0E15 cm ⁻² and an acceleration energy of about 50 KeV, and then diffused by heat treatment to form the p-type channel layer 4.

  A CVD oxide film (not shown) of NSG (Non-Doped Silicate Glass) is formed on the entire surface, and a mask made of a resist film is applied except for a portion serving as a trench opening. The CVD oxide film is partially removed by dry etching to form a trench opening in which the n − type semiconductor layer 2 is exposed.

  Further, after removing the resist film, the trench 7 is formed by dry etching the silicon semiconductor substrate in the trench opening with a CF-based gas and an HBr-based gas using the CVD oxide film as a mask. The depth of the trench 7 is formed to penetrate the channel layer 4.

  Dummy oxidation is performed to form a dummy oxide film (not shown) on the inner wall of the trench 7 and the surface of the channel layer 4 to remove etching damage during dry etching. The dummy oxide film formed by this dummy oxidation is removed by an oxide film etchant such as hydrofluoric acid.

  Thereby, a stable gate oxide film can be formed. In addition, the thermal oxidation at a high temperature has an effect of rounding the opening of the trench 7 to avoid electric field concentration at the opening of the trench 7. Thereafter, a gate oxide film 11 having a predetermined thickness corresponding to the driving voltage is formed.

  A non-doped polysilicon layer is deposited on the entire surface, and, for example, phosphorus (P) is implanted and diffused at a high concentration to increase the conductivity. The polysilicon layer deposited on the entire surface is dry etched without a mask to form the gate electrode 13 embedded in the trench 7. The gate electrode 13 may be embedded in the trench 7 by depositing polysilicon doped with impurities over the entire surface and then etching back.

A p-type impurity such as boron (B) is selectively ion-implanted into the body region formation region with an implantation energy of 50 KeV and a dose amount of about 1E15 cm ⁻² by a mask made of a resist film, and the resist film is removed. Further, the source region formation region and the gate electrode 13 are masked with a new resist film, and n-type impurities such as arsenic (As) are ion-implanted with an implantation energy of 140 KeV and a dose of about 5E15 cm ⁻² . Note that the step of implanting the p-type impurity and the n-type impurity may be interchanged.

  Thereafter, an insulating film such as BPSG (Boron Phosphorus Silicate Glass) serving as an interlayer insulating film is deposited on the entire surface by a CVD method. By this heat treatment at the time of film formation (less than 1000 ° C., about 30 minutes), the source region 15 is formed on the surface of the channel layer 4 adjacent to the trench 7, and at the same time, the body region 14 located between the source regions 15 is formed.

  Note that the termination region 22 is not formed before the channel layer 4 is formed, and n-type impurities are ion-implanted into the outer periphery of the chip simultaneously with the n-type impurity implantation of the source region 15 and diffused simultaneously with the diffusion treatment of the source region 15. Thus, the termination region 22 may be formed.

  The insulating film is etched using the resist film as a mask to leave the interlayer insulating film 16 on at least the gate electrode 13 and form a contact hole CH in which the source region 15 and the body region 14 are exposed. As a result, the termination region 22 is also exposed on the surface of the semiconductor substrate 10.

  After that, a barrier metal layer (not shown) made of a titanium-based material is formed, and an aluminum alloy, for example, is sputtered to a thickness of about 3 μm on the entire surface. Patterning into a predetermined shape such as an electrode layer (not shown).

  Further, an insulating film 23 such as a nitride film is formed, a desired region is opened, and a second metal layer is formed thereon by sputtering or the like. This is patterned into a desired shape to form a source wiring layer 27, a drain wiring layer 28, and a gate wiring layer (not shown).

  By making the electrode structure a multi-layer structure, the drain wiring layer 28 can also extend over the MOSFET cell. As a result, an external connection electrode (bump electrode) that is large relative to the chip area can be formed without reducing the operating area.

  Further, an insulating film 23 such as a nitride film is formed on the entire surface, and an opening (an opening for forming UMB) serving as a contact hole with the external connection electrode is formed at a desired position of the insulating film 23.

  Next, as shown in FIG. 7B, the n + -type silicon semiconductor substrate 1 is ground by back grinding from the second main surface Sf2 side of the semiconductor substrate 10 to a desired thickness T2 (for example, 100 μm to 300 μm).

  Thereafter, a conductive region is formed. That is, as shown in FIG. 8A, the semiconductor substrate 10 is attached to the upper surface of the support substrate 51 with the adhesive 50 interposed therebetween. The support substrate 51 has a thickness capable of mechanically supporting the thin semiconductor substrate 10 and is made of, for example, glass, plastic, metal, or the like. The second main surface Sf2 of the semiconductor substrate 10 is covered with a mask 40 made of a resist (thickness: about 20 μm, for example). And the mask 40 of the area | region where a through-hole is to be formed is partially removed, and the opening part 42 is provided.

  Referring to FIG. 8B, by performing dry etching through mask 40, through hole 31 penetrating n + type silicon semiconductor substrate 1, n − type semiconductor layer 2, and termination region 22 is formed. The through hole 31 is provided outside the joint surface J between the semiconductor substrate 10 and the termination region 22 and inside the end E of the semiconductor substrate 10. The width W1 from the end E of the semiconductor substrate 10 to the end of the termination region 22 is, for example, 50 μm, and the width W2 of the through hole 31 is, for example, 40 μm.

  Referring to FIG. 8C, a metal film is formed in the through hole 31 and on the second main surface Sf2 of the semiconductor substrate 10 to form the conductive region 30 and the drain back electrode 18r. First, a barrier metal layer is formed on the entire inner wall and back surface of the through hole 31. The barrier metal layer is made of a metal layer such as a titanium (Ti) layer, a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer, or a tantalum nitride (TaN) layer, and is formed by sputtering or the like. . Next, a seed layer (not shown) made of Cu having a thickness of about several hundred nm is formed on the entire inner wall of the through hole 31 (the inner wall of the barrier metal layer) and the entire back surface of the semiconductor substrate 10. The seed layer is preferably formed by sputtering. Next, electrolytic plating using this seed layer as an electrode is performed. That is, a needle is raised on the electrode attached to the plating solution and the seed layer (drain back electrode side) formed on the wafer, and a voltage is applied. Thus, a metal film made of Cu having a thickness of about several μm is formed on the inner wall of the through hole 31 and the back surface of the semiconductor substrate 10.

  In this way, the conductive region 30 is formed, and the drain back electrode 18r is formed. The drain back electrode 18r is electrically connected to the drain electrode 18 provided on the first main surface Sf1 side through the conductive region 30.

  After the above process is completed, the semiconductor substrate 10 is peeled from the support substrate 51.

Thereafter, as shown in FIG. 3, the UBM 24 is formed in the opening. The UBM 24 is a metal layer in which nickel (Ni: thickness: 2.4 μm) and gold (Au: thickness: 500 mm) are laminated in this order from the lower layer by, for example, electroless plating. Further, a solder resist 25 exposing the UBM 24 is provided on the insulating film 23, and a source bump electrode 37, a drain bump electrode 38, and a gate bump electrode (not shown) are formed by screen printing using the UBM 24 as a base electrode. Get.

It is a top view explaining the semiconductor device of this invention. It is sectional drawing explaining the semiconductor device of this invention. It is sectional drawing explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is (A) top view explaining the conventional semiconductor device, (B) sectional drawing.

Explanation of symbols

1 n + type silicon semiconductor substrate 2 n− type semiconductor layer 4 channel layer 7 trench 10 semiconductor substrate (semiconductor chip)
DESCRIPTION OF SYMBOLS 11 Gate insulating film 13 Gate electrode 13c Connecting part 14 Body region 15 Source region 16 Interlayer insulating film 17 Source electrode layer 18 Drain electrode layer 18r Drain back electrode 19 Gate electrode layer 20 Operation region 22 Termination region 23 Insulating film (nitride film)
24 UBM
25 Solder resist 27 Source wiring layer 28 Drain wiring layer 30 Conductive region 31 Through hole 32 Metal layer 37 Source bump electrode 38 Drain bump electrode 39 Gate bump electrode 40 Mask 42 Opening 50 Adhesive material 51 Support substrate 110 Semiconductor substrate 111 n-type Semiconductor layer 112 p-type impurity layer 113 body region 114 source region 115 trench 116 gate insulating film 117 gate electrode 118 interlayer insulating film 120 source electrode 121a gate pad electrode 121 metal gate wiring 125 polysilicon gate wiring 122 drain electrode 123 n + type region 126 Solder bump

Claims (10)

A semiconductor substrate;
An operating area of a discrete semiconductor provided on the semiconductor substrate;
A conductive region provided at least in a corner portion of the semiconductor substrate on the outer periphery of the operation region, and having a metal layer penetrating the semiconductor substrate;
A semiconductor device comprising:   2. The semiconductor substrate according to claim 1, wherein a termination region for terminating a depletion layer extending on an outer periphery of the operation region is provided on the semiconductor substrate, and the conductive region is provided outside a bonding surface between the semiconductor substrate and the termination region. The semiconductor device described.   The termination region is a high-concentration impurity region provided at an outer peripheral end on one main surface side of the semiconductor substrate, and the conductive region is provided through the high-concentration impurity region in the high-concentration impurity region. The semiconductor device according to claim 2.   The semiconductor device according to claim 1, wherein the conductive region is disposed along two sides of the semiconductor substrate in a planar pattern of one main surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the conductive region is electrically connected to the operation region.   The semiconductor device according to claim 1, wherein the conductive region is formed by covering at least an inner wall of a through hole provided in the semiconductor substrate with a conductive material.   The semiconductor device according to claim 1, wherein the conductive region is continuously provided on an outer periphery of the operation region.   The semiconductor device according to claim 1, wherein the conductive region is provided discontinuously on an outer periphery of the operation region.   A first electrode layer connected to the operating region, a second electrode layer electrically connected to the conductive region, and the first electrode layer and the second electrode layer on one main surface side of the semiconductor substrate, respectively 2. The first wiring layer and the second wiring layer to be connected, and the first external connection electrode and the second external connection electrode to be connected to the first and second wiring layers, respectively, are provided. Semiconductor device.   The semiconductor device according to claim 1, wherein another metal layer is provided on the other main surface side of the semiconductor substrate, and the conductive region is connected to the other metal layer.

Images