JP7507322B1 - Semiconductor Device - Google Patents

Abstract

A chip-size package type semiconductor device (1) capable of face-down mounting comprises a semiconductor substrate (32), a semiconductor layer (40) formed on the semiconductor substrate (32), a vertical field effect transistor (10) formed on the semiconductor layer (40), a ball-shaped bump electrode having a height of 100 μm or more formed on the front side of the semiconductor layer (40), and a multi-layered metal layer (30) formed in contact with the entire surface of the rear side of the semiconductor substrate (32), wherein a first metal layer (30a) which is the thickest of the metal layers (30) is mainly composed of a first metal which has the highest ductility among the metal types constituting the metal layer (30), the first metal layer (30a) has a thickness of 8 μm or more, and in a plan view of the semiconductor layer (40), the outer periphery of the metal layer (30) is provided with a protrusion (50) which protrudes downward on the rear side of the semiconductor substrate (32), and in a cross-sectional view of the protrusion (50), there is a portion where the width of the protrusion (50) is 5 μm or more.

Description

The present disclosure relates to semiconductor devices, and in particular to chip-size package type semiconductor devices.

Vertical field effect transistors are required to have ball-shaped bump electrodes.

Japanese Patent No. 5073992

Patent document 1 discloses a structure of a vertical field effect transistor having a ball-shaped bump electrode, with an electrode metal of about 2 μm thickness on the back surface. In a vertical field effect transistor having a ball-shaped bump electrode, protrusions (burrs) formed on the electrode metal on the back surface may fall off after ultrasonic cleaning and become a cause of short circuit with other components.

In order to solve the above problems, the semiconductor device according to the present disclosure is a chip-size package type semiconductor device capable of face-down mounting, comprising a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a vertical field-effect transistor formed on the semiconductor layer, a ball-shaped bump electrode having a height of 100 μm or more formed on the front side of the semiconductor layer, and a multi-layered metal layer formed in contact with the entire surface of the rear side of the semiconductor substrate, wherein the thickest first metal layer of the metal layers is mainly composed of a first metal having the highest ductility among the metal types constituting the metal layer, the first metal layer has a thickness of 8 μm or more, the outer periphery of the metal layer is provided with a protrusion (burr) protruding downward on the rear side of the semiconductor substrate in a plan view of the semiconductor layer, and the protrusion has a portion in a cross-sectional view where the width of the protrusion is 5 μm or more.

With this configuration, the protrusions (burrs) of the metal layer formed during the process of singulating the semiconductor device can be stably formed with a wide structure, and it is possible to prevent the protrusions (burrs) from falling off and becoming a cause of short circuits when the semiconductor device is subjected to an impact such as ultrasonic cleaning.

The present disclosure aims to provide a semiconductor device that has a ball-shaped bump electrode, has low on-resistance, and is resistant to impacts such as ultrasonic cleaning.

FIG. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment. FIG. 3A is a schematic plan view of a general unit configuration of the vertical field effect transistor according to the first embodiment. FIG. 3B is a schematic perspective view of a substantial unit configuration of the vertical field effect transistor according to the first embodiment. FIG. 4 is a flow diagram showing a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a perspective SEM image of the semiconductor device according to the first embodiment. FIG. 6A is a cross-sectional SEM image of a semiconductor device according to Comparative Example 1 of the first embodiment. FIG. 6B is a cross-sectional SEM image of a semiconductor device according to Comparative Example 1 of the first embodiment. FIG. 7A is a planar electron microscope image of a semiconductor device according to Comparative Example 1 of the first embodiment. FIG. 7B is a planar electron microscope image of the semiconductor device according to Comparative Example 1 of the first embodiment. FIG. 8A is a schematic cross-sectional view showing a point in time of the process of dividing the semiconductor device according to the first embodiment. FIG. 8B is a schematic cross-sectional view showing a point in time of the process of dividing the semiconductor device according to the first embodiment. FIG. 8C is a schematic cross-sectional view showing a point in time of the process of dividing the semiconductor device according to the first embodiment. FIG. 8D is a schematic cross-sectional view showing a point in time of the process of dividing the semiconductor device according to the first embodiment. FIG. 8E is a schematic cross-sectional view showing a point in time of the process of dividing the semiconductor device according to the first embodiment. FIG. 8F is a schematic cross-sectional view showing a point in time of the process of dividing the semiconductor device according to the first embodiment. FIG. 9A is a cross-sectional SEM image of the semiconductor device according to the first embodiment. FIG. 9B is an enlarged view of the white framed portion of FIG. 9A, which is a cross-sectional SEM image of the semiconductor device according to the first embodiment. FIG. 10 shows cross-sectional SEM images of the semiconductor devices according to the first embodiment and the first comparative example of the first embodiment, and the falling-off rate of the protrusions after ultrasonic cleaning. FIG. 11 shows a cross-sectional SEM image of a semiconductor device according to Comparative Example 2 of the first embodiment and a falling-off rate of protrusions after ultrasonic cleaning. FIG. 12A is a cross-sectional SEM image of the semiconductor device according to the first embodiment. FIG. 12B is a cross-sectional SEM image of the semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional SEM image of the semiconductor device according to the first embodiment when mounted face-down.

Below, a specific example of a semiconductor device according to one aspect of the present disclosure will be described with reference to the drawings. Each embodiment shown here shows one specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangements of components, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, the same reference numerals are used for substantially the same configuration, and duplicate explanations are omitted or simplified.

(Embodiment 1)
[1. Structure of the semiconductor device]
The structure of the vertical field effect transistor 10 in the present disclosure will be described taking a single configuration as an example. However, in order to enjoy the effects of the present disclosure, the single configuration is not essential, and a vertical field effect transistor with a dual configuration or a vertical field effect transistor with a triple or more configuration may be used.

Figure 1 is a cross-sectional view showing an example of the structure of semiconductor device 1. Figure 2 is its plan view, and the size, shape, and pad arrangement of semiconductor device 1 are one example. Figure 1 is a cross-section taken along line I-I in Figure 2. Also, S, G, and D shown in Figure 2 indicate source, gate, and drain bump electrodes, respectively.

1 and 2, the semiconductor device 1 has a semiconductor layer 40, a metal layer 30, and a vertical field effect transistor 10 (hereinafter also simply referred to as transistor 10) formed in the semiconductor layer 40. The semiconductor layer 40 has an active region A1 in a plan view of the semiconductor layer 40. The active region A1 is the minimum range that includes all of the region in which an inversion layer is formed and becomes a conductive channel when a voltage equal to or greater than a threshold value is applied to a gate electrode (not shown) with respect to the potential of the source electrode 11.

The semiconductor layer 40 has a control region A2 that contains a gate electrode and controls the conduction of the active region A1 in a plan view of the semiconductor layer 40. The semiconductor layer 40 also has a conductive drain region A3 that includes a drain pull-up region 38 that provides electrical conduction between the drain region (semiconductor substrate 32) described below and the surface side of the semiconductor layer 40.

The semiconductor layer 40 is formed by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33. The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of the first conductivity type containing impurities of the first conductivity type. The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. The low-concentration impurity layer 33 is of the first conductivity type, containing impurities of the first conductivity type at a concentration lower than the concentration of the impurities of the first conductivity type in the semiconductor substrate 32.

The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth. The low-concentration impurity layer 33 is also the drift layer of the transistor 10, and may be referred to as the drift layer in this specification.

The metal layer 30 is formed in contact with the back surface side of the semiconductor layer 40, and is formed over the entire back surface side of the semiconductor layer 40. The metal layer 30 has a multi-layer structure and is composed of a first metal layer 30a and a second metal layer 30b that is in contact with the first metal layer 30a and exposed on the back surface side of the semiconductor device 1.

The first metal layer 30a is at least 8 μm thick and is the thickest metal layer in the multi-layer structure. Furthermore, the first metal layer 30a is mainly composed of a first metal that is the most ductile of the metal types constituting the metal layer 30. The first metal can be, for example, silver (Ag) or copper (Cu).

The second metal layer 30b is mainly composed of a second metal that is less ductile than the first metal. The second metal can be, for example, nickel (Ni). Note that the metal layer 30 (the first metal layer 30a and the second metal layer 30b) may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material.

The metal layer 30 has a protrusion 50 formed thereon, which protrudes downward toward the rear surface side of the semiconductor substrate 32. The protrusion 50 is formed along the outer periphery of the metal layer 30 in a plan view (see FIG. 5). The protrusion 50 contains a first metal, which is the main component of the first metal layer 30a. Details of the protrusion 50 will be described later. Note that the protrusion 50 shown in FIG. 1 does not necessarily accurately represent the component ratio of the first metal to the second metal.

1 and 2, a body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the active region A1 of the low-concentration impurity layer 33. A source region 14 containing impurities of the first conductivity type, a gate conductor 15, and a gate insulating film 16 are formed in the body region 18. The gate conductor 15 and the gate insulating film 16 are formed inside a plurality of gate trenches 17 formed to a depth from the upper surface of the semiconductor layer 40 through the body region 18 to a part of the low-concentration impurity layer 33. The source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the source region 14 and the body region 18 via the portion 13. The gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to a ball-shaped gate bump electrode 119 via a gate electrode (not shown) installed in the control region A2.

The portion 12 of the source electrode 11 is a layer that is bonded to the ball-shaped source bump electrode 111, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

Portion 13 of source electrode 11 is a layer that connects portion 12 to semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

In the drain conduction region A3 in the low-concentration impurity layer 33, a drain pull-up region 38 is formed to a depth reaching the semiconductor substrate 32. The drain pull-up region 38 is a layer containing impurities of the first conductivity type at a concentration higher than the concentration of the impurities of the first conductivity type in the low-concentration impurity layer 33.

The portion 82 of the drain electrode 81 is a layer that is bonded to the ball-shaped drain bump electrode 181, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 82 may be plated with gold or the like.

Portion 83 of drain electrode 81 is a layer that connects portion 82 to semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

With the above-described configuration of transistor 10, semiconductor substrate 32 functions as a drain region of transistor 10. A portion of low-concentration impurity layer 33 on the side in contact with semiconductor substrate 32 may also function as a drain region. Metal layer 30 also functions as a drain electrode of transistor 10.

1, the body region 18 is covered with an interlayer insulating layer 34 having an opening, and a portion 13 of the source electrode 11 is provided through the opening of the interlayer insulating layer 34, the portion 13 being connected to the source region 14. The interlayer insulating layer 34 and the portion 13 of the source electrode 11 are covered with a passivation layer 35 having an opening, and a portion 12 is provided that is connected to the portion 13 of the source electrode 11 through the opening of the passivation layer 35. A ball-shaped source bump electrode 111 is installed in contact with the portion 12 of the source electrode 11 through the opening of the passivation layer 35.

The drain pull-up region 38 is covered with an interlayer insulating layer 34 having an opening, and a portion 83 of the drain electrode 81 is provided through the opening of the interlayer insulating layer 34 and connected to the drain pull-up region 38. The interlayer insulating layer 34 and the portion 83 of the drain electrode 81 are covered with a passivation layer 35 having an opening, and a portion 82 is provided that is connected to the portion 83 of the drain electrode 81 through the opening of the passivation layer 35. A ball-shaped drain bump electrode 181 is installed in contact with the portion 82 of the drain electrode 81 through the opening of the passivation layer 35.

The areas of the source electrode 11 and the drain electrode 81 that are partially exposed on the surface of the semiconductor device 1 through the openings in the passivation layer 35 are called the source pad and the drain pad, respectively. The source bump electrode 111 and the drain bump electrode 181 are installed in contact with the source pad and the drain pad, respectively. Similarly, although not shown in FIG. 1, the gate bump electrode 119 is installed in contact with the gate pad where the gate electrode (not shown) is partially exposed on the surface of the semiconductor device 1.

The source bump electrode 111, the gate bump electrode 119, and the drain bump electrode 181 are typically ball-shaped. In this specification, a bump electrode being ball-shaped includes a shape in which a part of a perfect sphere has been cut off or chipped. Typically, the source pad, gate pad, and drain pad are circular and of the same size in a plan view.

The ball-shaped bump electrodes are formed by first placing spherical solder balls of the same diameter on each pad and then melting the portions that contact each pad by performing heat treatment (reflow). The shape of the bump electrodes is selected according to the diameter of the pads that are to be contacted and the desired height after formation (height h [μm] of each bump electrode as viewed from the top surface of the passivation layer 35). In this embodiment 1, as shown in FIG. 1, the diameter r1 [μm] of each bump electrode in plan view is larger than the diameter of the corresponding pad (diameter r2 [μm] of the opening in the passivation layer 35). In the plan view shown in FIG. 2, each pad is indicated by a dashed line.

In the semiconductor device 1, for example, the first conductivity type may be N-type and the second conductivity type may be P-type, with the source region 14, the semiconductor substrate 32, the low concentration impurity layer 33, and the drain pull-up region 38 being N-type semiconductors, and the body region 18 being a P-type semiconductor.

In addition, in the semiconductor device 1, for example, the first conductivity type may be P type and the second conductivity type may be N type, with the source region 14, the semiconductor substrate 32, the low concentration impurity layer 33, and the drain pull-up region 38 being P type semiconductors, and the body region 18 being an N type semiconductor.

In the following explanation, the conductive operation of the semiconductor device 1 will be described assuming that the transistor 10 is a so-called N-channel transistor, in which the first conductivity type is N-type and the second conductivity type is P-type.

2. Operation of Vertical Field-Effect Transistor
3A and 3B are respectively a plan view and a perspective view of an approximate unit configuration of a transistor 10 repeatedly formed in the X direction and the Y direction in the semiconductor layer 40 of the semiconductor device 1. For ease of understanding, the semiconductor substrate 32 and the source electrode 11 are not shown in Figs. 3A and 3B. The Y direction is a direction parallel to the upper surface of the semiconductor layer 40 and in which the gate trench 17 extends. The X direction is a direction parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction.

3A and 3B, the transistor 10 has a connection portion 18a that electrically connects the body region 18 and the source electrode 11. The connection portion 18a is a region of the body region 18 in which the source region 14 is not formed, and contains the same second conductivity type impurity as the body region 18. The source region 14 and the connection portion 18a are alternately and periodically arranged in the Y direction.

In the semiconductor device 1, when a high voltage is applied to the drain electrode 81 and a low voltage is applied to the source electrode 11, and a voltage equal to or greater than the threshold value is applied to the gate electrode (gate conductor 15) with the source electrode 11 as a reference, an inversion layer is formed near the gate insulating film 16 in the body region 18, which becomes a conductive channel. As a result, a main current flows through the path of drain electrode 81-drain pull-up region 38-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conductive channel formed in the body region 18-source region 14-source electrode 11, and the semiconductor device 1 becomes conductive. In addition, a PN junction is formed at the contact surface between the low-concentration impurity layer 33 and the body region 18 in this conductive path, and functions as a body diode. In addition, since this main current flows through the metal layer 30, by making the metal layer 30 thicker, the cross-sectional area of the main current path is expanded, and the on-resistance of the semiconductor device 1 can be reduced.

[3. Dividing the semiconductor device into individual pieces and forming protrusions]
From here, the manufacturing process of the semiconductor device 1 and the formation of the protrusions 50 provided on the outer periphery of the metal layer 30 of the semiconductor device 1 will be described.

Figure 4 shows a simplified manufacturing process of the semiconductor device 1 in this embodiment 1. The structure of each vertical field effect transistor, which will later be divided into individual semiconductor devices 1, is formed in an array on a silicon wafer by step 501.

Next, in step 502, bump electrodes are formed for the source, drain, and gate. To form the bump electrodes, spherical solder balls are first placed on the source pad, drain pad, and gate pad, respectively, and then heat treatment is performed to form them.

Next, in step 503, the back side of the silicon wafer (corresponding to the semiconductor substrate 32 when viewed from the perspective of each semiconductor device 1 that will be individually separated later) is thinned. Next, in step 504, a multi-layered metal layer 30 is formed over the entire thinned back side of the silicon wafer. The metal layer 30 may include a first metal layer 30a and a second metal layer 30b. The first metal layer 30a is formed to a thickness of 8 μm or more, and is the thickest of the multi-layered metal layers 30. The second metal layer 30b may be, for example, less than 1 μm thick.

Next, in step 505, the silicon wafer is diced using a blade to separate each semiconductor device 1. At this time, the metal layer 30 formed on the entire back surface of the silicon wafer in step 504 is also cut along with the silicon wafer, but the metal layer 30 that is physically pushed out by the blade extends along the side of the semiconductor device 1. As a result, protrusions (so-called burrs) 50 that extend toward the lower back surface side of the semiconductor device 1 (in the -Z direction) are formed on the outer periphery of the metal layer 30 of the separated semiconductor device 1.

Figure 5 shows an oblique SEM image of the semiconductor device 1 in this embodiment 1, viewed from the exposed surface side of the metal layer 30. Since the metal layer 30 is provided on the entire back surface of the semiconductor device 1, when viewed in an individualized semiconductor device 1, the protrusions 50 are formed over the entire length of the four outer periphery sides of the metal layer 30. The protrusions 50 are formed because the semiconductor device 1 is individualized in step 505 using a blade. In this disclosure, it is important that step 505 is dicing using a blade. The reason for this will be explained below.

For example, in addition to dicing using a blade, dicing using a laser is also used. When using a laser, it is necessary to prevent the semiconductor material and metal debris (so-called debris) scattered by laser irradiation from adhering to the semiconductor device. For this reason, the surface of the semiconductor device is generally covered in advance with a protective film that prevents debris from adhering. However, in the semiconductor device 1 of this embodiment 1, the bump electrodes (source bump electrode 111, gate bump electrode 119, drain bump electrode 181) are provided in a ball-shaped shape with a certain height. For this reason, it is difficult to form a protective film to prevent debris from adhering so as to sufficiently cover the surface of the semiconductor device 1, including the bump electrodes.

The inventors have found that when the height of the bump electrode exceeds 100 μm, it becomes difficult for the protective film commonly used in the past to adequately cover the surface of the semiconductor device 1. This disclosure is directed to a semiconductor device 1 having a bump electrode with a height of 100 μm or more. Therefore, dicing using a blade is unavoidable for individualization. For this reason, it is very difficult to avoid the formation of protrusions 50 on the metal layer 30.

Incidentally, before or after mounting the semiconductor device 1 on a mounting board, the semiconductor device 1 may be subjected to ultrasonic cleaning in order to remove any foreign matter adhering thereto. When an impact such as that of ultrasonic cleaning is applied to the semiconductor device 1, not only the foreign matter but also the protrusions 50 formed on the outer periphery of the metal layer 30 may physically separate from the metal layer 30.

Figures 6A and 6B show cross-sectional SEM images of the protrusions 500 in Comparative Example 1 of this embodiment 1. Comparative Example 1 is an example of the protrusions 500 formed when the thickness of the metal layer 30 is 3 μm. The protrusions 500 shown in Figures 6A and 6B both have a width of less than 5 μm in cross-sectional view. As will be described later, when the width of the protrusions 500 in cross-sectional view is less than 5 μm, they tend to physically separate from the metal layer 30 due to impacts such as ultrasonic cleaning.

Even if the protrusion 500 has a shape as shown in FIG. 6A or FIG. 6B, it is unlikely that all of the protrusions 500 will fall off uniformly along the four outer periphery sides of the semiconductor device 1 due to ultrasonic cleaning. Typically, there will be some parts that remain connected to the metal layer 30 without falling off. As a result, as shown in FIG. 7A or FIG. 7B, the protrusion 500 often remains in the semiconductor device (metal layer 30) of Comparative Example 1 as a string-like semi-loose body 500a. FIGS. 7A and 7B are optical microscope images of the protrusion 500 formed in Comparative Example 1 of the present embodiment 1, viewed from the exposed surface side of the metal layer 30 after ultrasonic cleaning.

7A and 7B, semi-loose body 500a that does not fall off and remains in a string shape may come into contact with another component (not shown) adjacent to the semiconductor device of Comparative Example 1 on the mounting board on which the semiconductor device of Comparative Example 1 is mounted, forming an unintended conductive path. Also, on the mounting board on which the semiconductor device of Comparative Example 1 is mounted, semi-loose body 500a may fall off from the semiconductor device of Comparative Example 1 for some reason, and may cause a short circuit between other components unrelated to the semiconductor device of Comparative Example 1.

Taking these circumstances into consideration, the inventors have developed a structure that can reproducibly form wide protrusions 50 in cross-section so that the protrusions 50 will not come off the metal layer 30 and will remain stably connected to the metal layer 30 even when subjected to an impact such as ultrasonic cleaning.

That is, in a chip-size package type semiconductor device 1 capable of face-down mounting, a semiconductor substrate 32, a low-concentration impurity layer 33 formed on the semiconductor substrate 32, and the semiconductor substrate 32 and the low-concentration impurity layer 33 together referred to as a semiconductor layer 40, a vertical field-effect transistor 10 formed in the semiconductor layer 40, ball-shaped bump electrodes (source bump electrode 111, gate bump electrode 119, drain bump electrode 181) with a height of 100 μm or more formed on the surface side of the semiconductor layer 40, and a metal layer 30 having a multi-layer structure formed in contact with the entire surface of the back surface side of a conductive substrate 32, wherein a first metal layer 30a which is the thickest of the metal layers 30 is mainly composed of a first metal which is the most ductile of the metal types constituting the metal layer 30, the first metal layer 30a having a thickness of 8 μm or more, and in a plan view of the semiconductor layer 40, the outer periphery of the metal layer 30 is provided with a protrusion (burr) 50 which protrudes downwardly on the back surface side of the semiconductor substrate 32, and in a cross-sectional view of the protrusion 50, there are portions where the width of the protrusion 50 is 5 μm or more.

With such a structure, most of the metal layer 30 physically pushed out by the blade in step 505 becomes the first metal layer 30a. In other words, the protrusion 50 of the semiconductor device 1 can be composed mainly of the first metal constituting the first metal layer 30a. The first metal has the greatest ductility among the metals constituting the metal layer 30, and therefore can be flexibly deformed against physical external pressure. In addition, since the first metal layer 30a has a thickness of 8 μm or more, there is a large margin for it to be flexibly deformed against physical external pressure, and the protrusion 50 can be made into a wide shape that will not fall off due to the impact of ultrasonic cleaning.

Using Figures 8A to 8F, it will be explained that the protrusions 50 have a wide shape in this embodiment 1. Figures 8A to 8F show the step-by-step and schematic diagram of the singulation in step 505. The silicon wafer is attached to a dicing sheet 700 in advance, and a blade 600 is applied between the semiconductor devices 1 formed in an array on the silicon wafer. Note that the protrusions 50 shown in Figures 8C to 8F (not marked with a reference symbol in Figures 8C to 8F) do not necessarily accurately represent the component ratio of the first metal to the second metal.

As shown in Figure 8A, the blade 600 is lowered in the -Z direction, and cuts the silicon wafer and metal layer 30 while rotating and advancing. As shown in Figure 8B, in this embodiment 1, the first metal layer 30a is thick and the first metal has high ductility, so that the metal layer 30 is physically pushed out before the blade 600 reaches its lowest point. The dicing sheet 700 is made of an inherently flexible material and will not tear.

Figure 8C shows a schematic diagram of the blade 600 reaching its lowest point. At this time, the tip of the blade 600 penetrates the second metal layer 30b, so that the semiconductor device 1 is singulated at this stage. However, the extruded metal layer 30 (first metal layer 30a) flexibly deforms in the Z and X directions to reflect the shape of the tip of the blade 600. It is particularly important that the first metal layer 30a deforms in the X direction to reflect the rounded shape of the tip of the blade 600, and this deformation allows the width of the protrusion 50 to be increased. The second metal layer 30b changes the normal direction of the exposed surface while maintaining the stacked state with the first metal layer 30a.

If the first metal layer 30a is thin, there is little room for the first metal layer 30a to be physically pushed out and deformed even when the blade 600 reaches its lowest point, and the straight side of the blade 600 is simply reflected, and no effect of increasing the width of the protrusion 50 is obtained. The same is true when the ductility of the first metal is low.

8D and 8E are schematic diagrams showing the blade 600 being pulled up in the +Z direction, and at this time, the first metal layer 30a may be caught up in the pulling up of the blade 600 and may be partially pulled back toward the side of the semiconductor layer 40. As a result, in the individualized semiconductor device 1, a protrusion 50 is formed on the outer periphery of the metal layer 30, as shown in FIG. 8F.

Figures 9A and 9B show cross-sectional SEM images of a protrusion 50 that is a typical example of this embodiment 1. Figure 9B is an enlarged view of the white framed area shown in Figure 9A. Using Figure 9B, we clarify the definition of how to view the structure of the protrusion 50 in a cross-sectional view. Figure 9B shows an example of a cross-sectional view including the X direction and the Z direction, but a cross-section of the protrusion 50 in a different direction may be used.

The dashed line A in Figure 9B is the interface between the semiconductor substrate 32 and the metal layer 30. The semiconductor substrate 32 is typically silicon. The interface between the semiconductor substrate 32 and the metal layer 30 is relatively flat, and therefore the dashed line A can be seen as a straight line with few irregularities in cross section.

The dashed line B in FIG. 9B is an approximate interface between the first metal layer 30a and the second metal layer 30b. The exact interface between the first metal layer 30a and the second metal layer 30b is often not as flat as the interface between the semiconductor substrate 32 and the metal layer 30, and it may be difficult to say that the interface between the first metal layer 30a and the second metal layer 30b is a straight line in cross-sectional view. However, for convenience, the dashed line B may be placed parallel to the dashed line A so as to pass through as many areas as possible in the X direction where the difference in contrast caused by the difference between the first metal and the second metal becomes large.

In the semiconductor device 1 of this embodiment 1 (FIG. 9B), the first metal layer 30a is in contact with the semiconductor substrate 32, so the distance in the Z direction between the dashed lines A and B is the thickness of the first metal layer 30a. For reference, the actual interface between the first metal layer 30a and the second metal layer 30b is shown by a gray solid line in FIG. 9B, which is along the area where the difference in contrast caused by the difference between the first metal and the second metal becomes large.

Dashed line C in Figure 9B is the exposed surface of the second metal layer 30b in the -Z direction. In a cross-sectional view, the exposed surface of the second metal layer 30b may not be said to be in a straight line, similar to the interface between the first metal layer 30a and the second metal layer 30b. However, for convenience, dashed line C may be placed parallel to dashed lines A and B, and pass through as many areas of the second metal layer 30b exposed in the -Z direction as possible in the X direction. Therefore, the distance in the Z direction between dashed lines B and C is the thickness of the second metal layer 30b.

The dashed line D in Figure 9B is the side of the semiconductor layer 40. The side of the semiconductor layer 40 may be partially covered by the metal constituting the metal layer 30 near the interface with the metal layer 30, but as it moves away from the metal layer 30 in the +Z direction, a side where only the semiconductor layer 40 is exposed will eventually appear. The reason why the side of the semiconductor layer 40 is partially covered by the metal constituting the metal layer 30 near the interface with the metal layer 30 is that during dicing in step 505, the metal constituting the metal layer 30 may be rolled back in the +Z direction due to the influence of the push-out or pull-back of the blade 600 in the Z direction or the rotation direction of the blade 600 at that time.

The solid line E in Fig. 9B is a reference that defines the position of the base of the protrusion 50. It is a line that is parallel to the dashed line A and passes through the point inside the protrusion 50 where the normal direction of the exposed surface of the second metal layer 30b changes from the -Z direction to another direction (the -X direction in Fig. 9B).

9B is the lowest point that defines the length of the protrusion 50. That is, it is a line that passes through the point where the protrusion 50 reaches its lowest point in the -Z direction and is parallel to the solid line E. In this disclosure, the distance in the Z direction between the solid lines E and F is defined as the length of the protrusion 50.

Solid line G in Figure 9B is a reference for defining the inner position of protrusion 50. It is a line that passes through the point inside protrusion 50 where the normal direction at the exposed surface of second metal layer 30b changes from the -Z direction to another direction (the -X direction in Figure 9B), and is perpendicular to solid line E. In Figure 9B, if solid line G is extended in the +Z direction, it almost coincides with dashed line D, which is the side surface of semiconductor layer 40, but dashed line D and solid line G may or may not coincide.

9B is a reference for defining the outer position of the protrusion 50. The solid line H is a line parallel to the solid line G, passing through the farthest point on the outside of the protrusion 50 from the side surface of the semiconductor layer 40 (dashed line D) in a direction perpendicular to the side surface of the semiconductor layer 40 (X direction). In this disclosure, the distance in the X direction between the solid lines G and H is defined as the width of the protrusion 50, or the width of the base of the protrusion 50.

In this disclosure, the term metal layer 30 includes the protrusion 50. However, when referring to the area of the metal layer 30 that is properly stacked with the semiconductor layer 40 in the Z direction, the protrusion 50 is not included. In other words, the area of the metal layer 30 that is properly stacked with the semiconductor layer 40 in the Z direction refers to an area that is further inside the semiconductor device 1 than the reference (solid line G) that defines the inner position of the protrusion 50 or the side surface (dashed line D) of the semiconductor layer 40 in the X direction. For example, in FIG. 9B, the area corresponds to the area that is more inside the semiconductor device 1 than the solid line G.

The term protrusion 50 refers to the portion of the metal layer 30 that is outside the reference that defines the inner position of the protrusion 50. In FIG. 9B, it is the portion outside the solid line G, and necessarily includes the portion that protrudes in the -Z direction beyond the solid line E. The metal portion that partially covers the side surface of the semiconductor layer 40 (dashed line D) is also included in the term protrusion 50.

In order to make the protrusions 50 resistant to impacts such as ultrasonic cleaning, it is preferable to make the width of the base wider in cross section. FIG. 10 shows the shape of the protrusions 50 formed when silver (Ag) is used for the first metal layer 30a and the thickness of the Ag is changed as an example of this embodiment 1. The incidence of the protrusions 50 falling off after ultrasonic cleaning is also shown. Level 1 is when the second metal layer 30b is not formed and the Ag of the first metal layer 30a is exposed on the back side of the semiconductor device 1. Level 2 is when nickel (Ni) with a thickness of less than 1 μm is used as the second metal layer 30b, and the first metal layer 30a with a thickness of 3 μm is Comparative Example 1.

Ag is one of the most ductile metals, and Ni has lower ductility than Ag. Therefore, as shown in Figures 8A to 8F, it has the conditions to easily make the width of the protrusion 50 thicker in cross section. However, as shown in Figure 10, when the thickness of Ag, which is the first metal layer 30a, is 3 μm (Comparative Example 1), the width of the protrusion 50 formed by singulation in step 505 is 2.4 μm, and the shape is vulnerable to impact. The incidence rate of the protrusion 50 falling off after ultrasonic cleaning was 19%, and the possibility that the protrusion 50 may cause a short circuit after mounting could not be excluded.

In contrast, when the thickness of the Ag of the first metal layer 30a is 8 μm, the width of the protrusion 50 is stable at 5.0 μm or more, regardless of whether it is level 1 or level 2, and no falling off occurs after ultrasonic cleaning. The thicker the Ag of the first metal layer 30a, the wider the protrusion 50 tends to be. In other words, it can be said that the falling off of the protrusion 50 after ultrasonic cleaning can be prevented as long as the thickness of the first metal layer 30a is 8 μm or more, regardless of the presence or absence of the second metal layer 30b or the thickness of the second metal layer 30b. Therefore, regardless of the presence or thickness of the second metal layer 30b, it is desirable that the thickness of the first metal layer 30a is 8 μm or more.

11 shows, as Comparative Example 2 of the present embodiment 1, the shape of the protrusion 50 formed when the first metal layer 30a is made of nickel (Ni) having a thickness of 10 μm, the second metal layer 30b is not formed, and the Ni of the first metal layer 30a is exposed on the back side of the semiconductor device 1. The incidence of the protrusion 50 falling off after ultrasonic cleaning is also shown.

Ni is not particularly ductile among metals. Therefore, even though it has a thickness of 10 μm, the width of the protrusions 50 formed by singulation in step 505 is only about 1.0 μm, making it vulnerable to impacts. The incidence rate of protrusions 50 falling off after ultrasonic cleaning was high at 69%, and the results showed that the protrusions 50 are highly likely to become a cause of short circuits after mounting.

Therefore, in order to provide the protrusions 50 with sufficient resistance to shocks such as those caused by ultrasonic cleaning, the semiconductor device 1 has a multi-layered metal layer 30 formed in contact with the entire back surface of the semiconductor substrate 32, and the thickest first metal layer 30a is preferably made mainly of the first metal, which has the highest ductility among the metals constituting the metal layer 30, and the first metal layer 30a is desirably 8 μm or thicker. In the case of such a shape, the width of the protrusions 50 that appear after singulation in step 505 can be stably made thicker, at least 5 μm.

The characteristics of the protrusion 50 of this embodiment 1 will be described by comparing a typical example (FIG. 9B) with Comparative Example 1 (FIGS. 6A and 6B). As explained above, the width of the protrusion 50 formed in this embodiment 1 is consistently 5 μm or more. The reason for the wide width is that the protrusion 50 formed in this embodiment 1 has a shape in which the first metal layer 30a at the base of the protrusion 50 bulges outward from the side surface of the semiconductor layer 40 (dashed line D in FIG. 9B) in a cross-sectional view.

9B, in a cross-sectional view of the protrusions 50, the tips of the protrusions 50 are shaped so that they are the lowest point below the rear surface side of the semiconductor substrate 32 (in the -Z direction). In contrast, in FIG. 6A in Comparative Example 1, the protrusions 50 are not linear but winding in the -Z direction, so the tips of the protrusions 50 do not coincide with the lowest point in the -Z direction. If the protrusions 50 are not linear but winding in the -Z direction, the surface of the protrusions 50 will be subjected to the impact of the ultrasonic cleaning from all directions, which is undesirable as it increases the likelihood of them falling off.

Also, according to Figure 9B, in a cross-sectional view of protrusion 50, in the section from the base to the tip of protrusion 50, there is no portion where the width of protrusion 50 decreases once and then increases again in the direction toward the tip (the lower back surface side of semiconductor device 1). In contrast, in Figure 6B in Comparative Example 1, protrusion 500 has a shape in which the width is narrow at the base, but the width becomes wider in the direction toward the lowest point. In other words, in Comparative Example 1 (Figure 6B), protrusion 500 has a shape in which the width is narrower at the base, making it particularly vulnerable to shocks such as ultrasonic cleaning.

As shown by the gray solid line in Figure 9B, in this embodiment 1, the multi-layer structure of the metal layer 30 is maintained in the protrusion 50. In this disclosure, in a planar view of the semiconductor layer 40, the side facing the center of the semiconductor device 1 is called the inside, and the side facing the outer periphery of the semiconductor device 1 is called the outside. It can be seen that the second metal layer 30b having a thickness of less than 1 µm is exposed on the inside side of the protrusion 50, and the first metal layer 30a is exposed on the outside side of the protrusion 50.

Here, the effect of providing the second metal layer 30b will be explained. As mentioned above, in order to enjoy the effect of the present disclosure, the thickness of the first metal layer 30a, which is mainly composed of the first metal that has the greatest ductility among the metal layers 30, is required to be at most 8 μm or more. The second metal layer 30b may or may not be provided, and even if the second metal layer 30b is provided, there is no restriction on its thickness.

However, by providing the second metal layer 30b and appropriately selecting the ductility of the second metal, it is possible to prevent the length of the protrusion 50 from becoming unnecessarily long. Comparing the shape of the protrusion 50 shown in FIG. 10 between level 1 and level 2, the length of the protrusion 50 is shorter in level 2, in which Ni is deposited to a thickness of less than 1 μm as the second metal layer 30b. This is because the ductility of the second metal (Ni), which is the main component of the second metal layer 30b, is not large, and the second metal layer 30b suppresses the first metal layer 30a from being unnecessarily stretched during the singulation in step 505.

From the viewpoint of preventing falling off and avoiding short circuits, it is preferable that the length of the protrusion 50 is not unnecessarily long. As a result of the study by the inventors, when the first metal layer 30a is formed of Ag or Cu with a thickness of 10 μm, and the second metal layer 30b is formed so as to be laminated in direct contact with the first metal layer 30a, if the second metal is selected to have the same ductility as Ni, the length of the protrusion 50 can be kept to less than 20 μm even if the thickness is less than 1 μm.

In the results of level 2 shown in Figure 10, the length of the protrusions 50 is all less than 20 μm, and no falling off occurs after ultrasonic cleaning. For this reason, it is desirable for the length of the protrusions 50 protruding downward toward the rear surface side of the semiconductor substrate 32 to be less than 20 μm.

That is, the metal layer 30 has a second metal layer 30b, which is laminated in contact with the first metal layer 30a, and in a plan view, when the side facing the center of the semiconductor device 1 is defined as the inside and the side facing the outer periphery of the semiconductor device 1 is defined as the outside, the inner side of the protrusion 50 exposes the second metal layer 30b having a thickness of less than 1 μm, and the outer side of the protrusion 50 exposes the first metal layer 30a, and it is desirable for the semiconductor device 1 to have a length of the protrusion 50 protruding downwardly from the rear surface side of the semiconductor substrate 32 of 20 μm or less.

8A to 8F, in step 505, the portion of the first metal layer 30a that is physically pushed out by the blade 600 becomes the main component of the protrusion 50. Therefore, there is a correlation between the thickness of the first metal layer 30a required to increase the width of the protrusion 50 and the characteristics that appear in the shape of the protrusion 50 in cross section. This correlation is explained below.

Figure 12A shows a cross-sectional SEM image of a protrusion 50, which is another typical example of this embodiment 1. The structure shown in Figure 12A is a protrusion formed by singulating a semiconductor device 1 in which Ag is deposited to a thickness of 10 μm as the first metal layer 30a, and Ni is deposited to a thickness of less than 1 μm as the second metal layer 30b that is formed in contact with the first metal layer 30a. The width of the protrusion 50 defined using Figure 9B is Wb [μm], the length of the protrusion 50 is Hb [μm], and the thickness of the first metal layer 30a is M1 [μm].

Furthermore, if the distance in the X direction from the side surface of the semiconductor layer 40 (dashed line D) to the position (solid line H) that protrudes most outwardly of the semiconductor device 1 is taken as L1/2 [μm], then L1 can be considered to be approximately the width of the blade 600 used in singulation in step 505. By applying the blade 600, a width of L1 is removed from the silicon wafer in the X direction, and when only one side of the semiconductor device 1 provided on each side of the blade 600 is viewed, a trace of L1/2 being removed remains.

Therefore, when viewed from only one side, the amount of first metal layer 30a physically pushed out by blade 600 in step 505 (the concept of amount will be discussed in cross-section here, assuming that the amount is uniform in the depth direction of the page in FIG. 12A ) is M1×L1/2 [μm ² ], which can be seen to be transformed into protrusion 50 below the reference length of protrusion 50 (solid line E). Because the shape of protrusion 50 below solid line E is considered to be roughly triangular in cross-section, the amount of protrusion 50 formed is Wb×Hb/2.

Since these should be approximately equal, the relationship M1 x L1/2 ≒ Wb x Hb/2 holds. Therefore, the relationship M1 = Wb x Hb/L1 holds approximately. Since it is desirable for the width Wb of the protrusion 50 to have a relationship of Wb ≧ 5 μm, in this embodiment 1, it is sufficient that the thickness of the first metal layer 30a is such that the relationship M1 ≧ 5 x Hb/L1 holds. If this relationship holds, the protrusion 50 can be made stably wide.

That is, in a cross-sectional view of the protrusion 50, at the base of the protrusion 50, the position where the first metal layer 30a bulges outward most from the side of the semiconductor layer 40, if twice the length of the protrusion 50 bulging outward from the side of the semiconductor layer 40 in a direction perpendicular to the side of the semiconductor layer 40 at that position is defined as L1 [μm], the width of the base of the protrusion 50 is defined as Wb [μm], and the length of the protrusion 50 is defined as Hb [μm], then the thickness of the first metal layer 30a may be 5×Hb/L1 [μm] or greater.

Figure 12B shows a more precise depiction of the above relationship. In cross-sectional view, the curved shape that appears on the outer side of the protrusion 50 near the semiconductor layer 40 can be seen as reflecting the rounded shape of the tip of the blade 600. When the curved shape that appears downward and outward from the side of the semiconductor layer 40 (dashed line D) near the semiconductor layer 40 in cross-sectional view is approximated by a polynomial up to the second power, the distance from the side of the semiconductor layer 40 (dashed line D) to the position (point J in Figure 12B) where the approximation curve is minimal (i.e., the differential coefficient is zero) is L2/2 [μm], and L2 can be considered to be approximately the width of the blade 600 used in the singulation in step 505.

Therefore, the relationship M1 x L2/2 ≒ Wb x Hb/2 holds, and since it is desirable for the width Wb of the protrusion 50 to satisfy the relationship Wb ≧ 5 μm, it is desirable for the relationship M1 ≧ 5 x Hb/L2 to hold.

That is, in a cross-sectional view of the protrusion 50, the outer side surfaces of the metal layer 30 and the protrusion 50 have a curved shape originating from the side surface of the semiconductor layer 40, and if L2 [μm] is twice the distance in a direction perpendicular to the side surface of the semiconductor layer 40 from the side surface of the semiconductor layer 40 to the position where the approximate curve obtained by polynomial approximation of the curved shape is at a minimum, the width of the base of the protrusion 50 is Wb [μm], and the length of the protrusion 50 is Hb [μm], then the thickness of the first metal layer 30a may be 5×Hb/L2 [μm] or more.

However, if the metal layer 30 is made thicker, warping of the silicon wafer may become significant after the metal (metal layer 30) is deposited on the back surface of the silicon wafer in step 504 of the manufacturing process shown in Figure 4. If the silicon wafer warps significantly, it becomes difficult to proceed with the subsequent steps, which is inconvenient. In order to minimize warping of the silicon wafer, it is effective to not thin the silicon wafer as much as possible in the thinning process of the silicon wafer in step 503.

According to the results of the study by the present inventors, when the first metal layer 30a in the metal layer 30 is formed with a thickness of 8 μm and mainly composed of Ag, it is found that if the thickness of the semiconductor substrate 32 is 150 μm or more, the warpage occurring in the silicon wafer can be suppressed to a maximum of less than 7 mm. If the warpage of the silicon wafer is less than 7 mm, the steps after step 504 can be smoothly carried out.

It is also desirable to leave the semiconductor substrate 32 thick, provided that it does not exceed the allowable product thickness for the semiconductor device 1. An upper limit of 400 μm is often required for the product thickness. Taking into account a margin, it is desirable for the thickness of the semiconductor device 1 to be 390 μm or less.

That is, in the semiconductor device 1 in this embodiment 1, it is desirable that the thickness of the semiconductor substrate 32 is 150 μm or more, and the thickness of the semiconductor device 1 is 390 μm or less. More specifically, it is desirable that the thickness of the semiconductor substrate 32 is 150 μm or more and 280 μm or less. The upper limit of 280 μm is a value obtained by subtracting, with a margin taken into consideration, the minimum height of the ball-type bump electrode of 100 μm and the minimum thickness of the metal layer 30 of 8 μm from the upper limit thickness of the semiconductor device 1 of 390 μm.

The semiconductor device 1 in this embodiment 1 is characterized in that the height of the ball-shaped bump electrodes (source bump electrode 111, gate bump electrode 119, drain bump electrode 181) is at least 100 μm. The height of the bump electrodes may be required to be as large as 150 μm or more, and in such cases, the height of each bump electrode may be greater than the thickness of the semiconductor substrate 32. Below, the characteristics of the case where the height of each bump electrode is greater than the thickness of the semiconductor substrate 32 will be described.

When the height h [μm] of each bump electrode is greater than the thickness of the semiconductor substrate 32, as shown in Figures 1 and 2, typically, the diameter r1 [μm] of each bump electrode before mounting is greater than the diameter r2 [μm] of each pad with which each bump electrode contacts (r1>r2). However, depending on the magnitude relationship between r1 and r2 and the size of the semiconductor layer 40 in a plan view, the bump electrode may protrude from the outer periphery of the semiconductor device 1 when the semiconductor device 1 is mounted face-down on the mounting substrate. If the bump electrode protrudes from the outer periphery of the semiconductor device 1, it is undesirable because it increases the possibility of contacting the metal layer 30 and causing a short circuit. Figure 13 shows a cross-sectional SEM image of the semiconductor device 1 in this embodiment 1, which has a square shape with a side length of 800 μm (0.8 mm) in a plan view, after being mounted face-down on the mounting substrate.

As shown in Figure 13, the bump electrodes of the semiconductor device 1 are crushed by a certain amount in the vertical direction (+Z direction) when mounted face-down on the mounting substrate 800. As a result, the bump electrodes are pushed out in the horizontal direction (±X direction). If the diameter of the bump electrodes after mounting is r3 [μm], then r3 > r1. In the semiconductor device 1 shown in Figure 13, the diameter r1 of the bump electrodes before mounting was 0.26 μm, but it can be seen that the diameter r3 of the bump electrodes after mounting has expanded to at least 0.29 μm.

The inventors' study revealed that the amount of the pad pushed out laterally (r3-r2) is up to 5 times the difference (r1-r2) between the diameter of the bump electrode and the pad diameter before mounting. If the distance from the outer periphery of each pad (source pad, gate pad, drain pad) of the semiconductor device 1 to the outer periphery of the semiconductor layer 40 closest to it in a plan view is d [μm], then it can be said that each pad should be installed in advance so that the relationship d ≧ (r3-r2)/2 ≧ 5 × (r1-r2)/2 is satisfied for the semiconductor device 1. The right side of the relational expression is divided by 2 because only one side of the amount of the bump electrode pushed out in a cross-sectional view is taken into consideration.

If each pad is positioned so that the above relationship is satisfied, even after the semiconductor device 1 is mounted face-down, the bump electrodes (source bump electrode 111, gate bump electrode 119, drain bump electrode 181) will not protrude from the outer periphery of the semiconductor layer 40 in a planar view, thereby reducing the possibility of a short circuit.

However, there are cases where it is required to make the area of the semiconductor device 1 particularly small while ensuring that the height of the bump electrode is 150 μm or more. Typically, it is required that the semiconductor device 1 (semiconductor layer 40) is a square with a side length of 800 μm (0.8 mm) or less in a plan view. If it is necessary to form three types of bump electrodes, namely, the source bump electrode 111, the gate bump electrode 119, and the drain bump electrode 181, it is natural that the semiconductor device 1 is a square with four bump electrodes as shown in FIG. 2, as long as it is required to make the semiconductor layer 40 as small as possible.

When forming relatively large bump electrodes within the limited area of the semiconductor device 1, special care must be taken to ensure that the bump electrodes do not come into contact with each other. In plan view, it is preferable to ensure a dimension of at least 2×d between adjacent bump electrodes. Therefore, if the semiconductor layer 40 is square in plan view with a side length of L [μm], two bump electrodes are formed along one side of the semiconductor layer 40, so it is preferable that the relationship L≧2×r2+4×d≧10×r1-8×r2 holds.

It is desirable to select the diameter r1 of the bump electrode and the diameter r2 of the pad so that the above relationship is established for the length L of one side of the desired semiconductor device 1. For example, if the height h of the bump electrode is required to be 190 μm under the constraint of the length L of one side of the semiconductor layer 40 being 780 μm (0.78 mm), the diameter r1 of the bump electrode will be approximately 260 μm. Then, based on the above relationship, it is desirable for the diameter r2 of the pad on which the bump electrode is placed to be 228 μm or more.

That is, the semiconductor device 1 in the present disclosure is a chip-size package type semiconductor device 1 capable of face-down mounting, and is preferably a semiconductor device 1 that includes a semiconductor substrate 32, a low-concentration impurity layer 33 formed on the semiconductor substrate 32, and ball-shaped bump electrodes (source bump electrode 111, gate bump electrode 119, drain bump electrode 181) having a height of 150 μm or more formed on the surface side of the semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40, the height of the ball-shaped bump electrodes being greater than the thickness of the semiconductor substrate 32, the semiconductor layer 40 being a square with a side length of L [μm] in a planar view of the semiconductor layer 40, and the diameter of the ball-shaped bump electrode in a planar view being r1 [μm] and the diameter of the contact surface between the ball-shaped bump electrode and the surface of the semiconductor layer 40 being r2 [μm], where r1>r2 and the relationship L≧10×r1-8×r2 holds.

With such a structure, the height of the bump electrodes in a small semiconductor device 1 can be ensured to be 150 μm or more, and even after face-down mounting, the bump electrodes (source bump electrode 111, gate bump electrode 119, drain bump electrode 181) do not protrude from the outer periphery of the semiconductor layer 40 in a planar view, and contact between the bump electrodes can be prevented.

A semiconductor device equipped with the vertical field effect transistor of the present invention can be widely used as a device for controlling the conduction state of a current path.

1 Semiconductor device 10 Vertical field effect transistor (transistor)
11 source electrode 12, 13, 82, 83 portion 14 source region 15 gate conductor 16 gate insulating film 17 trench 18 body region 18a connection region 30 metal layer 30a first metal layer 30b second metal layer 32 semiconductor substrate 33 low concentration impurity layer or drift layer 34 interlayer insulating film 35 passivation layer 38 drain pull-up region 40 semiconductor layer 50, 500 protrusion (burr)
81 drain electrode 111 source bump electrode 119 gate bump electrode 181 drain bump electrode 500a semi-free body 600 blade 700 dicing sheet 800 mounting substrate 501 step 502 step 503 step 504 step 505 step A1 active region A2 control region A3 drain conduction region

Claims (7)

A chip size package type semiconductor device capable of face-down mounting,
A semiconductor substrate;
a semiconductor layer formed on the semiconductor substrate;
a vertical field effect transistor formed in the semiconductor layer;
a ball-shaped bump electrode having a height of 100 μm or more formed on the front surface side of the semiconductor layer;
a multi-layered metal layer formed in contact with the entire surface of the back surface of the semiconductor substrate;
The first metal layer, which is the thickest of the metal layers, is mainly composed of a metal having ductility equal to or greater than that of Ag ,
The first metal layer has a thickness of 8 μm or more,
When viewed from above, the semiconductor layer has an outer periphery of the metal layer that has a protrusion protruding downwardly toward a rear surface of the semiconductor substrate,
In a cross-sectional view of the protrusion, the protrusion has a width of 5 μm or more at a portion,
the metal layer comprises a second metal layer;
the second metal layer is laminated and formed in contact with the first metal layer;
When the side facing the center of the semiconductor device is defined as an inner side and the side facing the outer periphery of the semiconductor device is defined as an outer side in the plan view, the second metal layer having a thickness of less than 1 μm is exposed on the inner side surface of the protrusion at the location,
At the location, the outer side surface of the protrusion has the first metal layer exposed;
a length of said protrusion protruding downwardly from said rear surface side of said semiconductor substrate at said portion is 20 μm or less. 2 . The semiconductor device according to claim 1 , wherein in a cross-sectional view of the protrusion at the location, the protrusion has a shape in which the first metal layer constituting the protrusion bulges outward beyond a side surface of the semiconductor layer. In a cross-sectional view of the protrusion at the location, when the length is from the side surface of the semiconductor layer to the position where the first metal layer constituting the protrusion bulges outward most in a direction perpendicular to the side surface of the semiconductor layer, L1 [μm] is taken as twice the length, and the length of the protrusion is taken as Hb [μm].
The semiconductor device according to claim 2 , wherein the first metal layer has a thickness of 5×Hb/L1 [μm] or more. In a cross-sectional view of the protrusion at the location, the outer side surface of the first metal layer constituting the protrusion in a portion adjacent to the semiconductor layer has a curved shape originating from a side surface of the semiconductor layer,
Let L2 [μm] be twice the length from the side surface of the semiconductor layer to a position where an approximation curve obtained by polynomial approximation of the curved shape is at a minimum in a direction perpendicular to the side surface of the semiconductor layer, and let Hb [μm] be the length of the protrusion.
The semiconductor device according to claim 2 , wherein the first metal layer has a thickness of 5×Hb/L2 [μm] or more. 2. The semiconductor device according to claim 1, wherein in a cross-sectional view of the protrusion at the location, the protrusion does not have a portion whose width increases downward from the base to the tip of the protrusion on the rear surface side of the semiconductor substrate. The semiconductor device according to claim 1 , wherein in a cross-sectional view of the protrusion at the location, a tip of the protrusion is a lowest point below the rear surface side of the semiconductor substrate. The thickness of the semiconductor substrate is 150 μm or more,
The semiconductor device according to claim 1 , wherein the thickness of the semiconductor device is 390 μm or less.

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