JP2017143214A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP2017143214A
JP2017143214A JP2016024804A JP2016024804A JP2017143214A JP 2017143214 A JP2017143214 A JP 2017143214A JP 2016024804 A JP2016024804 A JP 2016024804A JP 2016024804 A JP2016024804 A JP 2016024804A JP 2017143214 A JP2017143214 A JP 2017143214A
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metal
semiconductor device
electrode
forming
semiconductor substrate
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JP6736902B2 (en
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真哉 赤尾
Masaya Akao
真哉 赤尾
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method capable of preventing yield deterioration caused by formation of a junction electrode by plating.SOLUTION: A semiconductor device manufacturing method comprises: a step of forming impurity layers 20, 22, 24 on a top face side of a semiconductor substrate 10; a step of forming an insulation film 30 having an opening on the top face of the semiconductor substrate; a step of forming by a CVD method, plug metal 34 which covers the insulation film by having plugging metal 34A which plugs the opening of the insulation film and protection metal 34B which links to the plugging metal and is located on the insulation film; a step of forming an extraction electrode 36 on the plug metal by sputtering or a PVD method; and a step of forming on the extraction electrode, a plating layer 38 having a junction electrode 39 by a plating method.SELECTED DRAWING: Figure 1

Description

本発明は、例えばＭＯＳＦＥＴ又はＩＧＢＴ(Insulated Gate Bipolar Transistor)などの半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a semiconductor device such as a MOSFET or an IGBT (Insulated Gate Bipolar Transistor).

特許文献１には、トレンチゲート電極を有する半導体装置が開示されている。地球環境保護の観点から、エネルギーを効率良く利用するために、電力システムは小型化と高出力化を続けている。電力システムに搭載されるパワーデバイスに要求される電流密度は上昇を続け、放熱性能の向上と、接合部の低抵抗化が求められている。これらの目的を達成するため、上面と下面の両面において、引出電極と、引出電極の後に形成される接合電極とを有するパワーデバイスが標準化しつつある。これらの接合電極により、パワーデバイスの上面をリードフレームに直接接合し、パワーデバイスの下面をヒートスプレッダに直接接合できるので、放熱性能の向上と、接合部の低抵抗化を計ることができる。   Patent Document 1 discloses a semiconductor device having a trench gate electrode. From the viewpoint of protecting the global environment, in order to efficiently use energy, power systems continue to be reduced in size and output. The current density required for power devices mounted in power systems continues to rise, and there is a need for improved heat dissipation performance and lower resistance at the junction. In order to achieve these objects, power devices having an extraction electrode and a bonding electrode formed after the extraction electrode are being standardized on both the upper surface and the lower surface. With these bonding electrodes, the upper surface of the power device can be directly bonded to the lead frame, and the lower surface of the power device can be directly bonded to the heat spreader. Therefore, it is possible to improve the heat dissipation performance and reduce the resistance of the bonding portion.

特開２００２−１５８３５４号公報JP 2002-158354 A

パワーデバイスの引出電極の表面に、めっき法で接合電極を積層することがある。めっき法ではウエハを液槽に浸漬するため、めっき処理に使用している薬液が引出電極の表層に存在する僅かな欠陥から下地のＭＯＳ構造等に染み込んでＭＯＳ構造等を腐食させる問題があった。半導体装置の内部構造に腐食が生じることによる歩留まり低下があった。   A joining electrode may be laminated on the surface of the extraction electrode of the power device by a plating method. In the plating method, since the wafer is immersed in the liquid bath, there is a problem that the chemical solution used in the plating process penetrates into the underlying MOS structure from a slight defect present on the surface of the extraction electrode and corrodes the MOS structure. . There was a decrease in yield due to the occurrence of corrosion in the internal structure of the semiconductor device.

本発明は、上述のような課題を解決するためになされたもので、めっき法で接合電極を形成することによる歩留まり低下を防止できる半導体装置の製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent a decrease in yield due to formation of a bonding electrode by a plating method.

本願の発明に係る半導体装置の製造方法は、半導体基板の上面側に不純物層を形成する工程と、該半導体基板の上面に開口を有する絶縁膜を形成する工程と、該絶縁膜の開口を埋める埋め込み金属と、該埋め込み金属とつながり、該絶縁膜の上に位置する保護金属と、を有することで該絶縁膜を覆うプラグ金属をＣＶＤ法で形成する工程と、該プラグ金属の上に、スパッタリング法又はＰＶＤ法により引出電極を形成する工程と、該引出電極の上に、めっき法により接合電極を形成する工程と、を備えたことを特徴とする。   A method of manufacturing a semiconductor device according to the present invention includes a step of forming an impurity layer on an upper surface side of a semiconductor substrate, a step of forming an insulating film having an opening on the upper surface of the semiconductor substrate, and filling the opening of the insulating film. Forming a plug metal that covers the insulating film by having a buried metal and a protective metal connected to the buried metal and located on the insulating film, and sputtering the plug metal on the plug metal; And a step of forming an extraction electrode by a PVD method and a step of forming a bonding electrode by a plating method on the extraction electrode.

本発明によれば、めっき液に溶解しないプラグ金属をセル領域の全域に形成するので、プラグ金属の上の引出電極、及びプラグ金属の下のバリアメタルの欠陥によってめっき液がバリアメタルの下に浸み込むことを防止できる。   According to the present invention, since the plug metal that does not dissolve in the plating solution is formed in the entire cell region, the plating solution is placed under the barrier metal due to the defect of the extraction electrode on the plug metal and the barrier metal under the plug metal. Infiltration can be prevented.

半導体装置の断面図である。It is sectional drawing of a semiconductor device. 引出電極の欠陥等を示す図である。It is a figure which shows the defect etc. of an extraction electrode. 半導体装置の平面図である。It is a top view of a semiconductor device. セル領域の拡大図である。It is an enlarged view of a cell area. セル領域の拡大図である。It is an enlarged view of a cell area. 半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of a semiconductor device. 半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of a semiconductor device. 半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of a semiconductor device. 半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of a semiconductor device. 半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of a semiconductor device. 比較例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of a comparative example. 比較例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of a comparative example.

本発明の実施の形態に係る半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態．
図１は、本発明の実施の形態に係る半導体装置の製造方法で製造された半導体装置の断面図である。この半導体装置はＩＧＢＴチップである。この半導体装置は例えばシリコンを材料とする半導体基板１０を備えている。半導体基板１０にはトレンチゲート電極１２が形成されている。具体的に言えば、半導体基板１０の上面側には、半導体基板１０にストライプ状に彫られた溝を埋めるトレンチゲート電極１２が設けられている。トレンチゲート電極１２の材料は例えばポリシリコンである。トレンチゲート電極１２と半導体基板１０の間にはゲート酸化膜１４が設けられている。 Embodiment.
FIG. 1 is a cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention. This semiconductor device is an IGBT chip. This semiconductor device includes a semiconductor substrate 10 made of, for example, silicon. A trench gate electrode 12 is formed on the semiconductor substrate 10. Specifically, a trench gate electrode 12 is provided on the upper surface side of the semiconductor substrate 10 so as to fill a groove carved in a stripe shape in the semiconductor substrate 10. The material of the trench gate electrode 12 is, for example, polysilicon. A gate oxide film 14 is provided between the trench gate electrode 12 and the semiconductor substrate 10.

半導体基板１０の上面側には不純物層２０、２２、２４が形成されている。不純物層２０はｐ型層であり、不純物層２２はｎ型層であり、不純物層２４はｐ型層である。不純物層２０、２２、２４は複数のトレンチゲート電極１２の間に設けられている。   Impurity layers 20, 22, and 24 are formed on the upper surface side of the semiconductor substrate 10. The impurity layer 20 is a p-type layer, the impurity layer 22 is an n-type layer, and the impurity layer 24 is a p-type layer. The impurity layers 20, 22, and 24 are provided between the plurality of trench gate electrodes 12.

トレンチゲート電極１２の頭頂部は絶縁膜３０で覆われている。絶縁膜３０は、トレンチゲート電極１２の上及び不純物層２２、２４の上にある。絶縁膜３０の材料は例えばシリコン酸化膜である。絶縁膜３０は平面視でストライプ状の開口を有している。絶縁膜３０はバリアメタル３２で覆われている。バリアメタル３２は、絶縁膜３０の開口底面に露出した不純物層２４に接している。バリアメタル３２の材料は例えばＴｉ又はＴｉＮである。   The top of the trench gate electrode 12 is covered with an insulating film 30. The insulating film 30 is on the trench gate electrode 12 and the impurity layers 22 and 24. The material of the insulating film 30 is, for example, a silicon oxide film. The insulating film 30 has a stripe-shaped opening in plan view. The insulating film 30 is covered with a barrier metal 32. The barrier metal 32 is in contact with the impurity layer 24 exposed at the opening bottom of the insulating film 30. The material of the barrier metal 32 is, for example, Ti or TiN.

このバリアメタル３２の上にはプラグ金属３４が形成されている。プラグ金属３４はバリアメタル３２を介して絶縁膜３０を覆う。プラグ金属３４は、絶縁膜３０の開口を埋める埋め込み金属３４Ａと、埋め込み金属３４Ａとつながり、絶縁膜３０の上に位置する保護金属３４Ｂと、を有する。保護金属３４Ｂの膜厚は５０〜１０００ｎｍとすることが好ましい。プラグ金属３４は、Ｗ、Ｔｉ又はＴｉＮの少なくとも１つを含む。Ｗ、Ｔｉ又はＴｉＮのいずれか１つでプラグ金属３４を形成してもよいし、これらの材料から選択した２つ以上の材料を積層させた積層構造でプラグ金属３４を形成してもよい。   A plug metal 34 is formed on the barrier metal 32. The plug metal 34 covers the insulating film 30 through the barrier metal 32. The plug metal 34 includes a buried metal 34 </ b> A that fills the opening of the insulating film 30 and a protective metal 34 </ b> B that is connected to the buried metal 34 </ b> A and is located on the insulating film 30. The thickness of the protective metal 34B is preferably 50 to 1000 nm. The plug metal 34 includes at least one of W, Ti, or TiN. The plug metal 34 may be formed of any one of W, Ti, or TiN, or the plug metal 34 may be formed of a stacked structure in which two or more materials selected from these materials are stacked.

プラグ金属３４の上には引出電極３６が形成されている。引出電極３６の材料は例えばＡｌＳｉ、Ａｌ、ＡｌＣｕ、又はＡｌＳｉＣｕである。不純物層２２、２４はバリアメタル３２とプラグ金属３４を介して，引出電極３６と電気的に接続されている。引出電極３６の上にはめっき層３８が形成されている。めっき層３８は、接合電極３９と酸化防止膜４０を備えている。接合電極３９の材料は例えばＮｉＰである。酸化防止膜４０の材料は例えばＡｕ又はＰｄである。めっき層３８には例えばリードフレームがはんだ付けされる。   An extraction electrode 36 is formed on the plug metal 34. The material of the extraction electrode 36 is, for example, AlSi, Al, AlCu, or AlSiCu. The impurity layers 22 and 24 are electrically connected to the extraction electrode 36 through the barrier metal 32 and the plug metal 34. A plating layer 38 is formed on the extraction electrode 36. The plating layer 38 includes a bonding electrode 39 and an antioxidant film 40. The material of the bonding electrode 39 is, for example, NiP. The material of the antioxidant film 40 is, for example, Au or Pd. For example, a lead frame is soldered to the plating layer 38.

半導体基板１０の下面側にはｎ型のバッファ層５０とｐ型のコレクタ層５２が形成されている。そして、コレクタ層５２の下面には接合電極５４が形成されている。接合電極５４の下面には酸化防止膜５６が形成されている。接合電極５４と酸化防止膜５６は、半導体基板の下面の下面電極として機能する。そしてこの下面電極はヒートシンクなどの外部構成にはんだ付けされる。   An n-type buffer layer 50 and a p-type collector layer 52 are formed on the lower surface side of the semiconductor substrate 10. A bonding electrode 54 is formed on the lower surface of the collector layer 52. An antioxidant film 56 is formed on the lower surface of the bonding electrode 54. The bonding electrode 54 and the antioxidant film 56 function as a lower surface electrode on the lower surface of the semiconductor substrate. The bottom electrode is soldered to an external structure such as a heat sink.

図２は、引出電極３６とバリアメタル３２の欠陥を示す図である。引出電極３６とバリアメタル３２には一定の確率で欠陥が生じる。引出電極３６の欠陥とは、引出電極３６の一部に生じた未形成部分３６Ａである。バリアメタル３２の欠陥とはバリアメタル３２の微小孔３２Ａのことである。未形成部分３６Ａには接合電極３９が形成され、微小孔３２Ａはプラグ金属３４によって埋め込まれている。   FIG. 2 is a diagram showing defects in the extraction electrode 36 and the barrier metal 32. Defects are generated in the extraction electrode 36 and the barrier metal 32 with a certain probability. The defect of the extraction electrode 36 is an unformed portion 36 </ b> A generated in a part of the extraction electrode 36. The defect of the barrier metal 32 is a minute hole 32 </ b> A of the barrier metal 32. A bonding electrode 39 is formed in the unformed portion 36 </ b> A, and the microhole 32 </ b> A is embedded with a plug metal 34.

図３は、本発明の実施の形態に係る半導体装置の平面図である。前述のとおりこの半導体装置はＩＧＢＴチップである。半導体装置の中央にはセル領域６０がある。セル領域６０にはストライプ状にトレンチゲート電極１２が形成される。半導体装置の上面にはゲート電極パッド６２が設けられている。ゲート電極パッド６２には、縦方向に伸びるゲート配線６４とセル領域６０を囲むゲート配線６４が接続されている。   FIG. 3 is a plan view of the semiconductor device according to the embodiment of the present invention. As described above, this semiconductor device is an IGBT chip. There is a cell region 60 in the center of the semiconductor device. In the cell region 60, the trench gate electrode 12 is formed in a stripe shape. A gate electrode pad 62 is provided on the upper surface of the semiconductor device. A gate wiring 64 extending in the vertical direction and a gate wiring 64 surrounding the cell region 60 are connected to the gate electrode pad 62.

ゲート配線６４に、ストライプ状のトレンチゲート電極１２が接続される。トレンチゲート電極１２は図３の横方向に伸びる。したがって、ゲート電極パッド６２は、ゲート配線６４を介してトレンチゲート電極１２に電気的に接続されている。セル領域６０は周辺耐圧部６６に囲まれている。周辺耐圧部６６は、チップの縁及び裏面側と、セル領域６０、ゲート電極パッド６２及びゲート配線６４を電気的に絶縁する機能を有している。   A stripe-shaped trench gate electrode 12 is connected to the gate wiring 64. The trench gate electrode 12 extends in the horizontal direction of FIG. Therefore, the gate electrode pad 62 is electrically connected to the trench gate electrode 12 via the gate wiring 64. The cell region 60 is surrounded by the peripheral pressure-resistant portion 66. The peripheral withstand voltage portion 66 has a function of electrically insulating the edge and back surface of the chip from the cell region 60, the gate electrode pad 62, and the gate wiring 64.

図４は、図３の破線Ａで囲まれた部分の拡大図である。図４の破線Ｄに沿った断面図が、先ほど説明した図１である。図４は、図１のＢ−Ｂ破線における断面図である。ゲート酸化膜１４があるので、トレンチゲート電極１２はセル領域６０のその他の部分と電気的に絶縁されている。ストライプ状の複数のトレンチゲート電極１２が平行に設けられている。図５は、図３の破線Ａで囲まれた部分の拡大図であり、図１のＣ―Ｃ破線における断面を表す図である。絶縁膜３０は、前述のトレンチゲート電極１２の上に、ストライプ状に複数設けられる。   4 is an enlarged view of a portion surrounded by a broken line A in FIG. The cross-sectional view along the broken line D in FIG. 4 is FIG. 1 described above. 4 is a cross-sectional view taken along a broken line BB in FIG. Due to the presence of the gate oxide film 14, the trench gate electrode 12 is electrically insulated from other parts of the cell region 60. A plurality of stripe-shaped trench gate electrodes 12 are provided in parallel. 5 is an enlarged view of a portion surrounded by a broken line A in FIG. 3, and is a diagram showing a cross section taken along a broken line CC in FIG. A plurality of insulating films 30 are provided in stripes on the trench gate electrode 12 described above.

上述した半導体装置の製造方法を説明する。まず、半導体基板１０の上面側に不純物層２０、２２、２４、トレンチゲート電極１２、ゲート酸化膜１４を形成する。次いで、半導体基板１０の上面に開口を有する絶縁膜３０を形成する。図６は、不純物層２０、２２、２４、トレンチゲート電極１２、ゲート酸化膜１４及び絶縁膜３０を形成したことを示す図である。不純物層２０、２２、２４は不純物をイオン注入し、それを熱処理することで形成する。絶縁膜３０は、トレンチゲート電極１２の上部にあり、半導体基板１０の上方に突出する。   A method for manufacturing the above-described semiconductor device will be described. First, impurity layers 20, 22, 24, a trench gate electrode 12, and a gate oxide film 14 are formed on the upper surface side of the semiconductor substrate 10. Next, an insulating film 30 having an opening is formed on the upper surface of the semiconductor substrate 10. FIG. 6 is a diagram showing that the impurity layers 20, 22, 24, the trench gate electrode 12, the gate oxide film 14, and the insulating film 30 are formed. The impurity layers 20, 22 and 24 are formed by ion-implanting impurities and heat-treating them. The insulating film 30 is on the trench gate electrode 12 and protrudes above the semiconductor substrate 10.

次いで、バリアメタル３２を形成する。バリアメタル３２は例えばスパッタ法で形成する。次いで、プラグ金属３４を形成する。図７は、プラグ金属３４を形成したことを示す図である。プラグ金属３４は、絶縁膜３０の開口を埋める埋め込み金属３４Ａと、埋め込み金属３４Ａとつながり、絶縁膜３０の上に位置する保護金属３４Ｂとを有することで、絶縁膜３０を覆う。プラグ金属３４はＣＶＤ法で形成する。ＣＶＤ法でプラグ金属３４を形成することで、バリアメタル３２に一定確率で生じる微小孔をプラグ金属３４で埋め込むことができる。   Next, the barrier metal 32 is formed. The barrier metal 32 is formed by sputtering, for example. Next, the plug metal 34 is formed. FIG. 7 is a view showing that the plug metal 34 is formed. The plug metal 34 covers the insulating film 30 by having a buried metal 34 </ b> A filling the opening of the insulating film 30 and a protective metal 34 </ b> B connected to the buried metal 34 </ b> A and positioned on the insulating film 30. The plug metal 34 is formed by a CVD method. By forming the plug metal 34 by the CVD method, it is possible to fill the plug metal 34 with micro holes generated in the barrier metal 32 with a certain probability.

次いで、プラグ金属３４の上にフォトレジスト形成し、これをフォトリソグラフィー法によってパターンニングする。図８には、フォトレジスト７０が示されている。パターニングされたフォトレジスト７０をマスクとして、周辺耐圧部６６に形成されたプラグ金属をエッチングする。セル領域６０のプラグ金属３４はフォトレジスト７０があるのでエッチングされない。   Next, a photoresist is formed on the plug metal 34, and this is patterned by a photolithography method. FIG. 8 shows a photoresist 70. Using the patterned photoresist 70 as a mask, the plug metal formed in the peripheral withstand voltage portion 66 is etched. The plug metal 34 in the cell region 60 is not etched because of the photoresist 70.

次いで、フォトレジスト７０を除去し、プラグ金属３４の上に引出電極３６を形成する。引出電極３６はスパッタリング法又はＰＶＤ法により形成する。図９は、引出電極３６を形成したことを示す図である。引出電極３６はプラグ金属３４の上に形成されバリアメタル３２とは直接接しない。   Next, the photoresist 70 is removed, and an extraction electrode 36 is formed on the plug metal 34. The extraction electrode 36 is formed by a sputtering method or a PVD method. FIG. 9 is a diagram showing that the extraction electrode 36 is formed. The extraction electrode 36 is formed on the plug metal 34 and is not in direct contact with the barrier metal 32.

絶縁膜３０の開口を埋め込んでいるプラグ金属３４の表面は概ね平坦であるので、引出電極３６とプラグ金属３４は確実に接触し、コンタクト抵抗を安定させることができる。スパッタリング法又はＰＶＤ法で引出電極３６を形成すると、一定の確率で欠陥が生じる。図１０には、引出電極３６を形成すべきであるにもかかわらず形成されなかった未形成部分３６Ａが示されている。   Since the surface of the plug metal 34 in which the opening of the insulating film 30 is embedded is substantially flat, the extraction electrode 36 and the plug metal 34 can be reliably in contact with each other and the contact resistance can be stabilized. When the extraction electrode 36 is formed by the sputtering method or the PVD method, defects are generated with a certain probability. FIG. 10 shows an unformed portion 36A that was not formed although the extraction electrode 36 should be formed.

次いで、引出電極３６の上に、めっき法により接合電極３９と酸化防止膜４０を形成する。次いで、半導体基板１０の下面を研削して、バッファ層５０とコレクタ層５２を形成する。次いで、スパッタ法で、接合電極５４と酸化防止膜５６を形成する。こうして、図１、２に示す半導体装置が完成する。   Next, the bonding electrode 39 and the antioxidant film 40 are formed on the extraction electrode 36 by plating. Next, the lower surface of the semiconductor substrate 10 is ground to form the buffer layer 50 and the collector layer 52. Next, the bonding electrode 54 and the antioxidant film 56 are formed by sputtering. Thus, the semiconductor device shown in FIGS. 1 and 2 is completed.

ここで、本発明の理解を容易にするために比較例について説明する。図１１は比較例に係る半導体装置の製造方法によって形成された半導体装置の断面図である。プラグ金属８０は、絶縁膜３０の間にだけ形成されており、絶縁膜３０の上には形成されていない。したがって、バリアメタル３２と引出電極３６が直接接触する部分がある。   Here, comparative examples will be described in order to facilitate understanding of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device formed by a method for manufacturing a semiconductor device according to a comparative example. The plug metal 80 is formed only between the insulating films 30 and is not formed on the insulating film 30. Therefore, there is a portion where the barrier metal 32 and the extraction electrode 36 are in direct contact.

プラグ金属８０をウエハ全面に積層した後、絶縁膜３０の間にだけプラグ金属８０が残るようにエッチングする。このエッチングにより、プラグ金属８０がえぐれることがある。そのため、絶縁膜３０と別の絶縁膜３０の間において、プラグ金属８０と引出電極３６のコンタクト抵抗が不安定になる。   After the plug metal 80 is stacked on the entire surface of the wafer, etching is performed so that the plug metal 80 remains only between the insulating films 30. By this etching, the plug metal 80 may be removed. Therefore, the contact resistance between the plug metal 80 and the extraction electrode 36 becomes unstable between the insulating film 30 and another insulating film 30.

比較例の場合、引出電極３６の未形成部分に露出したバリアメタル３２にめっき処理が施される。図１２は、引出電極３６の未形成部分３６Ａにめっき層３８を形成したことを示す図である。引出電極３６の未形成部分３６Ａとバリアメタル３２の微小孔３２Ａがある部分にめっき層３８を形成するために、ウエハを複数の薬液に浸漬すると、めっき薬液が未形成部分３６Ａ及び微小孔３２Ａを通ってトレンチゲート電極１２又はゲート酸化膜１４を腐食してしまう。図１２には腐食部分９０が示されている。腐食部分９０があると、ゲート電極パッド６２と、セル領域６０のその他の部分との電気的な絶縁性が保持できず、正常な動作ができない不良チップが発生してしまう。その他の部分というのは例えばエミッタである。   In the case of the comparative example, the barrier metal 32 exposed in the unformed portion of the extraction electrode 36 is subjected to plating. FIG. 12 is a view showing that the plating layer 38 is formed on the unformed portion 36 </ b> A of the extraction electrode 36. When the wafer is dipped in a plurality of chemicals to form the plating layer 38 in the part where the lead electrode 36 is not formed and the part 32A having the microhole 32A in the barrier metal 32, the plating chemicals are formed in the part 36A and the microhole 32A which are not formed. As a result, the trench gate electrode 12 or the gate oxide film 14 is corroded. In FIG. 12, a corroded portion 90 is shown. If the corroded portion 90 exists, the electrical insulation between the gate electrode pad 62 and the other portions of the cell region 60 cannot be maintained, and a defective chip that cannot operate normally is generated. The other part is, for example, an emitter.

本発明の実施の形態に係る半導体装置の製造方法では、図１０に示すように、微小孔３２Ａはプラグ金属３４で埋められ、未形成部分３６Ａにはプラグ金属３４が露出しているので、めっき処理の薬液がプラグ金属３４の下の構造にしみこまない。よって、トレンチゲート電極１２又はゲート酸化膜１４の腐食を防止できる。また、ＣＶＤ法でプラグ金属３４を形成するので、バリアメタル３２に欠陥又は異物が存在しても、それらの表面とその下地をプラグ金属３４で隙間なく被覆できる。プラグ金属３４の一部である保護金属３４Ｂの膜厚を５０〜１０００ｎｍと厚くしたので、プラグ金属３４の下地に欠陥又は異物が存在しても、それらの表面とその下地を、プラグ金属３４で被覆できる。なお、めっき処理の薬液に溶解しないように、プラグ金属３４の材料はＷ、Ｔｉ又はＴｉＮの少なくとも１つを含むことが好ましい。   In the method of manufacturing a semiconductor device according to the embodiment of the present invention, as shown in FIG. 10, the microhole 32A is filled with the plug metal 34, and the plug metal 34 is exposed in the unformed portion 36A. The processing chemical does not penetrate into the structure under the plug metal 34. Therefore, corrosion of the trench gate electrode 12 or the gate oxide film 14 can be prevented. Moreover, since the plug metal 34 is formed by the CVD method, even if a defect or a foreign substance exists in the barrier metal 32, the surface and the base thereof can be covered with the plug metal 34 without any gap. Since the thickness of the protective metal 34B, which is a part of the plug metal 34, is increased to 50 to 1000 nm, even if a defect or a foreign substance exists on the base of the plug metal 34, the surface of the plug metal 34 and the base thereof are covered with the plug metal 34. Can be coated. The material of the plug metal 34 preferably contains at least one of W, Ti, or TiN so as not to dissolve in the plating solution.

半導体基板１０の下面における接合電極５４と酸化防止膜５６をスパッタ法で形成し、半導体基板１０の上面における接合電極３９と酸化防止膜４０をめっき法で形成すると、半導体基板１０の下面側の膜応力が強くなり、半導体基板１０が上に凸に反る。半導体基板１０が上に凸に反ると、ウエハを裏面からハンドリングしにくくなり、加工歩留が低下する。そのようなウエハをダイシングしてチップ小片に切り分けても半導体基板１０は上に凸に沿ったままである。上に凸に沿ったチップの下面側をヒートシンク等の外部部品にはんだ付けすると、気泡がチップ中央部に蓄積され、はんだボイド不良が増加することによる組立歩留の低下が起こる。   When the bonding electrode 54 and the antioxidant film 56 on the lower surface of the semiconductor substrate 10 are formed by sputtering, and the bonding electrode 39 and the antioxidant film 40 on the upper surface of the semiconductor substrate 10 are formed by plating, a film on the lower surface side of the semiconductor substrate 10 is formed. The stress increases and the semiconductor substrate 10 warps upwards. If the semiconductor substrate 10 warps upward, it becomes difficult to handle the wafer from the back surface, and the processing yield decreases. Even if such a wafer is diced and cut into small chip pieces, the semiconductor substrate 10 remains along the convex. When the lower surface side of the chip along the upward convex is soldered to an external component such as a heat sink, bubbles are accumulated in the center portion of the chip, resulting in a decrease in assembly yield due to an increase in solder void defects.

しかしながら、本発明の実施の形態に係る半導体装置は、絶縁膜３０の開口を埋めつつ絶縁膜３０の上に達する厚いプラグ金属３４を形成したことに加え、プラグ金属３４はＷ、Ｔｉ又はＴｉＮの少なくとも１つを含むので、プラグ金属３４の応力が大きい。そのため、半導体基板１０の下面側の接合電極５４と酸化防止膜５６を厚く形成したとしても、プラグ金属３４は半導体基板１０を下に凸に反らせる。したがって、ウエハ裏面をハンドリングしやすくなり、例えばウエハ裏面を障害なく搬送治具に真空吸着させることができる。また、ウエハをダイシングしてチップ小片に切り分けた後にも半導体基板は下に凸に反ったままであるので、チップの下面をはんだ付けした際に発生する気泡はチップ中央部から外側に排気され、はんだボイド不良が低減する。よって、組立歩留を改善することができる。   However, in the semiconductor device according to the embodiment of the present invention, the plug metal 34 is made of W, Ti, or TiN in addition to forming the thick plug metal 34 reaching the insulating film 30 while filling the opening of the insulating film 30. Since at least one is included, the stress of the plug metal 34 is large. Therefore, even if the bonding electrode 54 and the antioxidant film 56 on the lower surface side of the semiconductor substrate 10 are formed thick, the plug metal 34 warps the semiconductor substrate 10 downward. Therefore, it becomes easy to handle the wafer back surface, and for example, the wafer back surface can be vacuum-adsorbed to the transfer jig without any obstacle. In addition, even after the wafer is diced and cut into small chips, the semiconductor substrate remains warped downward, so that bubbles generated when the lower surface of the chip is soldered are exhausted outward from the center of the chip, Void defects are reduced. Therefore, the assembly yield can be improved.

本発明の実施の形態に係るセル領域６０におけるプラグ金属３４は、プロセス中でドライエッチングされる事がないので、プラグ金属３４にドライエッチングに起因する「えぐれ」は発生しない。このため、プラグ金属３４の上に積層される引出電極３６の埋め込み性が改善し、コンタクト抵抗を安定させることができる。   Since the plug metal 34 in the cell region 60 according to the embodiment of the present invention is not dry-etched during the process, the plug metal 34 is not “blank” due to the dry etching. For this reason, the embedding property of the extraction electrode 36 laminated on the plug metal 34 is improved, and the contact resistance can be stabilized.

本発明の実施の形態に係る半導体装置の製造方法はその特徴を失わない範囲で様々な変形が可能である。例えば、半導体基板１０は、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成してもよい。ワイドバンドギャップ半導体としては、例えば炭化珪素、窒化ガリウム系材料又はダイヤモンドがある。ワイドバンドギャップ半導体を用いた半導体装置は、耐電圧が高く、許容電流密度も高いので、本発明のプラグ金属３４によりトレンチゲート電極１２等の腐食を抑制することが特に重要である。   The semiconductor device manufacturing method according to the embodiment of the present invention can be variously modified without losing its characteristics. For example, the semiconductor substrate 10 may be formed of a wide band gap semiconductor having a larger band gap than silicon. Examples of the wide band gap semiconductor include silicon carbide, gallium nitride-based materials, and diamond. Since a semiconductor device using a wide band gap semiconductor has a high withstand voltage and a high allowable current density, it is particularly important to suppress corrosion of the trench gate electrode 12 and the like by the plug metal 34 of the present invention.

電力半導体装置はＩＧＢＴチップであるとしたが、本発明の技術は、プラグ金属の上に引出電極とめっき膜を形成するプロセスを有するものに広く利用できる。よって半導体装置はＩＧＢＴチップに限定されず、ＭＯＳＦＥＴなどでもよい。   Although the power semiconductor device is assumed to be an IGBT chip, the technique of the present invention can be widely used for a device having a process of forming an extraction electrode and a plating film on a plug metal. Therefore, the semiconductor device is not limited to the IGBT chip, and may be a MOSFET or the like.

また、バリアメタル３２を省略して不純物層２４及び絶縁膜３０に直接プラグ金属３４を形成してもよい。   Alternatively, the plug metal 34 may be formed directly on the impurity layer 24 and the insulating film 30 without the barrier metal 32.

１０ 半導体基板、 １２ トレンチゲート電極、 １４ ゲート酸化膜、 ２０,２２,２４ 不純物層、 ３０ 絶縁膜、 ３２ バリアメタル、 ３２Ａ 微小孔、 ３４ プラグ金属、 ３４Ａ 埋め込み金属、 ３４Ｂ 保護金属、 ３６ 引出電極、 ３８ めっき層、 ３９ 接合電極、 ４０ 酸化防止膜   10 semiconductor substrate, 12 trench gate electrode, 14 gate oxide film, 20, 22, 24 impurity layer, 30 insulating film, 32 barrier metal, 32A microhole, 34 plug metal, 34A buried metal, 34B protective metal, 36 lead electrode, 38 plating layer, 39 bonding electrode, 40 antioxidant film

Claims (8)

半導体基板の上面側に不純物層を形成する工程と、
前記半導体基板の上面に開口を有する絶縁膜を形成する工程と、
前記絶縁膜の開口を埋める埋め込み金属と、前記埋め込み金属とつながり、前記絶縁膜の上に位置する保護金属と、を有することで前記絶縁膜を覆うプラグ金属をＣＶＤ法で形成する工程と、
前記プラグ金属の上に、スパッタリング法又はＰＶＤ法により引出電極を形成する工程と、
前記引出電極の上に、めっき法により接合電極を形成する工程と、を備えたことを特徴とする半導体装置の製造方法。 Forming an impurity layer on the upper surface side of the semiconductor substrate;
Forming an insulating film having an opening on the upper surface of the semiconductor substrate;
Forming a plug metal that covers the insulating film by a CVD method by having a buried metal filling the opening of the insulating film and a protective metal connected to the buried metal and positioned on the insulating film;
Forming an extraction electrode on the plug metal by a sputtering method or a PVD method;
Forming a bonding electrode on the extraction electrode by a plating method. 前記半導体基板にはトレンチゲート電極が形成され、
前記絶縁膜は、前記トレンチゲート電極の上及び前記不純物層の上にあることを特徴とする請求項１に記載の半導体装置の製造方法。 A trench gate electrode is formed on the semiconductor substrate,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is on the trench gate electrode and on the impurity layer. 前記保護金属の膜厚は５０〜１０００ｎｍであることを特徴とする請求項１又は２に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the protective metal has a thickness of 50 to 1000 nm. 前記プラグ金属は、Ｗ、Ｔｉ又はＴｉＮの少なくとも１つを含むことを特徴とする請求項１〜３のいずれか１項に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the plug metal includes at least one of W, Ti, and TiN. 前記プラグ金属は、前記半導体基板を下に凸に反らせる厚みを有することを特徴とする請求項４に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 4, wherein the plug metal has a thickness that warps the semiconductor substrate downward. 前記半導体基板の下面にスパッタ法で下面電極を形成する工程と、
前記下面電極を外部構成にはんだ付けすることを特徴とする請求項５に記載の半導体装置の製造方法。 Forming a lower surface electrode by sputtering on the lower surface of the semiconductor substrate;
6. The method of manufacturing a semiconductor device according to claim 5, wherein the lower surface electrode is soldered to an external configuration. 前記半導体基板はワイドバンドギャップ半導体によって形成されたことを特徴とする請求項１〜６のいずれか１項に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is formed of a wide band gap semiconductor. 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料又はダイヤモンドであることを特徴とする請求項７に記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.
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