JP2019145667A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To provide a semiconductor device having an electrode structure which can achieve both electrode embedding capabilities into a contact and the uniformity of a solder connection layer.SOLUTION: A semiconductor device includes a semiconductor substrate and a surface electrode in contact with the semiconductor substrate. The surface electrode includes, in order of proximity to the semiconductor substrate, a first layer, a second layer formed on a surface of the first layer, and a third layer formed on a surface of the second layer. The first layer is an AlSi layer, the second layer is an AlCu layer, and the third layer is an Ni layer. The Al grain size of the second layer is smaller than the Al grain size of the first layer.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a semiconductor device, and is particularly applicable to a semiconductor device used for a power device and a manufacturing method thereof.

As semiconductor devices used in power devices, insulated gate bipolar transistor (IGBT: I nsulated G ate B ipolar T ransistor) it is. As configurations of the surface electrode of the IGBT, International Publication No. 2011/004469 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2010-278164 (Patent Document 2) have been proposed.

  WO 2011/004469 states, “As a surface electrode of a semiconductor device, in order from the surface side of a semiconductor substrate, a first layer that is a barrier metal layer, a second layer that is an Al layer, an Al—Si layer, or an Al—Cu layer. A third layer that is a layer or an Al—Si—Cu layer and a fourth layer that is a solder joint layer, which are formed by electroless plating after Zn substitution treatment is performed on the third layer. Is possible. " Further, “Al of the second layer (132) is formed at a substrate temperature of 25 ° C. to 300 ° C., and AlSi, AlCu, or AlSiCu of the third layer (133) is formed at a substrate temperature of 25 ° C. to 300 ° C.” It is disclosed.

  JP 2010-278164 states, “A surface electrode is formed by forming an Al—Si layer or an Al—Si—Cu layer by sputtering at a substrate temperature of 250 ° C. or less as a first layer in contact with a semiconductor substrate, The second layer is manufactured by forming an Al layer or an Al—Cu layer by a sputtering method at a substrate temperature of 400 ° C. or higher, and forming a solder joint layer and a solder layer on the surface side. ” ing.

International Publication No. 2011/004469 JP 2010-278164 A

  The present inventors have studied surface electrodes of semiconductor devices used for power devices and found the following points.

  The denseness of the zinc (Zn) substitution film depends on the crystal orientation of aluminum (Al). Therefore, depending on the sputtering temperature, when Al with a large crystal orientation of (100) is formed on the electrode surface, there is a possibility that a blank is generated in the Zn substitution film.

  In addition, when Al is formed by sputtering at a substrate temperature of 300 ° C. or lower, voids may be generated when the contact diameter is reduced.

  Further, when a layer (Al layer or Al—Cu (aluminum-copper alloy) layer, etc.) in contact with the solder connection layer is formed by sputtering at a high temperature of 400 ° C. or more, a crystal having a large area (100) is formed on the electrode surface. Oriented Al is easily formed.

  An object of the present disclosure is to provide a semiconductor device having an electrode structure in which both the electrode embedding property in the contact and the uniformity of the solder connection layer are compatible.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An outline of typical ones of the present disclosure will be briefly described as follows.

  That is, the semiconductor device has a semiconductor substrate and a surface electrode in contact with the semiconductor substrate. The surface electrode includes a first layer, a second layer formed on the surface of the first layer, and a third layer formed on the surface of the second layer, in order from the semiconductor substrate. The first layer is an AlSi layer, the second layer is an AlCu layer, and the third layer is a Ni layer. The Al grain size of the second layer is smaller than the Al grain size of the first layer.

  According to the semiconductor device, both the electrode embedding property in the contact and the uniformity of the solder connection layer can be achieved.

1 is a cross-sectional view for explaining a semiconductor device according to Example 1. FIG. It is sectional drawing for demonstrating the semiconductor device which concerns on a modification. 1 is a diagram illustrating a configuration example of a plan view of a semiconductor device according to Example 1. FIG. It is sectional drawing which shows the formation process of an AlSi layer. It is sectional drawing which shows the formation process of an AlCu layer. It is sectional drawing which shows the patterning process of an AlSi layer and an AlCu layer. It is sectional drawing which shows the formation process of a polyimide layer. It is sectional drawing which shows the formation process of Zn substituted film. It is sectional drawing which shows the formation process of Ni layer. It is a figure which shows the surface photograph of the Al grain map of the surface of the AlCu layer formed by the sputtering from which a substrate temperature differs. It is a figure which shows the surface photograph of the Zn substituted film formed on the surface of the AlCu layer formed by the sputtering from which a substrate temperature differs. It is a figure which shows the surface photograph of the electroless Ni plating layer (Ni layer) formed on the surface of the AlCu layer formed by the sputtering from which a substrate temperature differs. It is a figure which shows the relationship between the substrate temperature at the time of a sputter | spatter, and the Al grain size (crystal grain size) of an AlCu layer. 6 is a cross-sectional view for explaining a semiconductor device according to Example 2. FIG. It is sectional drawing which shows the formation process of an AlSi layer. It is sectional drawing which shows the process of etch-back or grinding so that the height of an AlSi layer may become below a contact. It is sectional drawing which shows the formation process of an AlCu layer. It is sectional drawing which shows the patterning process of an AlCu layer. It is sectional drawing which shows the formation process of a polyimide layer. It is sectional drawing which shows the formation process of Zn substituted film. It is sectional drawing which shows the formation process of Ni layer. 7 is a cross-sectional view for explaining a semiconductor device according to Example 3. FIG. It is sectional drawing which shows the formation process of an AlSi layer. It is sectional drawing which shows the patterning process of an AlSi layer. It is sectional drawing which shows the formation process of an AlCu layer. It is sectional drawing which shows the patterning process of an AlCu layer. It is sectional drawing which shows the formation process of a polyimide layer. It is sectional drawing which shows the formation process of Zn substituted film. It is sectional drawing which shows the formation process of Ni layer. 4 is an enlarged plan view showing a part of a semiconductor wafer according to Examples 1, 2, and 3. FIG.

  Hereinafter, examples and modifications will be described with reference to the drawings. However, in the following description, the same components may be denoted by the same reference numerals and repeated description may be omitted. In order to clarify the description, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part as compared to the actual embodiment, but are merely examples, and the interpretation of the present invention is not limited to them. It is not limited.

  In the following embodiments and modifications, an insulated gate bipolar transistor (IGBT) is described as an example of a semiconductor element formed in a semiconductor device used for a power device. However, a semiconductor element such as a MOSFET or a diode is used. It can also be used as an electrode structure of a conventional semiconductor device.

  FIG. 1 is a cross-sectional view for explaining the semiconductor device according to the first embodiment. FIG. 1 is a cross-sectional view of a semiconductor wafer 1 on which a semiconductor device 100 is formed. For example, single crystal silicon can be used for the semiconductor wafer 1. The semiconductor wafer 1 includes an element region ER, a peripheral region PR provided so as to surround the periphery of the element region ER, and a scribe region SR that is diced during assembly. The peripheral region PR can also be called an outer peripheral region. The semiconductor device 100 includes an element region ER and a peripheral region PR. That is, a plurality of semiconductor chips are formed in the semiconductor wafer 1 by dicing the scribe region SR into pieces. Each semiconductor chip corresponds to the semiconductor device 100.

In the element region ER of the semiconductor wafer 1, an insulated gate bipolar transistor having a trench gate (IGBT: I nsulated G ate B ipolar T ransistor) is provided as a semiconductor element of the power device, also, to the emitter electrode of the IGBT A surface electrode ED to be connected is provided. The surface electrode ED can also be called an emitter electrode pad. In the peripheral region PR, a gate electrode G, a field plate electrode FP, and a channel stopper electrode GR are provided. The gate electrode G, field plate electrode FP, and channel stopper electrode GR will be described later with reference to FIG.

  The semiconductor wafer 1 includes a semiconductor substrate 11 and a back electrode 12 provided on the back side of the semiconductor substrate 11. The back electrode 12 is a collector electrode that can be made of gold (Au) or silver (Ag). The semiconductor substrate 11 is provided with a P + type collector region 13 and an N− type drift layer 14 stacked from the back side. The P type can be referred to as a first conductivity type, and the N type can be referred to as a second conductivity type.

  In the element region ER, a P-type body region 15 is provided above the N− type drift layer 14, and an N + type emitter region 16 is provided on the surface of the N− type drift layer 14. A trench gate 17 penetrating the body region 15 from the surface side of the semiconductor substrate 11 is provided. The trench gate 17 has a gate electrode 171 embedded in the trench and a gate oxide film 172 provided so as to cover the gate electrode 171. The surface of the trench gate 17 is covered with an interlayer insulating film 21 provided on a part of the semiconductor substrate 11.

  In the element region ER, an AlSi (aluminum / silicon alloy) layer 22 as a first layer is provided in contact with the surfaces of the semiconductor substrate 11 and the interlayer insulating film 21. That is, the interlayer insulating film 21 is selectively provided on the surface of the semiconductor substrate 11 so that the body region 15 and the emitter region 16 are exposed. The AlSi layer 22 as the first layer is provided in contact with the surface of the body region 15 and the surface of the emitter region 16 exposed from the interlayer insulating film 21. An AlCu (aluminum / copper alloy) layer 23 as a second layer is provided on the surface of the AlSi layer 22, and a nickel (Ni) layer 24 as a third layer is provided on the surface of the AlCu layer 23. A polyimide layer 30 as a protective film is provided on part of the surface of the AlSi layer 22 and the AlCu layer 23. The Ni layer 24 that is the third layer is a solder connection layer, and a solder layer is formed on the upper side of the Ni layer 24. The surface electrode ED includes an AlSi layer 22, an AlCu layer 23, and a Ni layer 24.

  In the peripheral region PR, a part of the surface of the N− type drift layer 14 has a P type region 19 provided simultaneously with the P type body region 15 and an N + type provided simultaneously with the N + type emitter region 16. A region 20 is provided. The P-type region 19 is a field plate layer, and the N + type region 20 is a channel stopper layer. An interlayer insulating film 21 is provided on a part of the semiconductor substrate 11 so that a part of the P-type region 19 and a part of the N + type region 20 are exposed. An AlSi layer 22 as a first layer is provided in contact with the surface of the P-type region 19 serving as a field plate layer and a part of the surface of the interlayer insulating film 21. The AlCu layer 23 as the second layer is provided on the surface of the AlSi layer 22 to form the field plate electrode FP. Further, an AlSi layer 22 as a first layer is provided in contact with the surface of the N + type region 20 serving as a channel stopper layer and a part of the surface of the interlayer insulating film 21. The AlCu layer 23 as the second layer is provided on the surface of the AlSi layer 22 to form the channel stopper electrode GR. Further, a polyimide layer 30 as a protective film is provided on a part of the surface of the interlayer insulating film 21 and a part of the surfaces of the AlSi layer 22 and the AlCu layer 23.

  In the scribe region SR, an interlayer insulating film 21 is provided on part of the surface of the N − -type drift layer 14. An AlSi layer 22 as a first layer is provided in contact with the surfaces of the semiconductor substrate 11 and the interlayer insulating film 21. On the surface of the AlSi layer 22, an AlCu layer 23 as a second layer is provided. On the surface of the AlSi layer 22 and the AlCu layer 23, a Ni layer 24 as a third layer is provided. A polyimide layer 30 as a protective film is provided on the surface of the Ni layer 24.

  In the field plate electrode FP and the field plate layer (P-type region 19), a depletion layer extending from a pn junction composed of the P-type body region 15 and the N-type drift layer 14 in the element region ER is extended. This relaxes the concentration of the electric field and prevents breakdown. In addition, a channel stopper electrode GR and a channel stopper layer (N + type region 20) are provided in order to prevent the depletion layer from extending too much and grounding to the end of the peripheral region PR to flow current. The potential of the collector electrode 12 is transmitted to the channel stopper electrode GR and the channel stopper layer (N + type region 20) to suppress the extension of the depletion layer.

  The separated semiconductor device 100 is mounted on, for example, a lead frame having three terminals (gate, emitter, collector), and then molded with a sealing resin or the like into one package.

  In FIG. 1, the first layer in contact with the semiconductor substrate 11 is composed of an AlSi layer 22 formed at a substrate temperature equal to or higher than the solid solubility line in the AlSi phase diagram. The second layer in contact with the first layer is composed of an AlCu layer 23 formed at a substrate temperature such that the grain size (particle size) of Al (aluminum) atoms is smaller than that of the first layer 22. The third layer formed on the second AlCu layer 23 is composed of a Ni layer 24 formed by an electroless plating method involving zinc (Zn) substitution treatment. The Ni layer 24 is provided as a solder connection layer.

  The AlSi layer 22 can be formed by a sputtering method under a substrate temperature condition such as 400 ° C. or higher and −500 ° C. or lower, for example. The AlCu layer 23 can be formed by a sputtering method under conditions of a substrate temperature such as 25 ° C. or higher and −200 ° C. or lower. That is, the AlCu layer 23 is formed by a sputtering method at a lower substrate temperature than the substrate temperature at the time of forming the AlSi layer 22 (low temperature sputtering). Conversely, the AlSi layer 22 is formed by a sputtering method at a substrate temperature that is higher than the substrate temperature at the time of forming the AlCu layer 23 (high temperature sputtering).

  In this case, the grain size of Al atoms in the AlSi layer 22 is preferably 13 μm or more and −20 μm or less, and the grain size of Al atoms in the AlCu layer 23 is preferably 10 μm or less, more preferably 9 μm or less.

  The AlSi layer 22 formed by sputtering under a substrate temperature condition such as 400 ° C. or higher and −500 ° C. or lower has higher reflow performance than AlCu or AlSiCu. Therefore, as shown in FIG. 1, the AlSi layer 22 can be formed without a void even in a fine contact having a contact diameter (L) of 0.5 μm or less, for example. The contact is a contact hole provided by selectively etching the interlayer insulating film 21. In the element region ER, the surface of the semiconductor substrate 11, that is, the surfaces of the emitter region 16 and the body region 15 are exposed from the contact holes, and the surfaces of the emitter region 16 and the body region 15 are within the contact holes. Connected. In the peripheral region PR, the surface of the P-type region 19 serving as the field plate layer and the surface of the N + -type region 20 serving as the channel stopper layer are exposed from the contact holes, and the P-type region serving as the field plate layer The surface of 19 and the surface of the N + type region 20 serving as the channel stopper layer are connected to the AlSi layer 22 in the contact hole. As is apparent from FIG. 1, the diameter of the contact hole provided in the peripheral region PR is larger than the diameter (L) of the contact hole provided in the element region ER.

  The second AlCu layer 23 is formed by sputtering at a substrate temperature such that the Al grain size is smaller than that of the first AlSi layer 22. Thereby, the 3rd layer (Ni layer 24) formed on the AlCu layer 23 of the 2nd layer can be formed as a uniform electroless plating layer.

  This makes it possible to achieve both electrode embedding in the contact and uniformity of the solder connection layer (electroless plating layer).

  Further, since the Al-based material layers (22, 23) to which different elements are added are bonded, each element diffuses in the direction of the bonding surface, and the surface of the semiconductor substrate 11 and the electrode surface of the AlCu layer 23 are diffused. It can suppress that an additive element precipitates and a residue and a nodule generate | occur | produce.

  Further, by forming the surface of the Al electrodes (22, 23) with the AlCu layer 23 containing Cu, it is possible to obtain a higher migration resistance compared to a single layer of the AlSi layer 22, and to operate at a high temperature and a large current. The quality of the semiconductor device 100 at the time can be improved.

  The second layer is most preferably an AlCu layer (23), but an AlSiCu (aluminum / silicon / copper alloy) layer or an AlSi layer can also be used.

  Although not shown in FIG. 1, a solder layer is formed on the surface of the Ni layer 24.

  FIG. 2 is a cross-sectional view for explaining a semiconductor device according to a modification. The semiconductor wafer 1a shown in FIG. 2 is different from the semiconductor wafer 1 shown in FIG. 1 in that a barrier metal 25 is provided between the surface of the semiconductor substrate 11 and the interlayer insulating film 21 and the AlSi layer 22. is there. Other configurations are the same as those in FIG. The barrier metal 25 can employ titanium nitride (TiN), titanium / tungsten (TiW), or the like. The structure of the semiconductor device 100a in FIG. 2 can achieve the same effect as the semiconductor device 100 in FIG.

  FIG. 3 is a diagram illustrating a configuration example of a plan view of the semiconductor device according to the first embodiment. FIG. 3 is a plan view of the semiconductor chip in which the semiconductor device 100 (or 100a) is viewed from the upper surface side. The emitter electrode pad (E) exposed from the polyimide layer 30 and the gate electrode pad. (G) and a plurality of pads (P) such as a Kelvin emitter electrode pad and a temperature measuring pad are shown.

  3A, the uppermost layer of each of the emitter electrode pad (E), the gate electrode pad (G), and the plurality of pads (P) is formed of a Ni layer 24 as shown in FIG. 1 or FIG. The structure using is shown. The uppermost layer of the emitter electrode pad (E) is the Ni layer 24 (E), and the uppermost layer of the gate electrode pad (G) is the Ni layer 24 (G). The uppermost layer of the plurality of pads (P) is the Ni layer 24 (P).

  In FIG. 3B, the difference from FIG. 3A is that the uppermost layer of the gate electrode pad (G) and the plurality of pads (P) is not the Ni layer 24 but the AlCu layer 23. It is a point. The top layer of the gate electrode pad (G) is the AlCu layer 23 (G), and the top layer of the plurality of pads (P) is the AlCu layer 23 (P). In the case of FIG. 3B, for example, when the Ni layer 24 is formed by an electroless plating method, the AlCu layer 23 (G) of the gate electrode pad (G) and the AlCu layer 23 ( A mask material is provided so as to cover the upper surface of P), and a Ni layer 24 (E) is provided on the surface of the AlCu layer 23 of the emitter electrode pad (E).

  3C, the difference from FIG. 3A is that the uppermost layer of the gate electrode pad (G) is an AlCu layer 23 (G) as shown in FIG. The Ni layer 24 (E) that is the uppermost layer of the emitter electrode pad (E) is partially provided on the surface of the AlCu layer 23 (E). In the case of FIG. 3C, for example, when the Ni layer 24 is formed by electroless plating, the AlCu layer 23 (G) of the gate electrode pad (G) and the AlCu layer 23 of the emitter electrode pad (E) A mask material is provided so as to cover a part of the surface, and the Ni layer 24 is formed on the upper surface of the AlCu layer 23 (P) of the plurality of pads (P) and a part of the surface of the AlCu layer 23 of the emitter electrode pad (E). (E) and 24 (P) are provided.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the drawings.

  4 to 9 are flowcharts showing the method for manufacturing the semiconductor device 100 in cross-sectional views. More specifically, a formation process for forming the surface electrode ED on the surface of the semiconductor substrate including the semiconductor element will be described. FIG. 4 is a cross-sectional view showing a process for forming the AlSi layer 22. FIG. 5 is a cross-sectional view showing a process for forming the AlCu layer 23. FIG. 6 is a cross-sectional view showing the patterning process of the AlSi layer 22 and the AlCu layer 23. FIG. 7 is a cross-sectional view showing a process for forming the polyimide layer 30. FIG. 8 is a cross-sectional view showing the step of forming the Zn substitution film. FIG. 9 is a cross-sectional view showing the formation process of the Ni layer 24.

  First, as shown in FIG. 4, a semiconductor substrate 11 on which an IGBT having a trench gate is formed is prepared. An interlayer insulating film 21 is formed on the surface of the prepared semiconductor substrate 11, the interlayer insulating film 21 is patterned, and contacts are formed on the interlayer insulating film 21. Then, a first AlSi layer 22 is formed on the surface of the semiconductor substrate 11 exposed from the contact and the surface of the interlayer insulating film 21. That is, in the element region ER, the AlSi layer 22 as the first layer is provided in contact with the surface of the body region 15 and the surface of the emitter region 16 exposed from the contact provided in the interlayer insulating film 21. In the peripheral region PR, the AlSi layer 22 as the first layer is provided in contact with the surface of the P-type region 19 and the surface of the N + type region 20 exposed from the contact provided in the interlayer insulating film 21. In the scribe region SR, the AlSi layer 22 as the first layer is provided in contact with the surface of the N − -type drift layer 14 exposed from the contact provided in the interlayer insulating film 21. For example, the AlSi layer 22 is formed by sputtering AlSi having a Si concentration of 0.5 wt% at a substrate temperature of 400 ° C. or higher and −500 ° C. or lower. It is desirable that the thickness of the AlSi layer 22 be ensured to be equal to or larger than the contact diameter (L) so that the contact formed in the element region ER can be filled. When the contact diameter (L) is 1 μm or more, the filling is relatively easy, so that is not the case.

  Next, as shown in FIG. 5, a second AlCu layer 23 is formed on the AlSi layer 22. For example, the AlCu layer 23 is formed by sputtering AlCu having a Cu concentration of 0.5 wt% at a substrate temperature of 25 ° C. or higher and −200 ° C. or lower.

  Next, as shown in FIG. 6, the AlSi layer 22 and the AlCu layer 23 are simultaneously patterned by etching using a photomask.

  Next, after a polyimide layer 30 is formed on the surfaces of the interlayer insulating film 21, the AlSi layer 22, and the AlCu layer 23, the polyimide layer 30 is patterned by etching using a photomask as shown in FIG. Thereby, a part of the AlCu layer 23 in the element region ER is exposed from the polyimide layer 30. In the scribe region SR, the surfaces of the interlayer insulating film 21, the AlSi layer 22, and the AlCu layer 23 are exposed from the polyimide layer 30.

  Thereafter, as shown in FIG. 8, using the polyimide layer 30 as a mask, the surface of the AlCu layer 23 is subjected to double zincate treatment, and the surface of the AlCu layer 23 in the element region ER and the AlSi layer 22 and the AlCu layer 23 in the scribe region SR. A Zn substitution film 35 is formed on the surface.

  Next, the Zn substitution film 35 is substituted with Ni, Ni is deposited using the substituted Ni as a catalyst, and the Ni layer 24 is formed by electroless plating as shown in FIG. Since the Ni layer 24 is provided as a solder connection layer, a solder layer is formed on the upper side of the Ni layer 24.

  Although not shown, after the Ni layer 24, Pd, Au or the like may be continuously formed on the Ni layer 24 by an electroless plating method.

  According to the manufacturing method, one or more of the following effects can be obtained.

  Since the first layer (AlSi layer 22) is formed by sputtering AlSi, which has higher reflow performance than AlCu, at a substrate temperature equal to or higher than the solid solubility line, it is possible to fill the contacts without generating voids. it can.

  Further, since the second layer is formed on the AlSi layer 22 by sputtering AlCu at a sufficiently low substrate temperature as compared with the sputtering of AlSi, the Al grain size of the AlCu layer 23 is set to the Al grain size of the AlSi layer 22. It can be made smaller than the grain size. Thereby, the cell of the crystal orientation of the surface of the AlCu layer 23 becomes small.

  In addition, since the Zn substitution film 35 formed by the zincate process has different denseness depending on the crystal orientation of Al, the Ni crystal formed by the electroless plating method can be obtained by reducing the crystal orientation cell on the surface of the AlCu layer 23. The uniformity of the layer 24 can be improved.

  Next, the Al grain size of the AlCu layer 23 and the surface of the Ni layer 24 formed by the electroless plating method will be described with reference to FIGS. FIG. 10 is a diagram showing a surface photograph of an Al grain map of the surface of the AlCu layer 23 formed by sputtering with different substrate temperatures. FIG. 11 is a view showing a surface photograph of the Zn substitution film formed on the surface of the AlCu layer 23 formed by sputtering with different substrate temperatures. FIG. 12 is a view showing a surface photograph of the electroless Ni plating layer (Ni layer) 24 formed on the surface of the AlCu layer 23 formed by sputtering with different substrate temperatures. FIG. 13 is a diagram showing the relationship between the substrate temperature during sputtering and the Al grain size (crystal grain size) of the AlCu layer. 10 to 12, (A) shows an AlCu layer formed by sputtering at a substrate temperature of 300 ° C., and (B) shows an AlCu layer formed by sputtering at a substrate temperature of 150 ° C. It is.

  As shown in FIG. 10, the Al grain size (particle size) of the AlCu layer in (A) is about 10.5 μm on average, and the Al grain size (particle size) of the AlCu layer in (B) is about 7.3 μm. This relationship is also shown in FIG.

  As shown in FIG. 11, it can be seen that the surface of the Zn-substituted film in (A) is rougher than the surface of the Zn-substituted film in (B). That is, the surface of the Zn substitution film in FIG. 11B is smoother than the surface of the Zn substitution film in FIG.

  As shown in FIG. 12, the electroless Ni plating layer in (A) has plating depressions on its surface. On the other hand, it can be seen that the electroless Ni plating layer in (B) has a dense and uniform surface with no plating depressions on its surface.

  That is, when the AlCu layer 23 of the second layer is formed by sputtering at a substrate temperature that reduces the Al grain size, the third layer (Ni layer 24) formed on the AlCu layer 23 is uniform. It can be formed as an electroless plating layer.

  If there is a depression in the electroless Ni plating layer, impurities may diffuse from the solder layer to the AlCu layer 23 and the AlSi layer 22 from there, which may affect the electrical characteristics of the semiconductor device such as on-resistance. Further, when impurities from the solder layer diffuse to the semiconductor substrate 11 such as the body region 15 and the emitter region 16 through the AlCu layer 23 and the AlSi layer 22, the threshold value of the semiconductor device such as an insulated gate bipolar transistor is changed. The reliability of the system may be reduced.

  In the above description, an insulated gate bipolar transistor (IGBT) has been described as an example of the semiconductor element, but is not limited thereto. It can also be used as an electrode structure of a semiconductor device using a semiconductor element such as a MOSFET or a diode. When the semiconductor element is a MOSFET, the source electrode of the MOSFET can be used as the structure of the surface electrode ED. When the semiconductor element is a diode, the anode electrode can be used as the structure of the surface electrode ED. That is, the structure of the surface electrode ED can be used as an electrode structure connected to one active region (for example, an emitter region, a source region, and an anode region) of a semiconductor element provided on the semiconductor substrate 11.

  Next, Example 2 will be described with reference to the drawings.

  FIG. 14 is a cross-sectional view for explaining the semiconductor device according to the second embodiment. The semiconductor wafer 1b shown in FIG. 14 is different from the semiconductor wafer 1 shown in FIG. 1 in that a first AlSi layer 22 is embedded in a contact provided in the interlayer insulating film 21. . The surface of the first AlSi layer 22 is made lower than the surface of the interlayer insulating film 21 by etch back or the like. Other configurations are the same as those in FIG.

  Thereby, the height of the surface electrode ED, the field plate electrode FP, and the channel stopper electrode GR is lowered, and the flatness of the electrode is improved or improved.

  In addition, the surface of the AlSi layer that has a low migration resistance and easily reacts with moisture as compared with the AlCu layer can be completely covered with the AlCu layer. Thereby, migration tolerance and moisture resistance can be improved.

  In the above description, the surface of the first AlSi layer 22 is set lower than the surface of the interlayer insulating film 21, but the present invention is not limited to this. The surface of the AlSi layer 22 may be mechanically ground to the same height as the surface of the interlayer insulating film 21.

  Next, a method for manufacturing the semiconductor device 100b shown in FIG. 14 will be described with reference to the drawings.

  15 to 21 are flowcharts showing the method for manufacturing the semiconductor device 100b in cross-sectional views. More specifically, a formation process for forming the surface electrode ED on the surface of the semiconductor substrate including the semiconductor element will be described. FIG. 15 is a cross-sectional view showing a process for forming the AlSi layer 22. FIG. 16 is a cross-sectional view showing a process of etching back or grinding so that the height of the AlSi layer is below the contact. FIG. 17 is a cross-sectional view showing the step of forming the AlCu layer 23. FIG. 18 is a cross-sectional view showing the patterning process of the AlCu layer 23. FIG. 19 is a cross-sectional view showing a process for forming the polyimide layer 30. FIG. 20 is a cross-sectional view showing the step of forming the Zn substitution film. FIG. 21 is a cross-sectional view showing the formation process of the Ni layer 24.

  First, as shown in FIG. 15, a semiconductor substrate 11 on which an IGBT having a trench gate is formed is prepared. An interlayer insulating film 21 is formed on the surface of the prepared semiconductor substrate 11, the interlayer insulating film 21 is patterned, and contacts are formed on the interlayer insulating film 21. Then, a first AlSi layer 22 is formed on the surface of the semiconductor substrate 11 exposed from the contact and the surface of the interlayer insulating film 21. That is, in the element region ER, the AlSi layer 22 as the first layer is provided in contact with the surface of the body region 15 and the surface of the emitter region 16 exposed from the contact provided in the interlayer insulating film 21. In the peripheral region PR, the AlSi layer 22 as the first layer is provided in contact with the surface of the P-type region 19 and the surface of the N + type region 20 exposed from the contact provided in the interlayer insulating film 21. In the scribe region SR, the AlSi layer 22 as the first layer is provided in contact with the surface of the N − -type drift layer 14 exposed from the contact provided in the interlayer insulating film 21. For example, the AlSi layer 22 is formed by sputtering AlSi having a Si concentration of 0.5 wt% at a substrate temperature of 400 ° C. or higher and −500 ° C. or lower. It is desirable that the thickness of the AlSi layer 22 is at least a contact diameter (L) so that the contact provided in the element region ER can be filled. When the contact diameter (L) is 1 μm or more, the filling is relatively easy, so that is not the case.

  Next, as shown in FIG. 16, etch back is performed so that the height of the surface of the AlSi layer 22 is less than or equal to the surface of the interlayer insulating film 21. The AlSi layer 22 may be mechanically ground so that the surface height of the AlSi layer 22 and the surface height of the interlayer insulating film 21 are the same. The AlSi layer 22 is embedded in a contact provided on the interlayer insulating film 21. The AlSi layer 22 is etched back or mechanically ground so that it exists only in the contacts.

  In particular, according to the method of mechanically grinding and forming the AlSi layer 22 so that it exists only in the contact, silicon residue (Si residue) peculiar to the AlSi material can be effectively removed from the surface of the interlayer insulating film 21, and the surface electrode The flatness of the ED is further improved, and further, the effect of preventing the AlCu layer 23 formed thereafter from being deteriorated in adhesion with the interlayer insulating film 21 due to the Si residue is also obtained.

  Next, as shown in FIG. 17, a second AlCu layer 23 is formed on the surface of the AlSi layer 22 and on the surface of the interlayer insulating film 21. For example, the AlCu layer 23 is formed by sputtering AlCu having a Cu concentration of 0.5 wt% at a substrate temperature of 25 ° C. or higher and −200 ° C. or lower.

  Next, as shown in FIG. 18, the AlCu layer 23 is simultaneously patterned by etching using a photomask.

  Next, after the polyimide layer 30 is formed on the surfaces of the interlayer insulating film 21 and the AlCu layer 23, the polyimide layer 30 is patterned by etching using a photomask as shown in FIG. Thereby, a part of the AlCu layer 23 in the element region ER is exposed from the polyimide layer 30. In the scribe region SR, the surface of the interlayer insulating film 21 and the AlCu layer 23 is exposed from the polyimide layer 30.

  Next, as shown in FIG. 20, using the polyimide layer 30 as a mask, the surface of the AlCu layer 23 is subjected to double zincate treatment to form a surface of the AlCu layer 23 in the element region ER and a surface of the AlCu layer 23 in the element region ER. Then, a Zn substitution film 35 is formed.

  Next, the Zn substitution film 35 is substituted with Ni, Ni is deposited using the substituted Ni as a catalyst, and the Ni layer 24 is formed by electroless plating as shown in FIG. Although not shown, thereafter, Pd, Au or the like may be continuously formed on the Ni layer 24 by an electroless plating method.

  Next, Example 3 will be described with reference to the drawings.

  FIG. 22 is a cross-sectional view for explaining the semiconductor device according to the third embodiment. The semiconductor wafer 1c shown in FIG. 22 differs from the semiconductor wafer 1 shown in FIG. 1 in that the first AlSi layer 22 is not formed in the peripheral region PR and the scribe region SR, and in the element region ER. The surface and side surfaces of the AlSi layer 22 are completely covered with the AlCu layer 23. In this case, the AlSi layer 22 and the AlCu layer 23 are separately subjected to pattern etching. At this time, the end 23E of the AlCu layer 23 covering the AlSi layer 22 is located in the peripheral region PR outside the element region ER having a fine contact. As a result, the AlSi layer 22 is completely covered with the AlCu layer 23 in the element region ER, and only the AlCu layer 23 serves as an electrode (field plate electrode FP, channel stopper electrode GR) in the peripheral region PR. Migration tolerance and moisture resistance of the apparatus 100c can be improved. That is, the field plate electrode FP and the channel stopper electrode GR for holding a voltage are formed in the peripheral region PR, and are easily affected by migration and moisture intrusion. However, since the electrodes (FP, GR) in the peripheral region PR are formed only by the AlCu layer 23, it is possible to contribute to improving the reliability of the semiconductor device 100c.

  Further, a structure is formed in which the heights of the electrodes in the peripheral region PR and the scribe region SR are lower than the height of the electrode (ED) in the element region ER. Thereby, when the scribe region SR is diced by the dicing blade, the burden on the dicing blade can be reduced.

  Further, although the electrodes (FP, GR) in the peripheral region PR are configured only by the AlCu layer 23, the contact diameter of the contact provided in the peripheral region PR can be formed relatively large unlike the element region ER. Therefore, even if the AlSi layer 22 is not provided, the contact burying property in the peripheral region PR is not a problem. In addition, since the field plate electrode FP and the channel stopper electrode GR are provided for the purpose of keeping the potential of the P-type region 19 and the N− type drift layer 14 described later constant, no large current flows. Therefore, even if the field plate electrode FP and the channel stopper electrode GR are formed only by the AlCu layer 23, the influence of the connection resistance between the P-type region 19 and the N − -type drift layer 14 does not matter.

  Further, the height of the wiring provided in the peripheral region PR such as the end 23E of the electrode (ED), the gate wiring G, the field plate electrode FP, the channel stopper electrode GR, etc. is the height of the electrode (ED) provided in the element region ER. Compared to, it keeps low. Thereby, even if the mold resin which seals the semiconductor device 100c contracts, the electrode slide generated by the contraction can be effectively suppressed.

  Next, a method for manufacturing the semiconductor device 100c shown in FIG. 22 will be described with reference to the drawings.

  23 to 29 are flowcharts showing the method for manufacturing the semiconductor device 100c in cross-sectional views. More specifically, a formation process for forming the surface electrode ED on the surface of the semiconductor substrate including the semiconductor element will be described. FIG. 23 is a cross-sectional view showing the step of forming the AlSi layer 22. FIG. 24 is a cross-sectional view showing the patterning process of the AlSi layer 22. FIG. 25 is a cross-sectional view showing the step of forming the AlCu layer 23. FIG. 26 is a cross-sectional view showing the patterning process of the AlCu layer 23. FIG. 27 is a cross-sectional view showing a process for forming the polyimide layer 30. FIG. 28 is a cross-sectional view showing the step of forming the Zn substitution film. FIG. 29 is a cross-sectional view showing the formation process of the Ni layer 24.

  First, as shown in FIG. 23, a semiconductor substrate 11 on which an IGBT having a trench gate is formed is prepared. An interlayer insulating film 21 is formed on the surface of the prepared semiconductor substrate 11, the interlayer insulating film 21 is patterned, and contacts are formed on the interlayer insulating film 21. Then, a first AlSi layer 22 is formed on the surface of the semiconductor substrate 11 exposed from the contact and the surface of the interlayer insulating film 21. That is, in the element region ER, the AlSi layer 22 as the first layer is provided in contact with the surface of the body region 15 and the surface of the emitter region 16 exposed from the contact provided in the interlayer insulating film 21. In the peripheral region PR, the AlSi layer 22 as the first layer is provided in contact with the surface of the P-type region 19 and the surface of the N + type region 20 exposed from the contact provided in the interlayer insulating film 21. In the scribe region SR, the AlSi layer 22 as the first layer is provided in contact with the surface of the N − -type drift layer 14 exposed from the contact provided in the interlayer insulating film 21. For example, the AlSi layer 22 is formed by sputtering AlSi having a Si concentration of 0.5 wt% at a substrate temperature of 400 ° C. or higher and −500 ° C. or lower. It is desirable that the thickness of the AlSi layer 22 be at least a contact diameter (L) so that the contact provided in the element region ER can be filled. When the contact diameter (L) is 1 μm or more, the filling is relatively easy, so that is not the case.

  Next, as shown in FIG. 24, the AlSi layer 22 is patterned by etching using a photomask. The AlSi layer 22 is selectively provided in the element region ER and is not provided in the peripheral region PR and the scribe region SR.

  Next, as shown in FIG. 25, a second AlCu layer 23 is formed on the patterned AlSi layer 22 and the interlayer insulating film 21. For example, the AlCu layer 23 is formed by sputtering AlCu having a Cu concentration of 0.5 wt% at a substrate temperature of 25 ° C. or higher and −200 ° C. or lower.

  Next, as shown in FIG. 26, the AlCu layer 23 is patterned by etching using a photomask. In the element region ER, the AlCu layer 23 is patterned so that the AlSi layer 22 is completely covered with the AlCu layer 23. At this time, the end 23E of the AlCu layer 23 covering the AlSi layer 22 is positioned in the peripheral region PR outside the element region ER having a fine contact.

  Next, after the polyimide layer 30 is formed on the surfaces of the interlayer insulating film 21 and the AlCu layer 23, the polyimide layer 30 is patterned by etching using a photomask as shown in FIG. Thereby, a part of the AlCu layer 23 in the element region ER is exposed from the polyimide layer 30. In the scribe region SR, the surfaces of the interlayer insulating film 21 and the AlCu layer 23 are exposed from the polyimide layer 30.

  Then, as shown in FIG. 28, using the polyimide layer 30 as a mask, the surface of the AlCu layer 23 is subjected to double zincate treatment, and on the surface of the AlCu layer 23 in the element region ER and the surface of the AlCu layer 23 in the scribe region SR, A Zn substitution film 35 is formed.

  Next, the Zn substitution film 35 is substituted with Ni, Ni is deposited using the substituted Ni as a catalyst, and the Ni layer 24 is formed by electroless plating as shown in FIG. Although not shown, thereafter, Pd, Au or the like may be continuously formed on the Ni layer 24 by an electroless plating method.

  FIG. 30 is an enlarged plan view illustrating a part of the semiconductor wafer according to the first, second, and third embodiments. In FIG. 30, the scribe region SR, the peripheral region PR, and a part of the element region ER are shown enlarged. The scribe region SR is not particularly limited, but a pattern electrode TEG for mask alignment is formed. The pattern electrode TEG is an electrode (22, 23, 24, etc.) formed in the scribe region SR in FIG. 1, FIG. 2, FIG. 14, and FIG. In the peripheral region PR of the semiconductor device, a channel stopper electrode GR, a plurality of field plate electrodes FP, and a gate electrode G are sequentially provided along the direction from the scribe region SR to the element region ER. They are spaced apart to run side by side. Most of the emitter electrode (ED) is formed in the element region ER, but a part is disposed in the peripheral region PR.

  Although an insulated gate bipolar transistor (IGBT) has been described as an example of the semiconductor element, it is not limited thereto. It can also be used as an electrode structure of a semiconductor device using a semiconductor element such as a MOSFET or a diode. When the semiconductor element is a MOSFET, the source electrode of the MOSFET can be used as the structure of the surface electrode ED. When the semiconductor element is a diode, the anode electrode can be used as the structure of the surface electrode ED.

  As mentioned above, the invention made by the present inventor has been specifically described based on the examples. However, the present invention is not limited to the above-described embodiments and examples, and needless to say, various modifications can be made. .

100, 100a, 100b, 100c: Semiconductor device ER: Element region PR: Peripheral region SR: Scribe region ED: Surface electrode FP: Field plate electrode GR: Channel stopper electrode 11: Semiconductor substrate 22: First layer (AlSi layer)
23: Second layer (AlCu layer)
24: Third layer (Ni layer)

Claims (18)

A semiconductor substrate;
A surface electrode in contact with the semiconductor substrate,
The surface electrode is in the order closer to the semiconductor substrate,
The first layer;
A second layer formed on the surface of the first layer;
A third layer formed on the surface of the second layer,
The first layer is an AlSi layer;
The second layer is an AlCu layer, an AlSiCu layer, or an AlSi layer,
The third layer is a Ni layer;
The Al grain size of the second layer is smaller than the Al grain size of the first layer,
Semiconductor device. The semiconductor device according to claim 1.
The Al grain size of the first layer is 13 μm or more and −20 μm or less,
The semiconductor device, wherein the Al grain size of the second layer is 9 μm or less. The semiconductor device according to claim 1.
A semiconductor device having a barrier layer between the semiconductor substrate and the first layer. The semiconductor device according to claim 1.
The semiconductor substrate has an IGBT,
The semiconductor device, wherein the surface electrode is an emitter electrode of the IGBT. The semiconductor device according to claim 1.
The semiconductor substrate has a MOSFET,
The semiconductor device, wherein the surface electrode is a source electrode of the MOSFET. The semiconductor device according to claim 1.
The semiconductor substrate has a diode;
The semiconductor device, wherein the surface electrode is an anode electrode of the diode. A semiconductor substrate including an element region and a peripheral region provided so as to surround the element region;
A surface electrode provided in the element region and in contact with the semiconductor substrate;
A field plate electrode provided in the peripheral region and in contact with the semiconductor substrate,
The surface electrode is in the order closer to the semiconductor substrate,
The first layer;
A second layer formed on the surface of the first layer;
A third layer formed on the surface of the second layer,
The first layer is an AlSi layer;
The second layer is an AlCu layer, an AlSiCu layer, or an AlSi layer,
The third layer is a Ni layer;
The field plate electrode includes the first layer and the second layer, or the second layer.
Semiconductor device. The semiconductor device according to claim 7.
A channel stopper electrode provided in the peripheral region and in contact with the semiconductor substrate;
The semiconductor device, wherein the field plate electrode is provided between the channel stopper electrode and the surface electrode. The semiconductor device according to claim 8.
The channel stopper electrode includes the first layer and the second layer, or the second layer. The semiconductor device according to claim 9.
The Al grain size of the first layer is 13 μm or more and −20 μm or less,
The semiconductor device, wherein the Al grain size of the second layer is 9 μm or less. The semiconductor device according to claim 7.
The Al grain size of the first layer is 13 μm or more and −20 μm or less,
The semiconductor device, wherein the Al grain size of the second layer is 9 μm or less. The semiconductor device according to claim 7.
The semiconductor substrate has an IGBT,
The semiconductor device, wherein the surface electrode is an emitter electrode of the IGBT. The semiconductor device according to claim 7.
An insulating film provided on a surface of the semiconductor substrate and having a contact;
The surface of the semiconductor substrate is exposed at the contact,
The semiconductor device, wherein the first layer is embedded in the contact. The semiconductor device according to claim 7.
In the element region, the second layer is provided so as to cover the first layer,
An end of the second layer is a semiconductor device located in the peripheral region. Forming a surface electrode on a surface of a semiconductor substrate including a semiconductor element;
The process includes
A first step of forming a first layer;
A second step of forming a second layer on the surface of the first layer;
A third step of forming a third layer on the surface of the second layer,
The first step includes a step of forming the first layer by sputtering AlSi at a substrate temperature of 400 ° C. or higher.
The second step includes a step of forming the second layer by sputtering AlCu, AlSiCu or AlSi at a substrate temperature of 200 ° C. or less,
The third step includes a step of forming Ni on the surface of the second layer by electroless plating to form the third layer.
A method for manufacturing a semiconductor device. In claim 15,
The third step includes
Forming a Zn-substituted film by zincating the surface of the second layer;
Replacing the Zn-substituted film with Ni, depositing Ni using the substituted Ni as a catalyst, and forming the third layer by the electroless plating method. In claim 15,
The first step includes
Forming a contact on an insulating film provided on a surface of the semiconductor substrate;
Forming a first AlSi layer on the surface of the semiconductor substrate exposed from the contact and on the surface of the insulating film;
And a step of etching back or grinding the first layer so that the first layer is embedded inside the contact. In claim 15,
The first step includes a step of patterning the first layer so as to be selectively provided in an element region of the semiconductor substrate,
In the second step, the second layer is patterned so as to cover the surface and side surfaces of the patterned first layer, and the end of the second layer is located in the peripheral region of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising:

Images