JP2004079800A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of high output operation at a high frequency band with a small drain capacitance. <P>SOLUTION: This semiconductor device comprises a semiconductor substrate, a gate electrode 3 arranged on the semiconductor substrate through an insulating film, a drain region in which first low concentration impurity diffusion layers and dot-shaped second high concentration impurity diffusion layers 45 are arranged in parallel to the gate electrode 3 at a plurality of positions, an interlayer insulating film 9a having dot-shaped contact holes 53 arranged inside by given intervals from the respective dot-shaped peripheries on the second high concentration impurity diffusion layers 45, metal wiring for the drain formed on the interlayer insulating film 9a while burying the dot-shaped contact holes 53 therein in the drain region, and a source region composed of a third impurity diffusion layer 41. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device for amplifying a high-frequency signal and a method for manufacturing the same.
[0002]
[Prior art]
As a transistor for amplifying a high-frequency signal of about 1 to 10 GHz of a mobile phone or the like to a power of about 0.1 to 100 W and transmitting it as radio waves to the air via an antenna, an LDMOS (Laterally Diffused) applying silicon MOS technology There is a Metal Oxide Semiconductor (Transistor) transistor. FIG. 12 is a plan view of a conventional LDMOS transistor, and FIG. 13 is a cross-sectional structure of the LDMOS transistor along the line AA ′ in FIG. In the figure, 1 is an active layer (silicon), 2 is a P-type source wireless diffusion layer (boron (B) is 1 × 10 ¹⁷ / Cm ³ 3) is a gate electrode (for example, a film in which WSi having a thickness of 300 nm is laminated on polycrystalline silicon having a thickness of 100 nm), 9a and 9b are interlayer insulating films (SiO 2). ₂ ) And 11 are isolation oxide films (SiO 2 of about 1 μm thickness). ₂ ), 12 is a P-type silicon substrate having a specific resistance of 10 mΩ · cm, 13 is a P-type silicon layer having a specific resistance of 10 Ω · cm formed on the P-type silicon substrate 12 by epitaxial crystal growth, and 14 is below the isolation oxide film 11. P-type isolation diffusion layer (boron (B) is 4 × 10 ^Fifteen / Cm ³ To a high concentration impurity diffusion layer (N) on the source region side. ⁺ Arsenic (As) is 1 × 10 ²¹ / Cm ³ Refers to the silicon content. Note that " ⁺ "" Indicates that the impurity concentration is high.
[0003]
42 is N on the drain region side ⁺ Diffusion layer (arsenic (As) is 1 × 10 ²¹ / Cm ³ Silicon), 43 is a P-type impurity diffusion layer (boron (B) is 1 × 10 ¹⁷ / Cm ³ To a low concentration impurity diffusion layer (N) provided on the drain region side. ⁻ Diffusion layer), for example, phosphorus (P) is 5 × 10 ¹⁷ / Cm ³ Refers to the silicon content. Note that " ⁻ Indicates that the impurity is N ⁺ This indicates a lower concentration. Reference numeral 44a denotes N existing only at the end of the active layer 1. ⁻ Diffusion layer (phosphorus (P) is 5 × 10 ¹⁷ / Cm ³ Silicon), 51 is a contact hole on the source region side, 52 is a contact hole on the drain region side, 6a and b are first aluminum (Al) wires (thickness 500 nm), 71 is a source region side contact hole. Reference numeral 72 denotes a through hole on the drain region side, and reference numerals 8a and b denote second aluminum (Al) wirings (thickness: 2 μm).
[0004]
The width (lateral direction, gate length direction in FIG. 12) of the contact hole 52 on the drain region side is 2 μm, while the length (vertical direction, gate width direction in FIG. 12) is 180 μm, and has a rectangular shape. ing. The width of the second high-concentration impurity diffusion layer 42 on the drain region side below the contact hole 52 is 4 μm, and the length is 184 μm in a rectangular shape. That is, the contact hole 52 is provided 2 μm in the horizontal direction and 4 μm in the vertical direction in FIG. 12 with respect to the second high-concentration impurity diffusion layer 42.
[0005]
Next, the structure and operation of a conventional LDMOS transistor will be briefly described. The third high-concentration impurity diffusion layer 41 on the source region side includes a first aluminum wiring 6b on the source region side formed in the contact hole 51, and a second aluminum wiring on the source region formed in the through hole 71. 8b, it is connected to the source wireless diffusion layer 2. On the other hand, the source wireless diffusion layer 2 is connected to a silicon substrate 12 having a specific resistance of 10 mΩ · cm. Therefore, the source region of the LDMOS transistor can be connected to the outside by grounding the silicon substrate 12, so that it is not necessary to provide a bonding wire from above the chip. By the way, this is the reason for source wireless. By not providing the bonding wire only on the source region side, the inductance component (resistance) of the bonding wire is reduced, so that a high-frequency signal can be stably amplified.
[0006]
The drain region is formed of a first low-concentration impurity diffusion layer (hereinafter simply referred to as “first N ⁻ Diffusion layer ". ) 44 and a second high-concentration impurity diffusion layer (hereinafter simply referred to as “second N ⁺ 42). 2nd N ⁺ The distance between the diffusion layer 42 and the end of the gate electrode 3 in the gate length direction is set to 3 μm. Also, the second N ⁺ Diffusion layer 42 is connected to an external bonding wire (not shown) via contact hole 52, first aluminum wiring 6a on the drain region side, through hole 72, and second aluminum wiring 8a on the drain region side. .
[0007]
Here, a case is considered where the voltage of the gate electrode is 0 V, the voltage of the source electrode (silicon substrate 12) is 0 V, and a positive voltage is applied to the drain terminal (bonding wire (not shown) connected to the drain). In this case, since the voltage of the gate electrode 3 is 0 V, the LDMOS transistor is off, and no current (drain current) flows between the source and the drain. Here, when the drain voltage increases, a depletion layer (not shown) in the drain region extends immediately below the gate electrode 3 and a high concentration impurity diffusion layer on the source region side (hereinafter simply referred to as “third N ⁺ (Diffusion layer) 41) and the third N on the source region side. ⁺ By lowering the potential barrier of the diffusion layer 41, a so-called punch-through current flows between the source and the drain. The drain voltage at which the punch-through current flows is defined as the source-drain breakdown voltage.
[0008]
In the LDMOS transistor, the first N on the drain region side ⁻ The width of the diffusion layer 44 in the gate length direction is equal to the third N on the source region side. ⁺ Since the diffusion layer 41 is larger than the width in the gate length direction, that is, the distance directly below the gate electrode 3 is long, a depletion layer (not shown) generated in the drain region is formed in the third N region on the source region side. ⁺ As a result, a large (for example, 75 V) drain voltage is required to come into contact with the diffusion layer 41, so that the withstand voltage between the source and the drain is improved.
[0009]
The P-type impurity diffusion layer 43 located immediately below the gate electrode 3 is provided to set the threshold voltage (Vth) of the LDMOS transistor to about 1V. The reason why such a P-type impurity diffusion layer is not provided on the drain region side is that the second N ⁺ The diffusion layer 42 and the first N ⁻ This is for preventing the impurity concentration of the P-type impurity region 13 in contact with the diffusion layer 44 from increasing as much as possible. When the concentration of the P-type impurity on the drain region side increases, the depletion layer of the PN junction on the drain region side becomes narrower, and the capacitance of the depletion layer increases. This means that the capacitance between the drain and the semiconductor substrate increases, which adversely affects the high-frequency operation. Incidentally, the fact that the P-type impurity diffusion layer 43 is not provided on the drain region side, that is, that there is a concentration gradient in the gate length direction is derived from the name of LDMOS Laterally Diffused.
[0010]
It is to be noted that the case where the above-mentioned source region side high concentration impurity diffusion layer 41 has a high impurity concentration is described. Generally, a region having a low impurity concentration is rarely provided in the impurity diffusion layer 41 on the source side. However, if the impurity diffusion region 41 on the source region side opposite to the gate electrode 3 is provided with a low impurity concentration region, If provided, the width of the low impurity concentration region on the source region side in the gate length direction is the first N ⁻ The width is set shorter than the width of the diffusion layer 44 in the gate length direction.
[0011]
When a voltage equal to or higher than the threshold voltage (Vth) is applied to the gate electrode 3 and a positive voltage is applied to the drain region, the LDMOS transistor is turned on, and a current flows between the source / drain regions. However, when the drain voltage increases, the first N ⁻ The diffusion layer 44 is depleted from the gate electrode 3 side, and when the drain voltage reaches 28 V, the first N ⁻ All the diffusion layers 44 are depleted.
[0012]
Next, a conventional method for manufacturing an LDMOS transistor will be briefly described with reference to FIGS. 14 to 18 are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device. 12 and 13 are the same or equivalent.
[0013]
After the source wireless diffusion layer 2 and the P-type separation / diffusion layer 14 are formed in the silicon substrate by impurity ion implantation, LOCOS oxidation is performed around the source / drain regions to provide element separation regions for electrically separating the respective elements. An isolation oxide film 11 is formed by a method. Subsequently, a P-type impurity diffusion layer 43 is formed in a portion extending below the gate electrode region and the source region by impurity ion implantation. Further, after forming a gate oxide film 31 on the silicon substrate to a thickness of about 50 nm, a gate electrode material is deposited and patterned to form a gate electrode 3.
[0014]
Subsequently, phosphorus is ion-implanted into the entire surface of the wafer to further perform heat treatment, and the first N ⁻ Diffusion layer 44 and N ⁻ The diffusion layer 44a is formed. Phosphorus is not ion-implanted immediately below the gate electrode 3, and the region of the source wireless diffusion layer 2 and the P-type impurity diffusion layer 43 has a high P-type impurity concentration. , In the region of the P-type impurity diffusion layer 43, N ⁻ No diffusion layer is formed. FIG. 14 shows a cross-sectional view of the LDMOS transistor when the above steps are completed.
[0015]
Next, N in the source / drain region ⁺ The portion other than the region where the diffusion layer is formed is covered with the resist film 47 (FIG. 15). Using the resist film 47 as an ion implantation mask, arsenic (As) is ion-implanted and heat treatment is further performed. ⁺ Diffusion layer 41 and second N on drain region side ⁺ The diffusion layer 42 is formed.
[0016]
Subsequently, an interlayer insulating film 9a is formed on the silicon substrate by the CVD method, and a contact hole 52 on the drain region side and a contact hole 51 on the source region side penetrating the interlayer insulating film 9a are formed by photolithography and etching. (FIG. 16). Note that the gate oxide film 31 is not shown in the cross-sectional views for respective steps after FIG.
[0017]
Next, an aluminum film is deposited on the interlayer insulating film 9a so as to fill the contact holes 51 and 52, and first aluminum wirings 6a and 6b are formed by photolithography and etching (FIG. 17).
[0018]
Further, an interlayer insulating film 9b is formed on the wafer, and a through-hole 71 on the source region side and a through-hole 72 on the drain region side are formed by photolithography technology and insulating film etching technology (FIG. 18).
[0019]
Finally, an aluminum film is deposited, and second aluminum wirings 8a and 8b are formed by photolithography and etching to complete the process. FIG. 13 is a structural sectional view of an LDMOS transistor completed through the above-described wafer process.
[0020]
[Problems to be solved by the invention]
As described above, the LDMOS transistor has an improved high-frequency characteristic by means of shortening the gate length (for example, 0.5 μm), adopting a source wireless structure, and not providing a Vth setting P-type impurity diffusion layer on the drain region side. And N on the drain region side ⁺ The breakdown voltage between the source and the drain is improved by separating the diffusion layer from the gate electrode. However, in order to realize a transistor capable of higher output operation in a high frequency band, it is necessary to further reduce the drain capacitance located on the output side.
[0021]
The drain capacitance mainly depends on the second N on the drain region side. ⁺ Diffusion layer 42 and first N on drain region side ⁻ It is composed of an N-type diffusion layer including the diffusion layer 44 and a PN junction capacitance formed between the P-type silicon layer 13 below the drain region. When the drain voltage increases, the first N ⁻ Since the diffusion layer 44 is almost depleted, it does not contribute to the drain capacitance. Therefore, the second N on the drain region side ⁺ If the area of the region of the diffusion layer 42 is reduced, the drain capacitance is reduced.
[0022]
As a device structure for reducing the drain capacitance, a structure of a conventional semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 5-121739. However, such a device structure can realize a large source / drain withstand voltage of 70 V or more which is practically necessary. Did not. The reason is as follows.
[0023]
Only by securing the distance between the opposite ends of the drain diffusion layer and the gate electrode, the drain N ⁺ If the distance between the diffusion layer and the isolation oxide film is short, the depletion layer does not spread very much when a high voltage is applied to the drain. Drain N ⁺ The layer is an N-type, and a PN junction is formed of P-type silicon below the isolation oxide film. However, when the impurity concentration is high, the depletion layer generally does not spread. In the case of such a conventional structure, the drain N ⁺ In the diffusion layer, the concentration of the N-type impurity is high, and the drain N ⁺ Since the distance between the diffusion layer and the isolation oxide film is short, the depletion layer becomes narrow. For this reason, the electric field of such a depletion layer becomes extremely large, and breakdown occurs between the source / drain regions due to avalanche collapse. That is, the source / drain breakdown voltage deteriorates. Since the silicon under the isolation oxide film is P-type and is connected to a layer corresponding to the source wireless layer, it has zero potential, while silicon on the drain region side has N potential. ⁺ The diffusion layer has a positive voltage. Therefore, a reverse voltage is applied to the PN junction in this region, and no current normally flows. However, the silicon layer below the isolation oxide film often has minute defects. There is a problem that the source / drain breaks down with a smaller electric field (drain voltage).
[0024]
As a structure for further reducing the drain capacitance, there is a structure of a conventional semiconductor device disclosed in Japanese Patent Application Laid-Open No. 10-214971. FIG. 19 schematically shows the element structure of the disclosed conventional semiconductor device. ⁺ Diffusion layer, N ⁻ The diffusion layer and the Al wiring are omitted. In the conventional transistor of FIG. 19, the drain region side contact hole 52 and the drain region side second N ⁺ A diffusion layer 42 is disposed, an octagonal gate electrode 3 is formed around the diffusion layer 42, and a source region side contact hole 51 is formed on the outermost side in the N region on the drain region side. ⁺ It is formed so as to surround the diffusion layer 52. By arranging a plurality of transistors in a basic unit as shown in FIG. 19 vertically and horizontally and electrically connecting them in parallel, an entire transistor is formed. The gate electrode 3 is connected to an outer gate terminal by a gate electrode 3a for extraction. In such a conventional transistor structure, since the area of the drain region per unit gate width (corresponding to the length of one circumference of the gate electrode 3) is small, the entire drain capacitance is certainly reduced.
[0025]
However, in the structure of the conventional semiconductor device shown in FIG. 19, the presence of the extraction gate electrode 3a which is not involved in the drain current cannot be avoided. That is, since the extraction gate electrode 3a is on the active layer 1 and only a thin gate oxide film exists between the extraction gate electrode 3a and silicon, this transistor structure has a very large parasitic gate / source capacitance. (Ie, input capacitance). Due to such a large input capacitance, there is a trade-off relationship that even if the output capacitance is reduced, the high-frequency characteristics are not improved.
[0026]
An object of the present invention is to provide a semiconductor device capable of high-output operation in a high-frequency band by reducing the drain capacitance without increasing the input capacitance of a semiconductor device such as an LDMOS transistor, and a method of manufacturing the same.
[0027]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating film, and a first low-concentration impurity formed in the semiconductor substrate on one side of the gate electrode. A second diffusion layer which is provided inside the diffusion layer and the first low-concentration impurity diffusion layer, has a higher impurity concentration than the first low-concentration impurity diffusion layer, and has a dot shape when projected onto the main surface of the semiconductor substrate; A second drain region in which a plurality of high-concentration impurity diffusion layers are arranged at a plurality of locations in a direction parallel to the gate electrode; An interlayer insulating film having a formed dot-shaped contact hole, and a drain metal layer formed on the interlayer insulating film while filling the dot-shaped contact hole in the drain region. When, with a, a source region and a third impurity diffusion layer formed in the semiconductor substrate on the other side of the gate electrode.
[0028]
Further, in the semiconductor device according to the present invention, the width of the low impurity concentration region in the third impurity diffusion layer is smaller than the width of the first low concentration impurity diffusion layer in the gate length direction.
[0029]
Further, in the semiconductor device according to the present invention, the distance between the opposing sides of the dot-shaped second high-concentration impurity diffusion layer and the dot-shaped contact hole is set to 0.02 μm or more and 0.3 μm or less.
[0030]
In addition, a semiconductor device according to the present invention includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate with an insulating film interposed therebetween, and a first gate formed in the semiconductor substrate on one side of the gate electrode. A first impurity diffusion layer having a higher impurity concentration than the first lightly doped impurity diffusion layer provided inside the first lightly doped impurity diffusion layer and the first lightly doped impurity diffusion layer; A drain region having a second high-impurity diffusion layer having a rectangular shape having long sides parallel to the direction; and a rectangular region formed on the semiconductor substrate and on the second rectangular high-concentration impurity diffusion layer. An interlayer insulating film having a rectangular contact hole provided further inside by a predetermined distance; and a drain metal formed on the interlayer insulating film while filling the rectangular contact hole in the drain region. A third impurity diffusion layer formed in the semiconductor substrate on the other side of the gate electrode, wherein the width of the low impurity concentration region in the third impurity diffusion layer in the gate length direction is the first impurity diffusion layer; A source region smaller than the width of the low-concentration impurity diffusion layer; and an element isolation insulating film disposed around the source / drain region on the semiconductor substrate, wherein the element isolation insulating film in a gate width direction is provided. The distance between the opposite ends of the second high-concentration impurity diffusion layer is longer than the distance between the second high-concentration impurity diffusion layer and the opposite ends of the gate electrode in the gate length direction. .
[0031]
Further, in the semiconductor device according to the present invention, the interval between the rectangular second high-concentration impurity diffusion layer and each of the opposing sides of the rectangular contact hole is set to 0.02 μm or more and 0.3 μm or less.
[0032]
In the semiconductor device according to the present invention, the third impurity diffusion layer has a high impurity concentration.
[0033]
Further, in the semiconductor device according to the present invention, the conductivity types of the first low-concentration impurity diffusion layer, the second high-concentration impurity diffusion layer, and the third impurity diffusion layer are all N-type.
[0034]
A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a P-type isolation diffusion layer in an element isolation region located around the source / drain region of a semiconductor substrate by ion implantation of an impurity; Forming an isolation insulating film, forming a P-type impurity diffusion layer below the gate electrode region and a portion extending over the source region by ion implantation of impurities, and forming a gate oxide film on the semiconductor substrate Forming a gate electrode in the gate electrode region on the gate oxide film; forming a first N-type low concentration impurity diffusion layer in the drain region by ion implantation of impurities; Forming a third N-type high-concentration impurity diffusion layer inside the P-type impurity diffusion layer in the source region, and forming an interlayer insulating layer on the semiconductor substrate. Forming a contact hole on the drain region and a contact hole on the source region through the interlayer insulating film on the drain region and the source region by photolithography and insulating film etching. A resist film having only a contact hole portion on the drain region side is formed on the interlayer insulating film by a lithography technique, and the first film is formed by ion implantation of impurities using the resist film and the interlayer insulating film as an ion implantation mask. Forming a second N-type high-concentration impurity diffusion layer inside the N-type low-concentration impurity diffusion layer; and forming the contact hole on the drain region side on the interlayer insulating film in the drain region. Forming a metal wiring for drain. The main surface to the projected shape of said semiconductor substrate at a high concentration impurity diffusion layer was to be determined by the opening of contact holes in the drain region side.
[0035]
Further, in the method for manufacturing a semiconductor device according to the present invention, the distance between the second N-type high-concentration impurity diffusion layer and the opposite end of the contact hole on the drain region side is set to 0.02 μm or more and 0.3 μm or less. And
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, the structure of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view showing the structure of an LDMOS transistor of the present invention. FIG. 2 is a sectional view taken along line BB ′ of FIG. 1, and FIG. 3 is a sectional view taken along line CC ′ of FIG. FIG. 4 is a sectional view of an element. In the figure, 1 is an active layer (silicon), 2 is a P-type source wireless diffusion layer (boron (B) is 1 × 10 ¹⁷ / Cm ³ Silicon), 3 is a gate electrode (for example, a film in which tungsten silicide (WSi) having a thickness of 300 nm is stacked on polycrystalline silicon having a thickness of 100 nm), and 6a is first aluminum on the drain region side. A wiring (metal wiring for drain), 6b is a first aluminum wiring (thickness: 500 nm) on the source region side, 8a is a second aluminum wiring on the drain region side, and 8b is a second aluminum wiring (thickness) on the source region side. 9a and 9b are interlayer insulating films (SiO 2 ₂ ), 11 is an isolation oxide film (insulating film for element isolation, about 1 μm thick SiO 2). ₂ ), 12 is a P-type silicon substrate (a type of semiconductor substrate, for example, a P-type silicon substrate having a specific resistance of 10 mΩ · cm), and 13 is formed on the P-type silicon substrate 12 by epitaxial crystal growth. Cm of a P-type silicon layer, 14 is a P-type isolation diffusion layer formed under the isolation oxide film 11 (for example, 4 × 10 ^Fifteen / Cm ³ To the source region side, a third high-concentration impurity diffusion layer (third N ⁺ Arsenic (As) is 1 × 10 ²¹ / Cm ³ Refers to the silicon content. By the way, " ⁺ "Indicates that the impurity concentration is high, and 2.6 × 10 ¹⁹ / Cm ³ More than 2 × 10 ²¹ / Cm ³ It represents the impurity concentration in the following range.
[0037]
It is to be noted that the case where the above-mentioned source region side high concentration impurity diffusion layer 41 has a high impurity concentration is described. Generally, a region having a low impurity concentration is rarely provided in the third impurity diffusion layer 41 on the source side. However, if a low impurity concentration region When the impurity concentration region is provided, the width of the low impurity concentration region on the source region side in the gate length direction is equal to the width of the first N region on the drain region side. ⁻ The width is set shorter than the width of the diffusion layer 44 in the gate length direction.
[0038]
43 is a P-type impurity diffusion layer (for example, boron (B) is 1 × 10 ¹⁷ / Cm ³ To a low concentration impurity diffusion layer (N) existing only at the end of the active layer 1. ⁻ Diffusion layer, for example, phosphorus (P) is 5 × 10 ¹⁷ / Cm ³ Silicon), and a first low-concentration impurity diffusion layer (first N ⁻ Diffusion layer), for example, phosphorus (P) is 5 × 10 ¹⁷ / Cm ³ Refers to the silicon content. Note that " ⁻ Indicates that the impurity is N ⁺ Lower concentration, 2 × 10 ¹⁶ / Cm ³ 1.3 × 10 ¹⁹ / Cm ³ It represents the impurity concentration in the following range. 45 is a second high-concentration impurity diffusion layer (second N-type impurity diffusion layer) provided on the drain region side. ⁺ A diffusion layer, for example, arsenic (As) of 1 × 10 ²¹ / Cm ³ Silicon), 51 is a contact hole on the source region side, 53 is a contact hole on the drain region side, 71 is a through hole on the source region side, and 72 is a through hole on the drain region side.
[0039]
Second N on the drain region side in the semiconductor device according to the first embodiment. ⁺ The shape of the diffusion layer 45 projected on the main surface of the semiconductor substrate is a square dot shape having a side of about 2.2 μm, and a plurality of dots are provided in parallel with the gate electrode 3 in the gate width direction. (FIG. 1). The second N of the dot shape on the drain region side ⁺ On the diffusion layer 45, a drain region side contact hole 53 having a side of 2 μm and also having a dot shape is provided through the interlayer insulating film 9a. That is, the dot shape of the opening of the contact hole 53 is the second N ⁺ The opposite sides of the dot shape of the diffusion layer 45 are formed on the inside such that the opposing sides are substantially at equal intervals. The distance between the two is preferably in the range of 0.02 to 0.3 μm. 2nd N ⁺ The diffusion layer 45 is connected to the first aluminum wiring (drain metal wiring) 6 a on the drain region side buried in the contact hole 53. Note that the interval between the dot-shaped contact holes 53 on the drain region side is 3 μm, and the second N ⁺ The distance between the opposing ends of the diffusion layer 45 and the gate electrode 3 is 3 μm.
[0040]
As described above, in the semiconductor device according to the first embodiment, the second high-concentration impurity diffusion layer (N ⁺ The diffusion layer) has a plurality of dot shapes, and each contact hole on the drain region side also has a second N ⁺ Since the dots are formed inside the diffusion layer 45 so that each side is substantially equidistant from the dots, contact between the drain region and the first aluminum wiring (drain metal wiring) 6a on the drain region side is made. Since the area is smaller than that of the conventional structure, the drain capacitance is reduced. As a result, a semiconductor device which can operate at high frequency and under high voltage can be obtained.
[0041]
In the first embodiment, the inside of the contact hole 53 on the drain region side is buried with aluminum. However, as shown in FIG. FIG. 5 shows a cross-sectional structure along the line CC ′ of FIG. 1 in the case of the plug structure 61. Also in the case of the plug structure, the same effect as in the first embodiment can be obtained.
[0042]
In the first embodiment, the LDMOS transistor structure has been described for the sake of convenience. However, the basic structure of the semiconductor device may be a general MOS transistor structure. In this case, the same effect as that of the LDMOS transistor structure can be obtained. .
[0043]
Embodiment 2 FIG.
The structure of the semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 6 is a plan view of the LDMOS transistor according to the second embodiment, and FIG. 7 is a cross-sectional view of the device along the line DD ′ in FIG. The components denoted by the same reference numerals as those in the first embodiment are the same or corresponding components. 6 and 7, reference numeral 46 denotes a second high-concentration impurity diffusion layer (N ⁺ Reference numeral 54 denotes a contact hole on the drain region side.
[0044]
41 is a third high-concentration impurity diffusion layer (third N ⁺ Arsenic (As) is 1 × 10 ²¹ / Cm ³ Refers to the silicon content. By the way, " ⁺ Indicates that the impurity concentration is high. In general, a region with a low impurity concentration is scarcely provided in the third impurity diffusion layer 41 on the source side. When the low impurity concentration region is provided in the impurity diffusion layer 41 on the source region side on the side of the drain region, the width of the low impurity concentration region on the source region side in the gate length direction is equal to the first N region on the drain region side. ⁻ The width is set shorter than the width of the diffusion layer 44 in the gate length direction.
[0045]
A characteristic part of the semiconductor device according to the second embodiment as compared with the conventional semiconductor device is the second N ⁺ These are the diffusion layer 46 and the drain region side contact hole 54 provided thereon. 2nd N ⁺ The diffusion layer 46 has a rectangular shape with a width of 2.2 μm and a length of 180.2 μm. Further, the second N ⁺ A rectangular drain region side contact hole 54 having a width of 2 μm and a length of 180 μm is arranged on the diffusion layer 46. ⁺ The diffusion layer 46 is connected to the first aluminum interconnection 6a on the drain region side. The size of the drain region side contact hole 54 is exactly the same as the conventional element structure. That is, the second N ⁺ The diffusion layer 46 has a rectangular shape in which each side of the drain region side contact hole 54 is extended at an interval of 0.1 μm. Therefore, the second N ⁺ Since the area of the projection surface of the diffusion layer 46 onto the main surface of the wafer is substantially the same as the area of the opening of the contact hole 54, the second N ⁺ As a result of the reduction in the area of the diffusion layer 46 projected onto the main surface of the wafer, the drain capacitance can be reduced.
[0046]
In addition, the second N ⁺ The distance in which the diffusion layer 46 is extended, that is, the interval is preferably in the range of 0.02 to 0.3 μm. This is because if the interval is small, manufacturing becomes difficult, while if the interval is increased, the drain capacitance increases.
[0047]
In the semiconductor device according to the second embodiment, the cross-sectional view taken along line EE ′ of FIG. 6 has the same shape as that of FIG. ⁺ The diffusion layer 45 is ⁺ The diffusion layer 46 is obtained by replacing the drain region contact hole 53 with a contact hole 54.
[0048]
Further, regarding the distance between the ends in the gate width direction, the second N ⁺ The distance between the opposing ends of the diffusion layer 46 and the isolation oxide film 11 is 4 μm (L1 in FIGS. 6 and 7), and the second N on the drain region side in the gate length direction. ⁺ The distance between the end of the diffusion layer 46 and the gate electrode 3 is longer than 3 μm (L2 in FIG. 6), that is, the distance is longer. The reason for this is that when a high voltage is applied to the drain region, the isolation oxide film 11 is applied so that current does not flow from the drain region to the P-type silicon substrate 12 through crystal defects existing under the isolation oxide film 11. To reduce the electric field, the second N ⁺ This is because it is necessary to separate the diffusion layer 46 from the isolation oxide film 11. Therefore, while maintaining the above relationship, the second N ⁺ The distance between the diffusion layer 46 and the end of the gate electrode 3 and the second N ⁺ By sufficiently increasing the distance between the opposing ends of the diffusion layer 46 and the isolation oxide film 11, a high source / drain withstand voltage can be realized.
[0049]
Embodiment 3 FIG.
A method for manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS. 8 to 11 are cross-sectional views illustrating steps in a method for manufacturing the semiconductor device according to the third embodiment. In the figure, 31 indicates a gate oxide film (insulating film), and 47 indicates a resist film. The components denoted by the same reference numerals as those in the first or second embodiment are the same or corresponding components.
[0050]
After the source wireless diffusion layer 2 and the P-type separation / diffusion layer 14 are formed in the silicon substrate by impurity ion implantation, LOCOS oxidation is performed around the source / drain regions to provide element separation regions for electrically separating the respective elements. An isolation oxide film 11 is formed by a method. Subsequently, a P-type impurity diffusion layer 43 is formed in a portion extending below the gate electrode region and the source region by impurity ion implantation. Further, after forming a gate oxide film 31 on the silicon substrate to a thickness of about 50 nm, a gate electrode material is deposited and patterned to form a gate electrode 3.
[0051]
Subsequently, phosphorus is ion-implanted into the entire surface of the wafer to further perform heat treatment, and the first N ⁻ Diffusion layer 44 and N ⁻ The diffusion layer 44a is formed. Phosphorus is not ion-implanted immediately below the gate electrode 3, and the region of the source wireless diffusion layer 2 and the P-type impurity diffusion layer 43 has a high P-type impurity concentration. , N in the region of the P-type impurity diffusion layer 43. ⁻ No diffusion layer is formed. FIG. 8 shows a cross-sectional view of the LDMOS transistor when the above steps are completed. The steps up to here are the same as those of the conventional method of manufacturing a semiconductor device (FIG. 14).
[0052]
Next, the third N of the source region ⁺ A region other than the region where the diffusion layer 41 is formed is covered with the resist film 47. Arsenic is ion-implanted using the resist film 47 as an ion implantation mask to form a third N region on the source region side. ⁺ Only the diffusion layer 41 is formed (FIG. 9).
[0053]
Subsequently, an interlayer insulating film 9a is formed by a CVD method, and a drain region side contact hole 53 and a source region side contact hole 51 are opened by a photolithography technique and an insulating film etching technique (FIG. 10). It should be noted that the gate oxide film 31 is not shown in the cross-sectional views for respective steps after FIG.
[0054]
Next, a resist film 47 having an opening only in the contact hole 53 on the drain region side is formed by photolithography (FIG. 11). Arsenic (As) is ion-implanted using the resist film 47 and the interlayer insulating film 9a as an ion implantation mask to form a second N ⁺ A diffusion layer 45 is formed. Since the interlayer insulating film 9a is sufficiently thick (approximately 500 nm) with respect to the depth of penetration of arsenic (approximately 26 nm at an acceleration voltage of 50 keV), arsenic is not implanted except in the region of the contact hole opening 53. The implanted arsenic diffuses by about 0.1 μm from the end of the drain region side contact hole 53 to the outside of the drain region side contact hole opening 53 due to a scattering phenomenon at the time of ion implantation and a subsequent heat treatment. 2nd N ⁺ A diffusion layer 45 is formed. In other words, the second N having a shape substantially equal to the opening of the drain region side contact hole 53 is formed. ⁺ A diffusion layer 45 is formed.
[0055]
Next, an aluminum film is deposited on the interlayer insulating film 9a so as to fill the contact holes 51 and 53, and first aluminum wirings 6a and 6b are formed by photolithography and etching.
[0056]
Further, an interlayer insulating film 9b is formed on the wafer, and a through-hole 71 on the source region side and a through-hole 72 on the drain region side are formed by photolithography and etching.
[0057]
Finally, an aluminum film is deposited, and second aluminum wirings 8a and 8b are formed by photolithography and etching to complete the process. FIG. 2 is a sectional view of the structure of the LDMOS transistor after the wafer process is completed.
[0058]
As described above, according to the method of manufacturing the semiconductor device according to the third embodiment, the resist film 47 having only the contact hole region on the drain region side is formed, and the resist film 47 and the interlayer insulating film 9a are used as an ion implantation mask to form an impurity. Is implanted into the second N ⁺ Since the diffusion layer 45 is formed, the second N layer having a shape substantially equal to the contact hole 53 on the drain region side is formed. ⁺ Since the diffusion layer 45 can be easily formed, as a result of the reduced drain capacitance according to the first or second embodiment, a semiconductor device capable of high-output operation in a high-frequency band can be easily manufactured with good reproducibility.
[0059]
【The invention's effect】
In a semiconductor device according to the present invention, a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating film, and a first low-concentration impurity formed in the semiconductor substrate on one side of the gate electrode A second diffusion layer which is provided inside the diffusion layer and the first low-concentration impurity diffusion layer, has a higher impurity concentration than the first low-concentration impurity diffusion layer, and has a dot shape when projected onto the main surface of the semiconductor substrate; A second drain region in which a plurality of high-concentration impurity diffusion layers are arranged at a plurality of locations in a direction parallel to the gate electrode; An interlayer insulating film having a formed dot-shaped contact hole, and a drain metal formed on the interlayer insulating film while filling the dot-shaped contact hole in the drain region. Line, and a source region made of a third impurity diffusion layer formed in the semiconductor substrate on the other side of the gate electrode, so that the drain capacitance is reduced, so that high-output operation in a high-frequency band is possible. A semiconductor device can be obtained.
[0060]
In the semiconductor device according to the present invention, the width of the low impurity concentration region in the third impurity diffusion layer is smaller than the width of the first low impurity concentration diffusion layer in the gate length direction. The breakdown voltage is improved.
[0061]
Further, in the semiconductor device according to the present invention, the interval between opposing sides of the dot-shaped second high-concentration impurity diffusion layer and the dot-shaped contact hole is set to 0.02 μm or more and 0.3 μm or less. As a result of further reducing the capacitance, a semiconductor device capable of high-power operation in a high-frequency band can be obtained.
[0062]
Further, in the semiconductor device according to the present invention, a semiconductor substrate, a gate electrode provided on the semiconductor substrate with an insulating film interposed therebetween, and a first gate electrode formed in the semiconductor substrate on one side of the gate electrode. A first impurity diffusion layer having a higher impurity concentration than the first lightly doped impurity diffusion layer provided inside the first lightly doped impurity diffusion layer and the first lightly doped impurity diffusion layer; A drain region having a second high-impurity diffusion layer having a rectangular shape having long sides parallel to the direction; and a rectangular region formed on the semiconductor substrate and on the second rectangular high-concentration impurity diffusion layer. An interlayer insulating film having a rectangular contact hole provided on the inner side of the predetermined interval, and a drain formed on the interlayer insulating film while filling the rectangular contact hole in the drain region. A third impurity diffusion layer formed in the semiconductor substrate on the other side of the gate electrode, and the width of the low impurity concentration region in the third impurity diffusion layer in the gate length direction is the same as that of the third impurity diffusion layer. A source region smaller than the width of the low-concentration impurity diffusion layer and an element isolation insulating film disposed around the source / drain region on the semiconductor substrate, wherein the element isolation insulating film in a gate width direction is provided. And the distance between the opposing ends of the second high-concentration impurity diffusion layer is longer than the distance between the second high-concentration impurity diffusion layer and the opposing ends of the gate electrode in the gate length direction. As a result, the withstand voltage between the source and the drain is improved and the drain capacitance is reduced. As a result, a semiconductor device capable of high-output operation in a high-frequency band is obtained.
[0063]
Further, in the semiconductor device according to the present invention, the interval between the rectangular second high-concentration impurity diffusion layer and each of the opposing sides of the rectangular contact hole is set to 0.02 μm or more and 0.3 μm or less. As a result of further reducing the drain capacitance, a semiconductor device capable of high-output operation in a high-frequency band is obtained.
[0064]
Further, in the semiconductor device according to the present invention, since the third impurity diffusion layer has a high impurity concentration, a semiconductor device capable of high-output operation in a high-frequency band can be obtained.
[0065]
Further, in the semiconductor device according to the present invention, the conductivity type of the first low-concentration impurity diffusion layer, the second high-concentration impurity diffusion layer, and the third impurity diffusion layer are all N-type. A semiconductor device operable in a high frequency band is obtained.
[0066]
In the method of manufacturing a semiconductor device according to the present invention, a step of forming a P-type isolation diffusion layer in an element isolation region located around the source / drain region of a semiconductor substrate by ion implantation of an impurity; Forming an isolation insulating film, forming a P-type impurity diffusion layer below the gate electrode region and a portion extending over the source region by ion implantation of impurities, and forming a gate oxide film on the semiconductor substrate Forming a gate electrode in the gate electrode region on the gate oxide film; forming a first N-type low concentration impurity diffusion layer in the drain region by ion implantation of impurities; Forming a third N-type high-concentration impurity diffusion layer inside the P-type impurity diffusion layer in the source region, and forming an interlayer insulation on the semiconductor substrate. A step of forming a film, and a step of forming a contact hole on a drain region side and a contact hole on a source region side penetrating the interlayer insulating film on the drain region and the source region by a photolithography technique and an insulating film etching technique, A resist film having only a contact hole portion on the drain region side is formed on the interlayer insulating film by photolithography, and the resist film and the interlayer insulating film are used as an ion implantation mask to perform the ion implantation of impurities. Forming a second N-type high-concentration impurity diffusion layer inside the first N-type low-concentration impurity diffusion layer; and forming the second N-type high-concentration impurity diffusion layer on the interlayer insulating film of the drain region while burying the contact hole on the drain region side. Forming a drain metal wiring, wherein The shape of the high-concentration impurity diffusion layer projected on the main surface of the semiconductor substrate is determined by the opening of the contact hole on the drain region side. An operable semiconductor device can be easily manufactured with good reproducibility.
[0067]
Further, in the method for manufacturing a semiconductor device according to the present invention, the distance between the second N-type high-concentration impurity diffusion layer and the opposite end of the contact hole on the drain region side may be 0.02 μm or more and 0.3 μm or less. Therefore, as a result of further reducing the drain capacitance, a semiconductor device capable of high-output operation in a high-frequency band can be easily manufactured with good reproducibility.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment.
FIG. 2 is a sectional view of the semiconductor device according to the first embodiment;
FIG. 3 is a sectional view of the semiconductor device according to the first embodiment;
FIG. 4 is a sectional view of a modification of the semiconductor device of the first embodiment;
FIG. 5 is a sectional view of a modification of the semiconductor device of the first embodiment;
FIG. 6 is a plan view of the semiconductor device according to the second embodiment;
FIG. 7 is a sectional view of a semiconductor device according to a second embodiment;
FIG. 8 is a diagram illustrating a part of a manufacturing process in a method of manufacturing a semiconductor device according to a third embodiment;
FIG. 9 is a diagram illustrating a part of a manufacturing process in a method of manufacturing a semiconductor device according to a third embodiment;
FIG. 10 is a diagram illustrating a part of a manufacturing process in a method of manufacturing a semiconductor device according to a third embodiment;
FIG. 11 is a view showing a part of the manufacturing process in the method for manufacturing a semiconductor device of the third embodiment.
FIG. 12 is a plan view of a conventional semiconductor device.
FIG. 13 is a sectional view of a conventional semiconductor device.
FIG. 14 is a diagram illustrating a part of a manufacturing process in a conventional method of manufacturing a semiconductor device.
FIG. 15 is a view illustrating a part of a manufacturing process in a conventional method of manufacturing a semiconductor device.
FIG. 16 is a view illustrating a part of a manufacturing process in a conventional method of manufacturing a semiconductor device.
FIG. 17 is a view illustrating a part of a manufacturing process in a conventional method of manufacturing a semiconductor device.
FIG. 18 is a view illustrating a part of a manufacturing process in a conventional method of manufacturing a semiconductor device.
FIG. 19 is a plan view of a conventional semiconductor device.
[Explanation of symbols]
Reference Signs List 1 active layer, 2P type source wireless diffusion layer, 3 gate electrode, 6a first aluminum wiring (drain metal wiring) on drain region side, 6b first aluminum wiring on source region side, 8a first aluminum wiring on drain region side 2a aluminum wiring, 8b second aluminum wiring on the source region side, 9a, 9b interlayer insulating film, 11 isolation oxide film (insulating film for element isolation), 12P type silicon substrate, 13P type silicon layer, 14P type Isolation diffusion layer, 31 gate oxide film (insulating film), 41 third N on source region side ⁺ Diffusion layers, 42, 45, 46 Second N on drain region side ⁺ Diffusion layer, 43 P-type impurity diffusion layer, 44 first N ⁻ Diffusion layer, 44a N ⁻ Diffusion layer, 47 resist film, 51 source region side contact hole, 52, 53, 54 drain region side contact hole, 61 plug structure, 71 source region side through hole, 72 drain region side through hole.

Claims (9)

A semiconductor substrate;
A gate electrode provided on the semiconductor substrate via an insulating film,
A first low-concentration impurity diffusion layer formed in the semiconductor substrate on one side of the gate electrode; and an impurity provided inside the first low-concentration impurity diffusion layer and higher than the first low-concentration impurity diffusion layer. A drain region in which a plurality of second high-concentration impurity diffusion layers each having a concentration and projected onto the main surface of the semiconductor substrate having a dot shape are arranged at a plurality of positions in a direction parallel to the gate electrode;
An interlayer insulating film having a dot-shaped contact hole provided on the second high-concentration impurity diffusion layer at a predetermined interval inside each side of the dot shape;
Drain metal wiring formed on the interlayer insulating film while filling the dot-shaped contact hole in the drain region;
A source region including a third impurity diffusion layer formed in the semiconductor substrate on the other side of the gate electrode;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein a width of the low impurity concentration region in the third impurity diffusion layer is smaller than a width of the first low concentration impurity diffusion layer in a gate length direction. 3. The semiconductor according to claim 1, wherein an interval between the opposite side of the dot-shaped second high-concentration impurity diffusion layer and the dot-shaped contact hole is 0.02 μm or more and 0.3 μm or less. 4. apparatus. A semiconductor substrate;
A gate electrode provided on the semiconductor substrate via an insulating film,
A first low-concentration impurity diffusion layer formed in the semiconductor substrate on one side of the gate electrode; and an impurity provided inside the first low-concentration impurity diffusion layer and higher than the first low-concentration impurity diffusion layer. A drain region including a second high-impurity diffusion layer having a concentration and having a rectangular shape formed by long sides parallel to a gate width direction, the surface being projected onto the main surface of the semiconductor substrate;
An interlayer insulating film having a rectangular contact hole formed on the semiconductor substrate and provided on the rectangular second high-concentration impurity diffusion layer at a predetermined distance from the rectangular shape;
A drain metal wiring formed on the interlayer insulating film while filling the rectangular contact hole in the drain region;
A third impurity diffusion layer formed in the semiconductor substrate on the other side of the gate electrode, wherein the width of the low impurity concentration region in the third impurity diffusion layer in the gate length direction is equal to the first low impurity concentration layer; A source region smaller than the width of the impurity diffusion layer;
A device isolation insulating film disposed around the source / drain region on the semiconductor substrate,
The distance between the opposing ends of the isolation insulating film and the second high-concentration impurity diffusion layer in the gate width direction is the distance between the second high-concentration impurity diffusion layer and the gate electrode in the gate length direction. A semiconductor device that is longer than the distance between the ends. 5. The semiconductor device according to claim 4, wherein a distance between the rectangular second high-concentration impurity diffusion layer and each side of the rectangular contact hole facing each other is 0.02 μm or more and 0.3 μm or less. 5. The semiconductor device according to claim 1, wherein said third impurity diffusion layer has a high impurity concentration. 7. The conductivity type of the first low-concentration impurity diffusion layer, the second high-concentration impurity diffusion layer, and the third impurity diffusion layer are all N-type. 2. The semiconductor device according to claim 1. Forming a P-type isolation diffusion layer in an element isolation region located around the source / drain region of the semiconductor substrate by ion implantation of impurities;
Forming an element isolation insulating film in the element isolation region;
Forming a P-type impurity diffusion layer at a portion below the gate electrode region and over the source region by ion implantation of impurities;
Forming a gate oxide film on the semiconductor substrate;
Forming a gate electrode in the gate electrode region on the gate oxide film;
Forming a first N-type low concentration impurity diffusion layer in the drain region by ion implantation of impurities;
Forming a third N-type high-concentration impurity diffusion layer inside the P-type impurity diffusion layer in the source region by ion implantation of impurities;
Forming an interlayer insulating film on the semiconductor substrate;
Drilling a contact hole on the drain region side and a contact hole on the source region side penetrating the interlayer insulating film on the drain region and the source region by photolithography technology and insulating film etching technology,
A resist film having only a contact hole portion on the drain region side is formed on the interlayer insulating film by a photolithography technique, and the resist film and the interlayer insulating film are used as an ion implantation mask to perform the ion implantation of impurities. Forming a second N-type high-concentration impurity diffusion layer inside the first N-type low-concentration impurity diffusion layer;
Forming a drain metal wiring formed on the interlayer insulating film of the drain region while burying the contact hole on the drain region side, in the second N-type high concentration impurity diffusion layer. A method of manufacturing a semiconductor device, wherein a shape projected on a main surface of the semiconductor substrate is determined by an opening of a contact hole on the drain region side. 9. The semiconductor device according to claim 8, wherein the distance between the second N-type high-concentration impurity diffusion layer and the opposite end of the contact hole on the drain region side is 0.02 μm or more and 0.3 μm or less. Manufacturing method.

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