JPH0410473A - Semiconductor device with mis type field-effect transistor - Google Patents

Abstract

PURPOSE:To increase electrostatic breakdown resistance by changing only the ratio of space in the channel width direction of the end section of a drain region and the contact surface of an electrode and the end section of a low-concentration drain region and the end section of a high-concentration drain region to space in the channel length direction in the relationship of both the end section of the drain region and the contact surface and both the end section of the low-concentration drain region and the end section of the high-concentration drain region. CONSTITUTION:Space in the channel width direction of an electrode contact surface formed between a drain region 5 and a drain electrode 7 and the end section of the drain region 5 in the drain region 5 is made larger than that in the channel length direction of an electrode contact surface on at least the channel region side and the end section of the drain region 5. The space is brought to twice or more of space in the channel length direction. When at least the surface side of the high-concentration drain region 51 of the drain region 5 has high breakdown strength type structure formed in a low-concentration drain region 50, space in the channel width direction of the end section of the low-concentration drain region 50 and the end section of the high-concentration drain region 51 is made larger than that in the channel length direction of the end section of the low-concentration drain region 50 and the end section of the high-concentration drain region 51 on at least the channel region side. Space in the channel width direction is brought to sextuple or more of space in the channel length and the surface carrier concentration of the low-concentration drain region 50 is brought to 10<18>atoms.cm<-2> or less at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having an MIS field effect transistor, and in particular to a technique for preventing electrostatic damage in a miniaturized MIS field effect transistor. It is related to.

[Conventional technology]

Currently, M I S (Metal In5ulator)
Sem1conduct.

r) type field effect transistors are used in many semiconductor integrated circuits, but as semiconductor devices become more highly integrated,
There is a demand for miniaturization of IS type field effect transistors, and various efforts have been made to meet this miniaturization.

FIG. 14 shows a plan view of a conventional Mis type field effect transistor. Here, a gate electrode 2 made of polysilicon is formed on a p-type silicon substrate 1 via a gate insulating film (not shown), and using this gate electrode 2 as a mask, donor impurities are introduced into a region 3 by a self-alignment line. A source region 4 and a drain region 5 are formed by diffusion. An insulating film (not shown) covering the upper part of this source region 4
A source electrode 6 is formed on the contact hole 4a, and the source region 4 and the source electrode 6 are connected to the contact hole 4a.

4b... are in conductive contact with each other. Further, the drain region 5 is in conductive contact with the drain electrode 7 through the contact holes 5a, 5b, . . . , and a MISFET is formed with the above structure. Furthermore, this MISFE
A p' type guard ring 8 is formed around the T to make conductive contact with the source electrode 6 through contact holes 8a, 8b, . . . . Also, in this MISFET,
In order to achieve miniaturization of elements, the size of contact holes is also becoming smaller, and in order to suppress the increase in contact resistance associated with this, a large number of contact holes are arranged at equal intervals.

Furthermore, conventionally, in order to improve the drain breakdown voltage of the above-mentioned MISFET, LDD (Lightly Dop
ed[1rain) structure, or GDD (Gra
ded Drain and 5source Diff
FIG. 15 shows a cross-sectional view in the channel length direction, and FIG. 16 shows a cross-sectional view in the channel width direction in the drain region. In this MISFET, the low concentration drain region 50
Since a highly doped drain region 51 is formed inside the gate electrode and a lightly doped drain region 50 is present on the gate electrode side, the depletion layer in this part expands greatly, and the electric field at the drain end is relaxed, increasing the breakdown voltage. Characteristics improve.

[Problem to be solved by the invention]

However, the conventional MrS type field effect transistor described above has the following problems.

In other words, as the dimensions of the entire device become smaller, the depth of the drain diffusion, the thickness of the gate oxide film, and the effective channel width are all reduced, so the current density generated by static electricity becomes relatively smaller. This results in a decrease in the electrostatic breakdown resistance of the device. In particular, since the diffusion depth of the drain region 5 becomes shallower as the surface area of the region decreases, the resistance to forward electrostatic discharge damage and surge damage of the equivalent diode parasitic between the drain region 5 and the substrate 1 decreases. That is, as shown in FIG. 10, the equivalent circuit of the drain part includes drain resistors RD-ia, RD-ib, and R between the source and drain of the MIS field effect transistor.
, -ic, Rtl-id1 diode D-ia, D-i
b, D-ic.

D-id and substrate resistances R5-1a and R5-1b.

It is considered that circuits in which R, -i c and R, -i d (i = 1 to N) are connected in series are arranged in parallel in the ±XY direction on the surface of the drain region. At the end 21 in the channel width direction (for example, i = N in FIG. 10), the curvature of the boundary surface causes a concentration of current due to static electricity, so electrostatic damage is likely to occur from here. However, as mentioned above,
As the diffusion depth of the drain region 5 becomes shallower due to miniaturization of devices, the curvature of the boundary surface of the drain region 5 increases, and as a result, the degree of current concentration at the curved portion increases.

On the other hand, in order to increase the electrostatic breakdown capability of the device, it is necessary to deepen the drain diffusion, increase the area, or build an output protection diode, but all of these things increase the area occupied by the device. This results in a result that is contrary to the demand for integration of semiconductor devices.

Furthermore, when the above-mentioned high-voltage drain structure is adopted, the lightly doped drain region 50 is formed to protrude by a predetermined amount from the heavily doped drain region 51 on the gate electrode 2 side. The end of the lightly doped drain region 50 in the channel width direction of the drain region 5 is formed relatively close to the end of the heavily doped drain region 51, and a highly doped guard ring 8 is formed at this end. Because these are opposed to each other, current due to static electricity is more likely to concentrate at the end of the drain region 5 in the channel width direction than in the drain region 5 of a normal structure, which further increases the electrostatic breakdown resistance of the device. There was also the problem of a decline.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and its object is to avoid concentration of current due to static electricity by changing only the dimensional ratio of the planar structure in the drain part of an MIS field effect transistor, and to The purpose is to increase the electrostatic breakdown resistance of the device without increasing the area occupied by the device.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a semiconductor device having a MIS field effect transistor in which a source region and a drain region are formed on the surface side of a semiconductor layer on both sides of a channel region formed under a gate electrode. The first
In the drain region, the distance in the channel width direction between the electrode contact surface formed between the drain electrode and the end of the drain region is set such that the distance in the channel width direction between the electrode contact surface and the end of the drain region on the channel region side is at least The spacing in the channel length direction is set to be larger than the spacing in the channel length direction. Here, it is desirable that the spacing in the channel width direction is at least twice the spacing in the channel length direction.

In addition, as a second means, a high breakdown voltage type structure is provided in which the drain region includes a low concentration drain region and a high concentration drain region, and at least the surface side of the high concentration drain region is formed within the low concentration drain region. In the case where the spacing in the channel width direction between the end of the lightly doped drain region and the end of the heavily doped drain region is at least equal to the distance between the end of the lightly doped drain region and the end of the heavily doped drain region on the channel region side, The spacing is made larger than the spacing in the channel length direction. Here, it is desirable that the spacing in the channel width direction be at least 6 times the spacing in the channel length direction, and furthermore, the surface carrier concentration of the lightly doped drain region is 10".
It is particularly effective to keep the amount of atoms below -cm-2.

[Effect]

First, according to the first means, in order to form a drain region by making the length in the channel width direction extending from the electrode contact portion longer than the length in the channel length direction, the drain region is formed at the end in the channel width direction. The resistance becomes larger than the drain resistance in the channel length direction. Therefore, when a current generated due to static electricity or the like occurs in the drain junction, conventionally, when a current is generated at the drain junction,
The current that was concentrated in the drain region now flows uniformly over the entire edge around the drain region. As a result, it is possible to suppress the local increase in current density, and it is possible to avoid the occurrence of heat generation due to current, lower resistance, current concentration, and melting due to the positive feedback mechanism of heat generation. Breakage resistance can be improved. Moreover, this improvement in electrostatic breakdown resistance can be achieved without increasing the area occupied by the drain region simply by adjusting the position of the electrode contact surface of the drain region.

Next, according to the second means, the distance in the channel length direction between the end of the lightly doped drain region and the end of the heavily doped drain region on the channel region side is set to a predetermined dimension due to the demand for high breakdown voltage. On the other hand, since we decided to make the gap in the channel width direction at both ends larger than the gap in the channel length direction, the internal resistance in the drain region, which conventionally had a small value in the channel width direction, has been reversed. Therefore, it has a larger value in the channel width direction than in the channel length direction. Therefore, electrostatic damage at the ends of the drain region in the channel width direction can be prevented, so that the electrostatic damage resistance of the device as a whole can be increased. in this case,
When the spacing in the channel width direction is 6 times or more the spacing in the channel length direction, the electrostatic breakdown resistance is significantly improved, and the surface carrier concentration of the lightly doped drain region is increased to 10
In the case of setting it to 13atoII+s -cm-'' or less, it is possible to improve the electrostatic breakdown resistance even more significantly while increasing the breakdown voltage of the element.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a plan view of the first embodiment of the MISFET formed in a semiconductor device, and FIGS. 2 and 3 show lines a-b and c in FIG. -d A cutaway view showing the state of cutting along the cotton. In this MISFET, a p-type silicon substrate 1 with a surface concentration of 2 x 1016 cmI has a thickness of 2
500mm thick through 50mm gate insulating film (not shown)
A gate electrode 2 made of polysilicon is formed,
From above, the surrounding area is a field oxide film 10 with a thickness of 1 μm.
For example, ions such as As are implanted into the region 3 surrounded by the gate electrode 2 using a self-line method using the gate electrode 2 as a mask to form a source region 4 and a drain region 5 with a depth of 0.2 μm and a surface concentration of 1020 cm −2 . has been done. Furthermore, an insulating film (not shown) is formed on the entire surface of these, and a source electrode 6 and a drain electrode 7 are formed on the openings formed on the source region 4 and drain region 5 of this insulating film. It is formed by vapor deposition, etc.

Note that contact holes 8a are provided around these.

A P'-type guard ring 8 having a depth of 0.3 dm and a surface concentration of 10'' cm@-2 is formed on the surface side of the silicon substrate I, in conductive contact with the source electrode 6 through 8b, 8c, . . . .

Here, the distance between the edge on the channel side of the contact surface between the drain region 5 and the drain electrode 7 and the edge on the channel side of the drain region 5 is α, and the distance between those edges in the channel width direction is α. It is formed so that β. In this case, MrSFET was created by changing the arrangement of the contact holes 5a, 5b, 5c, and 5d of the drain region 5 within the range of β/α−0.5 to 2.0, respectively, but in this example, In order to easily change the ratio of β/α without increasing the area occupied by the element, α is kept constant at 2 μm, and β is set at 1 to 4 μm.
It was set so that

FIG. 11 shows the dependence of the electrostatic breakdown resistance of a MOSFET having such a planar arrangement on the ratio of β/α.

Here, normally if the value of β/α is about 2°0, β/α
When the value of α is 1, the electrostatic breakdown resistance is nearly twice as high, and when the value of β/α is 0.5, the electrostatic breakdown resistance is five times or more. This improvement in electrostatic breakdown resistance is due to M
This can be achieved simply by changing the arrangement of contact holes 5a, 5b, 5c, 5d, etc., without increasing the depth or area of drain region 5 of the OSFET.

In this embodiment, in particular, since the edge of the drain region 5 in the channel width direction is opposed to the guard ring 8 to which the source potential is applied, the above-mentioned noticeable problem is prevented by preventing current concentration at the edge. It is considered that the effect is being obtained.

The value of β/α can be applied not only to the MO3FET of the above embodiment but also to MOSFETs having various planar patterns.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG. 4 shows a plan view of the second embodiment, FIGS. 6 to 8 are process sectional views taken along line a-b in FIG. 4, and FIG. 9 is a plan view of the second embodiment. FIG. 3 is a cross-sectional view taken along line c-d of FIG. In this embodiment, the same parts as in the first embodiment are denoted by the same reference numerals, and the explanation thereof will be omitted.

In the second embodiment, the drain region 5 is composed of a lightly doped drain region 50 and a heavily doped drain region 51. The method for forming the drain region 5 is as shown in FIG. 6, using the gate electrode 2 as a mask,
P (phosphorous) is ion-implanted at a dose of "atoms -cm-", and through a heat treatment process, a low concentration drain region 5 with a depth of 1.0 μm and a surface concentration of 2 x 10 "cm-" is formed.
In order to obtain ohmic contact with the electrode, a resist 12 is formed on the gate electrode 2 side on the lightly doped drain region 50 as shown in FIG. As (arsenic) is ion-implanted to obtain a sufficiently high carrier concentration to form a highly doped drain region 51 together with a highly doped source region 41 . After that, heat treatment is performed, and finally, as shown in FIG.
．． form 7.

This drain region 5 is formed so that the offset amount β in the channel width direction shown in FIG. 9 is larger than the offset amount α in the channel length direction of the lightly doped drain region 50 shown in FIG. This structure is obtained by forming a highly doped drain region 51 through a resist pattern 10 shown in FIG. In this example, α is constant at 2 μm, and β is 2 to 16 μm.
A plurality of high voltage MISFETs were created with different voltages within the range of m. FIG. 12 shows the dependence of the electrostatic breakdown capacity of MISFET on β/α. Here, around the value of β/α being 6, the electrostatic damage resistance increases rapidly, and the electrostatic damage resistance is more than 10 times that when the value of β/α is 1.0. is obtained.

This remarkable increase in electrostatic breakdown resistance does not increase the depth of the drain region 5 of the MISFET or the area occupied by the device (
, and can be achieved by changing only the ratio of β and α, and its practical value can be found in that it can be achieved by changing only the pattern dimensions when forming the heavily doped drain region 51.

Furthermore, FIG. 13 shows the dependence of the electrostatic breakdown resistance on the surface concentration of the lightly doped drain region 50 when α=2 μm and 1β=6 μm. As shown in this figure, the surface concentration of the low concentration drain region 50 is 5×10”ato
ms-cm-" or less, the electrostatic breakdown strength decreases rapidly. However, the carrier concentration in the low concentration drain region 50 is the most important factor that determines the breakdown voltage of the device, and it is important to increase the breakdown voltage. In order to achieve this, the carrier concentration in the low concentration drain region must be lowered to some extent. Therefore, according to this example, the above remarkable effect can be achieved in the conventional high voltage withstand voltage element with extremely low electrostatic breakdown resistance. Therefore, both an increase in the breakdown voltage of the element and an improvement in the electrostatic breakdown breakdown voltage can be achieved at the same time.

〔Effect of the invention〕

As explained above, the present invention provides a method for determining the spacing in the channel width direction and the channel length in the relationship between the end of the drain region and the electrode contact surface, or the end of the lightly doped drain region and the end of the heavily doped drain region. By changing only the ratio of the directional spacing, MISFE can be realized without increasing the element area.
The electrostatic breakdown resistance of T can be increased.

Furthermore, in a high-voltage MISFET, when the impurity concentration of the lightly doped drain region is reduced in order to increase the breakdown voltage of the device, the electrostatic breakdown resistance is extremely improved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the structure of a MISFET according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line a-b in FIG. 1. FIG. 3 is a cross-sectional view taken along line c-d in FIG. 1. FIG. 4 is a plan view showing the structure of a MISFET according to a second embodiment of the present invention. FIG. 5 is a plan view showing a resist pattern when forming a heavily doped drain region in the second embodiment. 6 to 8 are process sectional views of a portion cut along line a-b in FIG. 4. FIG. 9 is a cross-sectional view showing a state cut along line c-d in FIG. 4. FIG. FIG. 10 is an equivalent circuit diagram of the drain section of a conventional MISFET. FIG. 11 is a graph showing the relationship between the electrostatic breakdown resistance and the value of β/α in the first embodiment. FIG. 12 is a graph showing the relationship between the electrostatic breakdown strength and the value of β/α in the second embodiment. FIG. 13 is a graph showing the relationship between the electrostatic breakdown resistance and the surface concentration of the lightly doped drain region in the second embodiment. FIG. 14 is a plan view showing the configuration of a conventional MISFET. FIGS. 15 and 16 are longitudinal sectional views showing the structure of a conventional high voltage MISFET. [Explanation of symbols] 1...Silicon substrate 2...Gate electrode 3...Diffusion region 4...Source regions 4a, 4b, 4c, 4d・s7 tact hole 5...Drain region 5a, 5b, 5c 6...Source electrode 7...Drain electrode 8...Guard ring 8a, 8b, 8c, 8d・':179')5
0...Low concentration drain region 51...High concentration drain region. 5d...Contact hole to hole

Claims (5)

[Claims] (1) In a semiconductor device having a MIS field effect transistor in which a source region and a drain region are formed on the surface side of a semiconductor layer on both sides of a channel region formed under a gate electrode, the drain region is located between the drain electrode and the source region. an electrode contact surface on the side of the channel region, and the distance between the electrode contact surface and the end of the drain region in the channel width direction is at least the width of the channel width between the electrode contact surface and the end of the drain region on the channel region side. A semiconductor device having a MIS type field effect transistor characterized in that the distance is larger than the distance in the longitudinal direction. (2) A semiconductor device having an MIS type field effect transistor according to claim 1, wherein the interval in the channel width direction is twice or more the interval in the channel length direction. A semiconductor device having an effect transistor. (3) MIS type field effect in which a source region and a drain region are formed on the surface side of the semiconductor layer on both sides of a channel region formed under the gate electrode, and the drain region includes a low concentration drain region and a high concentration drain region In a semiconductor device having a transistor, at least a surface side of the heavily doped drain region is formed within the lightly doped drain region, and a channel width between an end of the lightly doped drain region and an end of the heavily doped drain region is A semiconductor having an MIS type field effect transistor, wherein the distance in the direction is larger than the distance in the channel length direction between an end of the lightly doped drain region and an end of the heavily doped drain region on the side of the channel region. Device. (4) A semiconductor device having an MIS type field effect transistor according to claim 3, wherein the interval in the channel width direction is six times or more the interval in the channel length direction. A semiconductor device having an effect transistor. (5) In the semiconductor device having the MIS field effect transistor according to claim 3 or 4, the surface carrier concentration of the low concentration drain region is 10^1^3a.
M characterized by being less than toms cm^-^2
A semiconductor device having an IS type field effect transistor.