KR100228375B1 - Transistor with separated current paths for high field area at the ending part of gate and for the current between source and drain of it - Google Patents
Transistor with separated current paths for high field area at the ending part of gate and for the current between source and drain of it Download PDFInfo
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- KR100228375B1 KR100228375B1 KR1019950043612A KR19950043612A KR100228375B1 KR 100228375 B1 KR100228375 B1 KR 100228375B1 KR 1019950043612 A KR1019950043612 A KR 1019950043612A KR 19950043612 A KR19950043612 A KR 19950043612A KR 100228375 B1 KR100228375 B1 KR 100228375B1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 5
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- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000000593 degrading effect Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
본 발명은 트랜지스터의 하이 필드영역에 고전류 패스가 존재하여 소자의 신뢰성을 저하시키는 것을 방지하기 위하여 액티브 레이아웃으로 하이 필드영역과 고전류패스를 분리시키는 구조를 구비한 트랜지스터에 관한 것으로, 액티브영역과 필드영역으로 이루어지는 반도체기판상의 상기 액티브영역 및 필드영역의 소정부분에 걸쳐 형성된 게이트와 상기 게이트 양단의 액티브영역에 형성된 고농도 불순물접합영역으로 구성된 트랜지스터에 있어서, 채널부분의 액티브영역과 필드영역이 만나는 부분에 형성되는 높은 전류밀도 영역과 상기 게이트 엣지에서 하이 필드를 형성하는 영역이 소정간격만큼 분리된 것을 특징으로 하는 트랜지스터구조를 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor having a structure in which a high field path and a high current path are separated in an active layout in order to prevent high current paths in a high field area of a transistor from degrading reliability of the device. A transistor comprising a gate formed over a predetermined portion of an active region and a field region on a semiconductor substrate, and a high concentration impurity junction region formed in an active region at both ends of the gate, wherein the transistor is formed at a portion where the active region and the field region of the channel portion meet. A high current density region and a region forming a high field at the gate edge are separated by a predetermined interval.
Description
제1도는 종래의 트랜지스터 구조도.1 is a conventional transistor structure diagram.
제2도는 본 발명의 일실시예에 의한 트랜지스터 구조도.2 is a transistor structure diagram according to an embodiment of the present invention.
제3도는 본 발명의 다른 실시예에 의한 트랜지스터 구조도.3 is a transistor structure diagram according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 액티브영역 12 : 게이트11 active area 12 gate
14 : 필드영역 30 : 포켓 이온주입영역14: field region 30: pocket ion implantation region
본 발명은 반도체 소자에 관한 것으로, 특히 트랜지스터의 고전계(high electric field)영역에 높은 밀도의 전류 경로가 존재함에 따른 소자의 신뢰성 저하를 방지하기 위하여, 액티브 레이아웃의 변형으로 게이트 단부의 고전계 영역과 소오스 드레인 간의 전류경로를 분리시킬 수 있는 트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular to a high electric field region at the gate end due to a modification of the active layout, in order to prevent the deterioration of the reliability of the device due to the presence of a high density current path in the high electric field region of the transistor. And a transistor capable of separating a current path between a source and a source drain.
확산영역(액티브영역)은 n+소오스/드레인 이온주입을 했을 경우 필드산화막 엣지 밑으로 측면확산되는 이온에 의해 게이트 밑의 확산영역보다 넓어지게 된다. 이 액티브 영역 크기의 차이는 소오스에서 드레인으로의 (특히 게이트 엣지에서) 전류흐름에 영향을 미치게 되는데 본 발명은 이를 완화시켜주는 방법을 제시하고 있다.The diffusion region (active region) becomes wider than the diffusion region under the gate due to ions diffused laterally under the field oxide film edge when n + source / drain ion implantation is performed. This difference in active region size affects the current flow from the source to the drain (especially at the gate edge), and the present invention provides a way to mitigate this.
본 발명은 특히 정전방전소자(ESD)나 고전력소자와 같이 매우 큰 전류용량을 요구하는 회로에 사용가능하다.The present invention is particularly applicable to circuits requiring very large current capacity, such as electrostatic discharge devices (ESD) and high power devices.
첨부도면 제1(a)도는 종래의 트랜지스터 배치도이고, 제1(b)도는 상기 제1도 (a)의 a-a'선을 따른 단면도이다. 제1(a)도에 도시한 형태의 액티브 영역(확산영역)(1)을 갖는 종래의 트랜지스터의 구조는, 게이트 전극(2) 형성 후 n+소오스/드레인 형성을 위한 이온주입 공정에서 필드산화막 단부(edge) 밑으로 이온이 측면 확산되어 액티브 영역의 확장부분(5)이 만들어진다. 즉, 소오스/드레인 부분의 액티브 영역이 게이트 밑의 액티브 영역보다 넓어진다.1 (a) is a conventional arrangement of transistors, and FIG. 1 (b) is a cross-sectional view taken along line a-a 'in FIG. 1 (a). The structure of a conventional transistor having an active region (diffusion region) 1 of the type shown in FIG. 1 (a) is a field oxide film in an ion implantation process for n + source / drain formation after the gate electrode 2 is formed. Ions are laterally diffused below the edges to create an extension 5 of the active region. In other words, the active region of the source / drain portion is wider than the active region under the gate.
이와 같이, 게이트 부분의 액티브 영역 크기가 소오스/드레인 부분의 액티브 영역 크기 보다 좁아짐에 따라 제1(b)도에 도시한 바와 같이 소오스와 드레일 사이의 전류 밀도는 게이트 중심부 보다 게이트 단부(edge)에서 상대적으로 높아진다.Thus, as the size of the active region of the gate portion becomes narrower than the size of the active region of the source / drain portion, as shown in FIG. 1 (b), the current density between the source and the rail is smaller than the gate center. Relatively high at.
즉, 제1(c)도에 도시된 바와 같이 종래의 트랜지스터 구조에서는, 필드영역 엣지부의 소오스 및 드레인의 n+영역에서 형성된 전류(다)가 게이트 엣지의 하이필드영역 아래에서 상당힌 높은 전류밀도(라)를 갖게되어, 전기장과 전류밀도의 곱에 비례하는 주울열로 인한 히팅(heating)에 의하여 소자의 페일을 유발하게 된다.That is, as shown in FIG. 1 (c), in the conventional transistor structure, a high current density in which the current formed in the n + region of the source and drain of the field region edge portion is significant under the high field region of the gate edge. (D), causing the device to fail due to heating due to Joule heat proportional to the product of the electric field and the current density.
이때, 가장 취약한 부분은 (가)와 (나) 부분이다.At this time, the most vulnerable parts are (a) and (b) parts.
이러한 문제점을 해결하기 위한 본 발명의 목적은, 게이트 엣지쪽의 액티브영역을 확장하여 고전계가 발생되는 영역과 소오스/드레인 간의 전류경로를 분리하여 소자의 페일을 방지할 수 있는 트랜지스터를 제공하는데 있다.An object of the present invention to solve this problem is to provide a transistor that can prevent the device from failing by extending the active region toward the gate edge to separate the current path between the region where the high field is generated and the source / drain.
상기 목적을 달성하기 위한 본 발명은, 반도체 기판에 형성된 액티브 영역과 필드 영역, 상기 액티브 영역과 상기 필드 영역 상에 중첩된 게이트, 상기 게이트의 일측 및 타측의 상기 액티브 영역에 각각 형성된 고농도 불순물 영역으로 이루어지는 소오스 및 드레인을 구비하는 트랜지스터에 있어서, 상기 소오스와 드레인 사이의 전류경로에 직교하는 방향으로 상기 게이트 하부의 상기 액티브 영역의 폭이 상기 소오스 및 드레인의 폭보다 커서, 상기 게이트 하부의 상기 액티브 영역 단부에 형성되는 고전계 영역과 상기 소오스와 드레인 사이의 전류경로를 분리시키는 트랜지스터를 제공한다.The present invention provides a high concentration impurity region formed in an active region and a field region formed in a semiconductor substrate, a gate overlapping the active region and the field region, and formed in the active region on one side and the other side of the gate, respectively. A transistor having a source and a drain, the width of the active region under the gate being greater than the width of the source and the drain in a direction orthogonal to the current path between the source and the drain, wherein the active region under the gate A transistor is provided which separates a high electric field region formed at an end and a current path between the source and the drain.
또한, 상기 목적을 달성하기 위한 본 발명은, 반도체 기판에 형성된 액티브 영역과 필드 영역, 상기 액티브 영역과 상기 필드 영역 상에 중첩된 게이트, 상기 게이트의 일측 및 타측의 상기 액티브 영역에 각각 형성된 고농도 불순물 영역으로 이루어지는 소오스 및 드레인을 구비하는 트랜지스터에 있어서, 상기 소오스와, 상기 드레인 사이의 전류경로 방향의 상기 액티브 영역과 상기 필드 영역의 경계에 포켓이온주입 영역을 구비하여, 상기 게이트 하부의 상기 액티브 영역 단부에 형성되는 고전계 영역과 상기 소오스와 드레인 사이의 전류경로를 분리시키는 트랜지스터를 제공한다.In addition, the present invention for achieving the above object, high concentration impurity formed in the active region and the field region formed on the semiconductor substrate, the gate overlapped on the active region and the field region, the active region on one side and the other side of the gate, respectively A transistor having a source and a drain comprising a region, comprising: a pocket ion implantation region at a boundary between the source and the drain in the current path direction between the source and the drain region; A transistor is provided which separates a high electric field region formed at an end and a current path between the source and the drain.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
본 발명은 상술한 종래 기술의 문제점을 해결하기 위하여 추가되는 공정없이 제2(a)도에 도시된 바와 같이 게이트 하부의 액티브 영역(11)을 소오스 드레인 간의 전류경로에 직교하는 방향으로 확장시킨 구조를 갖는 트랜지스터 구조를 제공한다.The present invention has a structure in which the active region 11 under the gate is extended in a direction orthogonal to the current path between the source drains, as shown in FIG. 2 (a) without additional steps to solve the above-described problems of the prior art. It provides a transistor structure having a.
본 발명은 제2(a)도 및 제2(b)도에 도시된 바와 같이 게이트 엣지측의 액티브영역(11)을 소정넓이 만큼 늘림으로써 높은 전류밀도를 형성하는 영역(b)과 게이트 엣지부에서 하이 필드를 형성하는 영역(a)을 분리시킨다. 이에 따라 소자의 페일을 방지할 수 있게 된다. 제2(c)도는 제2(b)도의 구조의 전류 흐름을 도시한 것으로, 종래와 같이 게이트 단부에 이웃한 액티브 영역 엣지로 전류가 집중되어 흐르지 않게 된다. 따라서 고전계 영역과 높은 전류밀도 영역이 분리됨으로써 전계와 전류 밀도의 곱에 의하여 발생하는 히팅 효과에 의한 소자의 페일을 막을 수 있다.According to the present invention, as shown in FIGS. 2 (a) and 2 (b), the region b and the gate edge portion forming a high current density by increasing the active region 11 on the gate edge side by a predetermined width are shown. Separates the region (a) forming the high field. As a result, it is possible to prevent the device from failing. FIG. 2 (c) shows the current flow in the structure of FIG. 2 (b), and as in the prior art, the current is not concentrated at the edge of the active region adjacent to the gate end. Therefore, the high electric field region and the high current density region are separated to prevent the device from failing due to the heating effect caused by the product of the electric field and the current density.
한편, 본 발명의 다른 실시예로서, 전류 경로와 고전계 영역을 분리시키기 위하여 제3도에 도시된 바와 같이 액티브 영역을 상기한 실시예에서와 같이 늘리지 않고, 필드영역 엣지와 n+영역의 엣지가 만나는 영역에 p+이온을 주입하여 포켓(pocket)영역(30)을 형성한다.On the other hand, according to another embodiment of the present invention, a current path and a high electric field, without the active region, as shown the area in FIG. 3 in order to remove not increase as in the embodiment described above, the edge of the field area edge and n + region P + ions are implanted into the region where is formed to form a pocket region 30.
상기 본 발명의 일실시예 및 다른 실시예에 의한 트랜지스터구조는 별도의 추가되는 공정없이 액티브영역의 소정부분을 늘리기 위한 마스크를 이용하는 것 이외에는 통상적인 트랜지스터 제조공정과 동일한 공정에 의해 형성할 수 있다.The transistor structure according to one embodiment of the present invention and the other embodiment can be formed by the same process as the conventional transistor manufacturing process except for using a mask for increasing a predetermined portion of the active region without any additional process.
상술한 바와 같이 본 발명에 의하면, 고전계 영역과 고전류 밀도영역을 분리할 수 있으므로 각각의 영역에서의 전류 밀도의 곱에 의하여 발생하는 열효과에 의한 소자의 페일을 막을 수 있게 되어 반도체소자의 신뢰성을 향상시킬 수 있으며, 고성능의 칩 제조가 가능하게 된다.As described above, according to the present invention, since the high electric field region and the high current density region can be separated, the failing of the device due to the thermal effect generated by the product of the current density in each region can be prevented, thereby ensuring the reliability of the semiconductor device. It is possible to improve the performance, and it is possible to manufacture a high-performance chip.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043612A KR100228375B1 (en) | 1995-11-24 | 1995-11-24 | Transistor with separated current paths for high field area at the ending part of gate and for the current between source and drain of it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043612A KR100228375B1 (en) | 1995-11-24 | 1995-11-24 | Transistor with separated current paths for high field area at the ending part of gate and for the current between source and drain of it |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970030888A KR970030888A (en) | 1997-06-26 |
| KR100228375B1 true KR100228375B1 (en) | 1999-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950043612A KR100228375B1 (en) | 1995-11-24 | 1995-11-24 | Transistor with separated current paths for high field area at the ending part of gate and for the current between source and drain of it |
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| Country | Link |
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| KR (1) | KR100228375B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7307320B2 (en) | 2005-11-07 | 2007-12-11 | Samsung Electronics Co., Ltd. | Differential mechanical stress-producing regions for integrated circuit field effect transistors |
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1995
- 1995-11-24 KR KR1019950043612A patent/KR100228375B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7307320B2 (en) | 2005-11-07 | 2007-12-11 | Samsung Electronics Co., Ltd. | Differential mechanical stress-producing regions for integrated circuit field effect transistors |
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| Publication number | Publication date |
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| KR970030888A (en) | 1997-06-26 |
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