JPS6292340A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a flat insulating film by forming a wiring layer in three layer structure, in which a polycrystalline silicon layer having a blocking effect to anodizing treatment is interposed between upper and lower metallic layers as an intermediate layer, and anodizing-treating the metallic wiring layer as the upper layer. CONSTITUTION:An insulating film 12, a first metallic layer 13 consisting of aluminum, a polycrystalline silicon layer 14 and a second metallic layer 15 composed of aluminum are formed onto a semiconductor substrate 11. A photo- resist film 16 is shaped onto the layer 15. The layers 15 in regions not coated with the film 16 are converted into aluminum oxide layers through anodizing, using the film 16 as a mask. The aluminum oxide layers 17A, 17B are removed through etching. The films 14, 13 are removed through etching, employing the film 16 as the mask. The film 16 is got rid of, thus acquiring wiring layers 30.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for forming a metal wiring layer that is effective for flattening the surface of an insulating film covering all interconnection layers. Regarding the method.

[Conventional technology]
: Conventionally, the total wiring area of a semiconductor device is shown in Figure 2 (
As shown in a), a metal film is formed on the insulating film 22 on the surface of the semiconductor substrate 21, and then a predetermined area of the metal film is covered with a photoresist film and processed using an anisotropic dry etching method.
Remove photoresist film and form metal wiring 1: Layer 23
The surfaces of A and 23B were covered with an insulating film 27. Aluminum is often used for the metal film because it is superior to other metals in terms of electrical contact with silicon, adhesion with silicon oxide films, and cost as a material.

[Problem that the invention seeks to solve]

In the conventional semiconductor device manufacturing method described above, after forming a metal wiring layer using an anisotropic etching method, the surface is coated using a chemical vapor deposition method (hereinafter referred to as CVD method) or a deposition method using plasma excitation. The insulating film tends to grow thickly at the corners of the upper end of the metal wiring layer. This phenomenon occurs in film formation methods that mainly involve chemical reactions, such as the CVD method and plasma excitation method.
This occurs because the amount of reactive groups supplied at the corners of the upper surface ends of the metal wiring layers 23A, 23B is larger than at other locations.

As shown in FIG. 2(h), the film is formed about three times more easily at the corners 28 of the -F plane of the metal wiring layer 23A than at the corners 29 of the bottom surface. Insulating film 27 formed in this way
However, it is possible to flatten the film by performing heat treatment at a high temperature of about 950° to 1000°C, but especially when aluminum is used as the gold maple film, the melting point is as low as 650"O. However, such high-temperature heat treatment cannot be performed. Therefore, without using a special planarization technique, it is inevitable that the surface of the insulating film 27 will have a very uneven and bald shape.

Therefore, when the insulating film 27 is used as an interlayer insulating film and a second JWI metal wiring layer is further formed thereon, there is a drawback that the second metal wiring layer is disconnected.

Furthermore, when the insulating film 27 is used as a bathymetal carbon film for a device, when the device is sealed with resin, the stress from the resin acts on the device through the unevenness of the insulating film 27, and the gold bullion wiring layer 23A, 23B destruction may also occur.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes forming a three-layer film in which a first metal layer, a polycrystalline silicon layer, and a second metal layer are sequentially laminated on an insulating film formed on one main surface of a semiconductor substrate. a step of forming a photoresist film of a predetermined shape to cover the second metal layer;
After converting the entire second metal layer that does not contain C into a metal oxide layer by anodizing, the end portion of the second metal layer under the photoresist film 7B is converted into a metal oxide layer by further anodizing for a predetermined period of time. a step of converting the second metal layer into an oxide layer to make the cross section of the second metal layer approximately trapezoidal; a step of selectively etching and removing the metal oxide layer; The method is characterized in that it includes a step of sequentially etching and removing one metal layer to form a wiring layer made of three layers.

〔Example〕

FIGS. 1(a) to 1(f) are longitudinal cross-sectional views in the order of steps of an embodiment of the present invention.

First, as shown in FIG. 1(a), an insulating film 12 is formed on a semiconductor substrate [11], a first metal layer 13 made of aluminum, for example, is formed, and then a polycrystalline silicon layer 14 is formed. It is formed on the first metal layer 13.

Subsequently, a second gold layer 15 made of aluminum is formed on the surface of the polycrystalline silicon layer 140.

Next, as shown in FIG.
7 photoresist film 16 is formed in a predetermined region on top of 5.

Next, as shown in FIG. 1(C), a predetermined anodic oxidation treatment is performed using the photoresist film 16 as a mask, so that the twenty The gold stripe layer 15 is completely converted into an aluminum oxide layer.

Thereafter, by further adding anodizing treatment, the aluminum oxide layers 17A and 17B are allowed to penetrate into a part of the area under the area covered by the photoresist film 16. This creates a second layer that does not change into an aluminum oxide layer because it is covered by the photoresist film [6].
A gold bullion wiring layer 15A is formed. As mentioned above, the anodizing process changes the aluminum oxide layer to the polycrystalline silicon layer 1.
Since the edge that has reached the surface of 4 is further added, aluminum oxide progresses isotropically from the side of the second metal wiring layer 15A in the area masked by the photoresist film 16, so that the cross section is almost trapezoidal.

On the other hand, the anodic oxidation reaction is blocked by the polycrystalline silicon film 14, remains in the second metal layer, and does not proceed to the first metal layer.

Next, as shown in FIG. 1(d), the aluminum 6-oxide layers 17A and 17B are selectively etched away using a solution containing ethylene glycol and hydrochloric acid as main components.

Subsequently, as shown in FIG. 1(e), the polycrystalline silicon film 14 and the first metal layer 3 are sequentially etched using an anisotropic etching method using the photoresist film 16 as a mask. Remove. In this step, the first
The metal wiring layer 13A1 and the polycrystalline silicon wiring layer 14A
is formed by an anisotropic etching method, so its dimensions are
A predetermined shape defined by the photoresist film 16 is completed.

Finally, by removing the photoresist film 16,
First metal wiring layer 13A1 polycrystalline silicon wiring layer 14A1 second gold striped wiring layer 15A as shown in Figure 1
A wiring layer 30 having a layered structure is obtained.

〔Effect of the invention〕

As explained above, the present invention has a three-layer wiring structure in which a polycrystalline silicon layer is interposed as an intermediate layer between upper and lower metal layers and has a blocking effect against anodic oxidation, and further,
The upper metal wiring layer is subjected to a predetermined anodic oxidation treatment, and the formed metal oxide film is etched away to make the upper metal wiring layer have a trapezoidal cross section. This has the effect of flattening the surface of the membrane.

[Brief explanation of drawings]

FIG. 1 (al to ge) is a vertical cross-sectional view of an embodiment of the present invention in the order of steps, FIG. 2 (a) is a cross-sectional view of a conventional metal wiring area, and FIG.
FIG. 2B is a simplified diagram illustrating the thickness of an insulating film in a conventional metal wiring region. 11.21... Semiconductor substrate, 12.22...
...Insulating film, 13...First metal layer, 13A
10th metal interconnection layer, 14A polycrystalline silicon layer, 14A polycrystalline silicon interconnection layer, 15 second metal layer , 15A...
・Second metal wiring layer, 16...Photoresist film, 17A, 1713...Gold striped oxide film layer, 23
A, 23B...metal wiring layer, 27...
Insulating film, 28...Corner of upper part of metal wiring layer, 29.
... Corner of the bottom of all wiring layers, 30 ... Wiring layer. Figure 2 Figure 1 Figure t-1

Claims (1)

[Claims] forming a three-layer film in which a first metal layer, a polycrystalline silicon layer, and a second metal layer are sequentially laminated on an insulating film formed on one main surface of a semiconductor substrate; forming a photoresist film of a predetermined shape to cover the second metal layer, and after converting all of the second metal layer not covered with the photoresist film into a metal oxide layer by anodizing treatment, further anodizing treatment for a predetermined period of time. a step of converting the end portion of the second metal layer directly under the photoresist film into a metal oxide layer to make the cross section of the second metal layer approximately trapezoidal; and a step of selectively etching away the metal oxide layer. Then, using the photoresist film as a mask, the polycrystalline silicon layer and the first
1. A method of manufacturing a semiconductor device, comprising the step of sequentially etching away metal layers to form a wiring layer made of three layers.