JPS6278853A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6278853A
JPS6278853A JP21836985A JP21836985A JPS6278853A JP S6278853 A JPS6278853 A JP S6278853A JP 21836985 A JP21836985 A JP 21836985A JP 21836985 A JP21836985 A JP 21836985A JP S6278853 A JPS6278853 A JP S6278853A
Authority
JP
Japan
Prior art keywords
film
oxide film
silicon oxide
silicon
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21836985A
Other languages
Japanese (ja)
Inventor
Shozo Nishimoto
西本 昭三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21836985A priority Critical patent/JPS6278853A/en
Publication of JPS6278853A publication Critical patent/JPS6278853A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To leave the silicon oxide film having a film thickness enough for dielectric isolation on the side surface of the polysilicon film by a method wherein the etching to be performed on the silicon oxide film in the region other than the prescribed region is carried out in two stages, anisotropic etching and isotropic etching. CONSTITUTION:A three layer film consisting of a phosphorus-doped polysilicon film 3, a silicon oxide film 4 formed by thermal-oxidizing the film 3 and a silicon nitride film 5 is provided on one main surface of a silicon substrate 1 having a two layer insulating film. A silicon oxide film 11 is deposited on the whole surface by a vapor-phase growth method. The whole surface if thermal-oxidized to eliminate the acute angle part at the same time as the film thickness of the oxide film 11 on the side surface of the silicon film 3 is increased. Most of the oxide film 11 is removed by an anisotropic plasma etching method. The residual is removed with anisotropic wet etching liquid. The nitride film 5 and a silicon nitride film 10, both exposed on the surface, and a silicon oxide film 2 are etched way in order. A silicon oxide film 8 and a polysilicon film 9 are formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に導電層間の
絶縁膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an insulating film between conductive layers.

〔従来の技術〕[Conventional technology]

従来、導成j−間に絶縁膜を形成するには、下層の導′
dlLI−表面に化学気相成長(chemical v
apordeposition、以下CVDという)法
によシ絶縁膜を形成し、その上に上層の導電層を形成し
ていた。
Conventionally, in order to form an insulating film between conductors, the underlying conductor
dlLI - chemical vapor deposition on the surface
An insulating film is formed by an apor deposition (hereinafter referred to as CVD) method, and an upper conductive layer is formed thereon.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の絶縁膜の形成方法は、膜厚及び膜質の、
均一な絶縁膜を形成することができる点で優れているも
のの、所定形状に加工した下層導電層の縁辺部や角部が
加工形成されたときのままに、まるみがなく鋭角で残さ
れるため、その部分に電界が集中し、絶縁膜が破壊され
やすい。また、絶縁膜が下層と上層の導電層間だけでな
く、下地、の絶縁膜と上層の導電層間にも介在するため
、たとえば、二層多結晶シリコンを用いた半導体記憶装
置で上層の導電層を絶縁ゲート型電界効果トランジスタ
のゲート電極として用いる場合、写真食刻法によシ絶縁
膜の一部をエツチング除去する必要があり、工程が複雑
となシ目合せ余裕が必要となるために素子の微細化に適
さない欠点がある。
The conventional method for forming an insulating film described above depends on the film thickness and film quality.
Although it is superior in that it can form a uniform insulating film, the edges and corners of the lower conductive layer that have been processed into a predetermined shape remain as they were when they were formed, with no roundness and sharp angles. The electric field concentrates in that area, and the insulating film is likely to be destroyed. Furthermore, since an insulating film is interposed not only between the lower and upper conductive layers, but also between the underlying insulating film and the upper conductive layer, for example, in a semiconductor memory device using two-layer polycrystalline silicon, the upper conductive layer When used as the gate electrode of an insulated gate field effect transistor, it is necessary to remove a portion of the insulating film by photolithography, which complicates the process and requires margin for alignment, making the device There are drawbacks that make it unsuitable for miniaturization.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、絶縁膜を有する半導
体基板の一生面の所定領域に第1の導電膜と第1の酸化
膜及び酸化阻止膜とからなる3層膜を形成する工程と、
全面に第2の酸化膜を形成する工程と、前記#c1の導
電膜と前記第2の酸化膜の界面に前記第1の導電膜の酸
化膜からなる第3の酸化膜を形成する工程と、異方性エ
ツチング法により前記8g2の酸化膜を前記第1の酸化
膜及び第3の酸化膜の側面にのみ残す工程と、前記第2
の酸化膜及び第3の酸化膜を介して前記第1の導電膜と
電気的に絶縁する第2の導電膜を形成する工程を含むこ
とを特徴とする。
A method for manufacturing a semiconductor device according to the present invention includes a step of forming a three-layer film including a first conductive film, a first oxide film, and an oxidation prevention film in a predetermined region of the whole surface of a semiconductor substrate having an insulating film;
a step of forming a second oxide film on the entire surface; and a step of forming a third oxide film made of the oxide film of the first conductive film at the interface between the #c1 conductive film and the second oxide film. , leaving the 8g2 oxide film only on the side surfaces of the first oxide film and the third oxide film by an anisotropic etching method;
The method is characterized by including a step of forming a second conductive film that is electrically insulated from the first conductive film through an oxide film and a third oxide film.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図ないし第6図は本発明の一実施例の工程順縦断面
図である。シリコン酸化膜2上にシリコン窒化M10が
積層された2層絶縁膜を有するシリコン基板1の一生面
に、リンドープしたポリシリコン膜3、その熱酸化によ
って形成したシリコン酸化膜4及びシリコン窒化膜5か
らなる3層膜を設け、この3層膜を所定形状に加工する
。次いで、全面に気相成長法によシシリコン酸化膜11
を堆積しく第1図)、全面を熱酸化してポリシリコン膜
3の側面のシリコン酸化膜厚を増すと共に鋭角部をなく
す(第2図)。このとき、ポリシリコンM3のないシリ
コン基板表面部分及びポリシリコン膜3の上面は、シリ
コン窒化膜lOで覆われているので酸化はされない。次
に、異方性のプラズマエツチング法によシシリコン酸化
膜11の大部分を除去した後(第3図)、等方性のウェ
ットエツチング液によシ残シを除去する(第4図)。次
に、表面に請出したシリコン窒化膜5.10&びシリコ
ン酸化膜2を順次エツチング除去する(第5図)。その
後、シリコン酸化膜8、ポリシリコン膜9を形成する(
第6図)。
1 to 6 are vertical cross-sectional views in the order of steps of an embodiment of the present invention. A phosphorus-doped polysilicon film 3, a silicon oxide film 4 and a silicon nitride film 5 formed by thermal oxidation of the silicon substrate 1 have a two-layer insulating film in which silicon nitride M10 is laminated on a silicon oxide film 2. A three-layer film is provided, and this three-layer film is processed into a predetermined shape. Next, a silicon oxide film 11 is formed on the entire surface by vapor phase growth.
(FIG. 1), the entire surface is thermally oxidized to increase the thickness of the silicon oxide film on the side surfaces of the polysilicon film 3 and to eliminate the sharp corners (FIG. 2). At this time, the silicon substrate surface portion without the polysilicon M3 and the upper surface of the polysilicon film 3 are not oxidized because they are covered with the silicon nitride film IO. Next, most of the silicon oxide film 11 is removed by an anisotropic plasma etching method (FIG. 3), and then the remaining residue is removed by an isotropic wet etching solution (FIG. 4). Next, the silicon nitride film 5.10 and the silicon oxide film 2 exposed on the surface are sequentially removed by etching (FIG. 5). After that, a silicon oxide film 8 and a polysilicon film 9 are formed (
Figure 6).

本実施例は、気相成長法で形成したシリコン酸化膜11
を用い、所定領域以外のシリコン酸化膜11をエツチン
グ除去するために異方性エツチングと等方性エツチング
との2段階で行うことにより、シリコン酸化膜11被着
後ポリシリコン膜3をさほど熱酸化せずとも、ポリシリ
コン膜3の側面に絶縁分離に十分なだけのシリコン酸化
、喚11を残すことが出来る。
In this example, a silicon oxide film 11 formed by a vapor phase growth method is used.
By performing two steps of anisotropic etching and isotropic etching to remove the silicon oxide film 11 in areas other than a predetermined area, the polysilicon film 3 is thermally oxidized to a moderate degree after the silicon oxide film 11 is deposited. Even if this is not done, silicon oxide 11 can be left on the side surface of the polysilicon film 3 in an amount sufficient for insulation isolation.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、下層導電膜パターン側面
に接し基板全面を覆う絶#*膜を形成し、下層導電膜パ
ターン側面と、絶縁膜の接触する界面に下層導電膜の薄
い酸化膜を形成し、この酸化膜と異方性エツチング法で
残した厚い前記絶縁膜を介して下層導電膜と電気的に絶
縁した上層導電膜を形成する。これによシ、絶縁性に優
れ、素子の平坦化及び微細化に適した絶縁膜を形成する
ことができる。
As explained above, the present invention forms an insulating film that is in contact with the side surface of the lower conductive film pattern and covers the entire surface of the substrate, and forms a thin oxide film of the lower conductive film at the interface where the side surface of the lower conductive film pattern contacts the insulating film. Then, an upper conductive film is formed which is electrically insulated from the lower conductive film via this oxide film and the thick insulating film left by anisotropic etching. This makes it possible to form an insulating film that has excellent insulation properties and is suitable for planarization and miniaturization of elements.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第6図は本発明の一実施例の工程順縦断面
図である。 1・・・・・・シリコン基板、2,4,8.11・・・
・・・シリコン酸化膜、3.9・・・・・・ポリシリコ
ン膜、5.10・・・・・・シリコン窒化膜。 !・ ν ・ 代理人 弁理士  内 原   ヨ(:(−一
1 to 6 are vertical cross-sectional views in the order of steps of an embodiment of the present invention. 1... Silicon substrate, 2, 4, 8.11...
... silicon oxide film, 3.9 ... polysilicon film, 5.10 ... silicon nitride film. !・ ν ・ Agent Patent attorney Yo Uchihara (:(-1)

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜を有する半導体基板の一主面の所定領域に第1の
導電膜と第1の酸化膜及び酸化阻止膜とからなる3層膜
を形成する工程と、全面に第2の酸化膜を形成する工程
と、前記第1の導電膜と前記第2の酸化膜の界面に前記
第1の導電膜の酸化膜からなる第3の酸化膜を形成する
工程と、異方性エッチング法により前記第2の酸化膜を
前記第1の酸化膜及び第3の酸化膜の側面にのみ残す工
程と、前記第2の酸化膜及び第3の酸化膜を介して前記
第1の導電膜と電気的に絶縁する第2の導電膜を形成す
る工程を含むことを特徴とする半導体装置の製造方法。
A step of forming a three-layer film consisting of a first conductive film, a first oxide film, and an oxidation prevention film in a predetermined region of one main surface of a semiconductor substrate having an insulating film, and forming a second oxide film on the entire surface. forming a third oxide film made of an oxide film of the first conductive film at the interface between the first conductive film and the second oxide film; a step of leaving the No. 2 oxide film only on the side surfaces of the first oxide film and the third oxide film; A method for manufacturing a semiconductor device, comprising the step of forming an insulating second conductive film.
JP21836985A 1985-09-30 1985-09-30 Manufacture of semiconductor device Pending JPS6278853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21836985A JPS6278853A (en) 1985-09-30 1985-09-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21836985A JPS6278853A (en) 1985-09-30 1985-09-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6278853A true JPS6278853A (en) 1987-04-11

Family

ID=16718813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21836985A Pending JPS6278853A (en) 1985-09-30 1985-09-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6278853A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203323A (en) * 1989-12-29 1991-09-05 Samsung Electron Co Ltd Manufacture of semiconductor device
US5384278A (en) * 1992-11-16 1995-01-24 United Technologies Corporation Tight control of resistor valves in a SRAM process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203323A (en) * 1989-12-29 1991-09-05 Samsung Electron Co Ltd Manufacture of semiconductor device
US5384278A (en) * 1992-11-16 1995-01-24 United Technologies Corporation Tight control of resistor valves in a SRAM process

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