JPH0864557A - Manufacture of mesa type semiconductor element - Google Patents
Manufacture of mesa type semiconductor elementInfo
- Publication number
- JPH0864557A JPH0864557A JP20184494A JP20184494A JPH0864557A JP H0864557 A JPH0864557 A JP H0864557A JP 20184494 A JP20184494 A JP 20184494A JP 20184494 A JP20184494 A JP 20184494A JP H0864557 A JPH0864557 A JP H0864557A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- protective film
- type semiconductor
- film
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、メサ型のダイオード、
トランジスタ等の半導体素子の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a mesa type diode,
The present invention relates to a method for manufacturing a semiconductor element such as a transistor.
【０００２】[0002]
【従来の技術】従来、この種のダイオード素子は例えば
次のような方法で製造される。まず、図３（１）に示す
ように、Ｐ型の半導体領域１１がその上に形成されてい
るＮ型の半導体基板１２の上面に、図３（２）及び
（２）´に示すように、Ｐ型半導体領域１１とＮ型半導
体基板１２のＰＮ接合部１３を各素子単位に分離するた
めの溝部１４をエッチング等の手段により縦横に形成す
る。次いで図３（３）に示すように、溝部１４にガラス
１５を注入、その後約７００゜Ｃの温度で焼成し、図３
（４）に示すように、溝部１４に露出するＰＮ接合部１
３を覆うようにガラス保護膜１５ａを形成する。なお、
このガラス保護膜１５ａは、接合部１３に水その他の不
要な導電物質が付着しダイオード素子にリーク電流が発
生するのを防止する役目を果たす。このガラス保護膜１
５ａを形成した後、最後に溝部１４の底部中央部１４ａ
をガラス保護膜１５ａの上からダイサー等により切断
し、図３（５）に示すように個々のダイオード素子１６
に分離する。2. Description of the Related Art Conventionally, this type of diode element is manufactured, for example, by the following method. First, as shown in FIG. 3A, on the upper surface of the N-type semiconductor substrate 12 on which the P-type semiconductor region 11 is formed, as shown in FIGS. A groove portion 14 for separating the P-type semiconductor region 11 and the PN junction portion 13 of the N-type semiconductor substrate 12 into respective element units is formed vertically and horizontally by means such as etching. Then, as shown in FIG. 3 (3), glass 15 is injected into the groove portion 14 and then baked at a temperature of about 700 ° C.
As shown in (4), the PN junction portion 1 exposed in the groove portion 14
The glass protective film 15 a is formed so as to cover the film 3. In addition,
The glass protective film 15a plays a role of preventing a leak current from being generated in the diode element due to the adhesion of unnecessary conductive material such as water to the joint portion 13. This glass protective film 1
5a is formed, and finally, the bottom center portion 14a of the groove 14 is formed.
Is cut from above the glass protective film 15a with a dicer or the like, and as shown in FIG.
To separate.
【発明が解決しようとする課題】しかしながら、上記従
来例においては次のような問題点があった。すなわち、
溝部１４の底部中央部をダイサー等で切断する際、ガラ
ス保護膜１５ａの上から切断することになるので、ガラ
ス保護膜１５ａに応力が生じ、時としてガラス保護膜１
５ａに欠け、割れ、剥れ等が生じる。その結果、水その
他の不要な導電物質が接合部１３に付着し、ダイオード
素子１６にリーク電流が発生してしまうという問題点が
あった。本発明は、これらの問題を解消できるようにし
たメサ型半導体素子の製造方法を提供することを技術的
課題とするものである。However, the above-mentioned conventional example has the following problems. That is,
When the center of the bottom of the groove 14 is cut with a dicer or the like, it is cut from above the glass protective film 15a, so stress is generated in the glass protective film 15a, and sometimes the glass protective film 1
5a is chipped, cracked, or peeled off. As a result, there is a problem that unnecessary conductive material such as water adheres to the joint portion 13 and a leak current is generated in the diode element 16. An object of the present invention is to provide a method for manufacturing a mesa type semiconductor device which can solve these problems.
【課題を解決するための手段】上記技術的課題を解決す
るため、本願発明では次の技術的手段を講じている。す
なわち、本願の請求項１に記載したダイオード素子の製
造方法は、性質の異なる他の半導体領域がその上に形成
されている半導体基板の上面に、前記半導体基板と前記
性質の異なる他の半導体領域の接合部を各素子単位に分
離するための縦横の分離溝を形成する工程と、前記半導
体基板の上面にガラスを塗布、焼成して保護膜を形成す
る工程と、前記分離溝の底部中央部及び前記縦横の分離
溝によって分離された前記各単位素子上面の領域を除く
前記保護膜上にレジスト膜を塗布、形成する工程と、前
記レジスト膜が塗布、形成されていない領域の前記保護
膜を除去する工程と、前記レジスト膜を除去する工程
と、前記溝部底部中央部を切断することにより個別の半
導体素子に分離する工程、とからなることを特徴として
いる。また、本願請求項２に記載したメサ型半導体素子
の製造方法は、請求項１記載のメサ型半導体素子の製造
方法において、前記半導体基板の上面及び下面の両面に
前記ガラスを塗布、焼成して保護膜を形成することを特
徴としている。In order to solve the above technical problems, the present invention takes the following technical measures. That is, in the method for manufacturing a diode element according to claim 1 of the present application, another semiconductor region having a different property from the semiconductor substrate is formed on the upper surface of the semiconductor substrate on which another semiconductor region having a different property is formed. Forming a vertical and horizontal separation groove for separating the junction part into each element unit, a step of applying glass on the upper surface of the semiconductor substrate and baking to form a protective film, and a bottom central portion of the separation groove. And a step of applying and forming a resist film on the protective film excluding the area of the upper surface of each unit element separated by the vertical and horizontal separation grooves, and the protective film in the area where the resist film is not applied and formed. It is characterized in that it comprises a step of removing, a step of removing the resist film, and a step of cutting the center portion of the bottom of the groove portion into individual semiconductor elements. The method for manufacturing a mesa-type semiconductor element according to claim 2 of the present application is the method for manufacturing a mesa-type semiconductor element according to claim 1, wherein the glass is applied and baked on both upper and lower surfaces of the semiconductor substrate. The feature is that a protective film is formed.
【作用】以上のような手段を講じることにより、請求項
１記載の発明によれば、溝部底部中央部上の保護膜を除
去した後に切断工程を行うので、切断時、保護膜に応力
による欠け、割れ、剥れ等が生じることはない。また、
請求項２記載の発明によれば、半導体基板の両面にガラ
スを塗布して焼成するので、焼成時、該両面のガラスが
略等しく収縮する。その結果、収縮による応力を上面、
下面で均等にする、または均等に近づけることができ
る。According to the invention described in claim 1, the cutting step is performed after removing the protective film on the center of the bottom of the groove by taking the above-mentioned means. No cracking or peeling occurs. Also,
According to the second aspect of the present invention, the glass is applied to both surfaces of the semiconductor substrate and fired, so that the glass on both sides shrinks substantially equally during firing. As a result, the stress due to contraction is
The bottom surface can be even or close to even.
【本発明の効果】従って、本発明によれば、保護膜に欠
け、割れ、剥れが生じず、リーク電流の発生しない信頼
性の高いメサ型半導体素子を提供することができる。ま
た、請求項２記載の発明によれば、焼成工程中にガラス
に生じる収縮による応力によって基板が反ったり割れた
りするのを防止することができる。As described above, according to the present invention, it is possible to provide a highly reliable mesa type semiconductor element in which the protective film is not chipped, cracked or peeled off and no leak current is generated. Further, according to the second aspect of the present invention, it is possible to prevent the substrate from warping or cracking due to the stress due to the contraction of the glass during the firing step.
【実施例】以下、本発明の実施例を図１を参照して説明
する。まず、図１（１）に示すように、Ｐ型の半導体領
域１がその上に形成されているＮ型の半導体基板２の上
面に、図１（２）及び（２）´に示すように、Ｐ型半導
体領域１とＮ型半導体基板２の接合部３を各単位素子５
に分離するための溝部４をエッチング等の手段により縦
横に形成する。次いで半導体基板２の上面にガラスペー
スト６を塗布し、その後約７００゜Ｃの温度で焼成して
ガラス保護膜６ａを形成する（図１（３）、（４）参
照）。本実施例においてガラスペースト６は、できるだ
け溝部４以外の部分を薄くして塗布するのが好ましい。
このようにすることにより、焼成時のガラスの収縮によ
る半導体基板の反りを軽減することができる。また、半
導体基板の厚みを比較的厚くしておくことによっても同
様の効果を得られる。次に、図１（５）に示すように、
溝部４の底部中央部４ａ及び、各単位素子５の上面５ａ
の領域を除くガラス保護膜６ａ上にレジスト膜７を塗
布、形成する。この後、図１（６）に示すように、まず
前記半導体基板をフッ硝酸溶液中に浸しレジスト膜７が
塗布されていない箇所のガラス保護膜を除去した後、次
いで図１（７）に示すように、硫酸溶液中に前記半導体
基板を浸してレジスト膜７を除去する。そして図１
（８）に示すように、溝部４の底部中央部４ａの中心を
ダイサーによりダイシングし、個々のダイオード素子８
に分離する。上記実施例において、ガラス保護膜を溝部
４にのみ形成し、その後溝部４の底部中央部４ａのガラ
ス保護膜を選択的に除去してもよく、このようにすれば
焼成時の半導体基板の反りをほぼ解消することができ
る。また、図２は本発明の別の実施例を示す。図２
（１）及び（２）に示すように、Ｐ型の半導体領域１が
その上に形成されているＮ型の半導体基板２の上面に、
Ｐ型半導体領域１とＮ型半導体基板２の接合部３を各素
子単位５に分離するための溝部４をエッチング等の手段
により縦横に形成する。次いで図２（３）（４）に示す
ように、半導体基板２の上面及び下面にガラスペースト
６を塗布し、その後約７００゜Ｃの温度で焼成してガラ
ス保護膜６ａ、６ｂを形成する。次に、図２（５）に示
すように、溝部４の底部中央部４ａ及び、各単位素子５
の上面５ａ上の領域を除くガラス保護膜６ａ上にレジス
ト膜７を塗布、形成する。この後、図２（６）に示すよ
うに、まず前記半導体基板をフッ硝酸溶液中に浸しレジ
スト膜７が塗布されていない箇所のガラス保護膜６ａ及
び半導体基板裏面の６ｂを除去した後、次いで図２
（７）に示すように、硫酸溶液中に前記半導体基板を浸
してレジスト膜７を除去する。そして、図２（８）に示
すように、溝部４の底部中央部４ａの中心をダイサーに
よりダイシングし、個々のダイオード素子に分離する。
本実施例によれば、ガラス保護膜を形成する際に、半導
体基板の両面にガラスを塗布した後、焼成するので、上
面のガラスと下面のガラスの収縮による応力は略等しく
なり、半導体基板に反りが生じる、あるいは反りが生じ
て割れるということを確実に防止できる。従って、半導
体基板の厚みを薄くすることが可能で、ガラスペースト
６の塗布、厚み等の制御に特別注意を払う必要をなくす
ことができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. First, as shown in FIG. 1A, on the upper surface of an N-type semiconductor substrate 2 on which a P-type semiconductor region 1 is formed, as shown in FIGS. , The junction 3 between the P-type semiconductor region 1 and the N-type semiconductor substrate 2 is connected to each unit element 5
The groove portion 4 for separating into two is formed vertically and horizontally by means such as etching. Next, the glass paste 6 is applied to the upper surface of the semiconductor substrate 2 and then baked at a temperature of about 700 ° C. to form the glass protective film 6a (see FIGS. 1 (3) and 1 (4)). In this embodiment, it is preferable that the glass paste 6 is applied as thinly as possible except the groove portion 4.
By doing so, the warp of the semiconductor substrate due to the shrinkage of the glass during firing can be reduced. The same effect can be obtained by making the semiconductor substrate relatively thick. Next, as shown in FIG. 1 (5),
The central portion 4a of the bottom of the groove 4 and the upper surface 5a of each unit element 5
A resist film 7 is applied and formed on the glass protective film 6a excluding the area (1). Thereafter, as shown in FIG. 1 (6), first, the semiconductor substrate is dipped in a hydrofluoric nitric acid solution to remove the glass protective film at a portion where the resist film 7 is not applied, and then shown in FIG. 1 (7). Thus, the semiconductor substrate is dipped in a sulfuric acid solution to remove the resist film 7. And FIG.
As shown in (8), the center of the bottom central portion 4a of the groove portion 4 is diced by a dicer to obtain individual diode elements 8
To separate. In the above embodiment, the glass protective film may be formed only in the groove portion 4 and then the glass protective film in the bottom central portion 4a of the groove portion 4 may be selectively removed. Can be almost eliminated. 2 shows another embodiment of the present invention. Figure 2
As shown in (1) and (2), on the upper surface of the N-type semiconductor substrate 2 on which the P-type semiconductor region 1 is formed,
Grooves 4 for separating the junction 3 between the P-type semiconductor region 1 and the N-type semiconductor substrate 2 into each element unit 5 are formed vertically and horizontally by means such as etching. Next, as shown in FIGS. 2 (3) and (4), the glass paste 6 is applied to the upper and lower surfaces of the semiconductor substrate 2 and then baked at a temperature of about 700 ° C. to form the glass protective films 6a and 6b. Next, as shown in FIG. 2 (5), the bottom central portion 4 a of the groove portion 4 and each unit element 5
A resist film 7 is applied and formed on the glass protective film 6a except the region on the upper surface 5a. After that, as shown in FIG. 2 (6), first, the semiconductor substrate is dipped in a hydrofluoric nitric acid solution to remove the glass protective film 6a and the rear surface of the semiconductor substrate 6b where the resist film 7 is not applied. Figure 2
As shown in (7), the resist film 7 is removed by immersing the semiconductor substrate in a sulfuric acid solution. Then, as shown in FIG. 2 (8), the center of the bottom central portion 4a of the groove portion 4 is diced by a dicer to separate into individual diode elements.
According to this example, when the glass protective film is formed, the glass is applied to both surfaces of the semiconductor substrate and then baked, so that the stress due to the contraction of the glass on the upper surface and the glass on the lower surface become substantially equal to each other. It is possible to reliably prevent the occurrence of warpage or the occurrence of warpage and cracking. Therefore, the thickness of the semiconductor substrate can be reduced, and it is possible to eliminate the need to pay special attention to the application of the glass paste 6, the control of the thickness, and the like.
【図１】本発明の実施例の方法を説明する工程図であっ
て、（１） は、Ｐ型の半導体領域がその上に形成され
ているＮ型半導体基板の断面図、（２） は、上面に縦
横の溝部が形成された半導体基板の断面図、（２）´
は、上面に縦横の溝部が形成された半導体基板の平面
図、（３） は、上面にガラスペーストが塗布された半
導体基板の断面図、（４） は、上面にガラスペースト
を塗布した後、焼成してガラス保護膜を形成した半導体
基板の断面図、（５） は、ガラス保護膜上にレジスト
膜が形成された半導体基板の断面図、（６） は、ガラ
ス保護膜を選択的に除去した半導体基板の断面図、
（７） は、レジスト膜が除去された半導体基板の断面
図、（８） は、個々に分離されたダイオード素子の断
面図、である。1A and 1B are process diagrams illustrating a method of an embodiment of the present invention, (1) is a cross-sectional view of an N-type semiconductor substrate on which a P-type semiconductor region is formed, and (2) is And (2) 'is a cross-sectional view of a semiconductor substrate having vertical and horizontal grooves formed on its upper surface.
Is a plan view of the semiconductor substrate having vertical and horizontal grooves formed on the upper surface, (3) is a cross-sectional view of the semiconductor substrate having the upper surface coated with the glass paste, and (4) is a sectional view of the semiconductor substrate having the upper surface coated with the glass paste. A cross-sectional view of a semiconductor substrate having a glass protective film formed by baking, (5) is a cross-sectional view of a semiconductor substrate having a resist film formed on the glass protective film, and (6) is a glass protective film being selectively removed. Sectional view of the completed semiconductor substrate,
(7) is a cross-sectional view of the semiconductor substrate from which the resist film has been removed, and (8) is a cross-sectional view of the diode elements that are individually separated.
【図２】本発明の別の実施例を示す工程図であって、
（１） は、Ｐ型の半導体領域がその上に形成されてい
るＮ型半導体基板の断面図、（２） は、上面に縦横の
溝部が形成された半導体基板の断面図、（３） は、上
面及び裏面にガラスペーストが塗布された半導体基板の
断面図、（４） は、上面及び裏面にガラスペーストを
塗布した後、焼成してガラス保護膜を形成した半導体基
板の断面図、（５） は、上面のガラス保護膜上にレジ
スト膜が形成された半導体基板の断面図、（６） は、
ガラス保護膜を選択的に除去した半導体基板の断面図、
（７） は、レジスト膜が除去された半導体基板の断面
図、（８） は、個々に分離されたダイオード素子の断
面図、である。FIG. 2 is a process chart showing another embodiment of the present invention,
(1) is a cross-sectional view of an N-type semiconductor substrate having a P-type semiconductor region formed thereon, (2) is a cross-sectional view of a semiconductor substrate having vertical and horizontal grooves formed on its upper surface, (3) is , (4) is a cross-sectional view of a semiconductor substrate having a top surface and a back surface coated with a glass paste, and (4) is a cross-sectional view of a semiconductor substrate having a glass protective film formed by baking the glass paste after coating the top surface and the back surface. ) Is a sectional view of a semiconductor substrate in which a resist film is formed on the glass protective film on the upper surface, and (6) is
A cross-sectional view of a semiconductor substrate from which a glass protective film is selectively removed,
(7) is a cross-sectional view of the semiconductor substrate from which the resist film has been removed, and (8) is a cross-sectional view of the diode elements that are individually separated.
【図３】従来例を示す工程図であって、（１） は、Ｐ
型の半導体領域がその上に形成されているＮ型半導体基
板の断面図、（２） は、上面に縦横の溝部が形成され
た半導体基板の断面図、（２）′は、上面に縦横の溝部
が形成された半導体基板の平面図、（３） は、溝部に
ガラスペーストが塗布された半導体基板の断面図、
（４） は、溝部にガラスペーストを塗布した後、焼成
してガラス保護膜を形成した半導体基板の断面図、
（５） は、個々に分離されたダイオード素子の断面
図、である。FIG. 3 is a process diagram showing a conventional example, in which (1) is P
Cross-sectional view of an N-type semiconductor substrate having a semiconductor region of type formed thereon, (2) is a cross-sectional view of a semiconductor substrate having vertical and horizontal grooves formed on the upper surface, and (2) 'is vertical and horizontal on the upper surface. A plan view of the semiconductor substrate in which the groove is formed, (3) is a cross-sectional view of the semiconductor substrate in which the glass paste is applied to the groove,
(4) is a cross-sectional view of a semiconductor substrate in which a glass protective film is formed by applying a glass paste to the groove and then baking it.
(5) is a cross-sectional view of the diode elements that are individually separated.
１ Ｐ型の半導体領域 ２ Ｎ型の半導体基板 ３ ＰＮ接合部 ４ 溝部 ５ 各単位素子領域 ６ ガラスペースト ６ａ ガラス保護膜 ７ レジスト膜 1 P-type semiconductor region 2 N-type semiconductor substrate 3 PN junction part 4 Groove part 5 Each unit element region 6 Glass paste 6a Glass protective film 7 Resist film
Claims (2)
成されている半導体基板の上面に、前記半導体基板と前
記性質の異なる他の半導体領域の接合部を各素子単位に
分離するための縦横の分離溝を形成する工程と、 前記半導体基板上面にガラスを塗布、焼成して保護膜を
形成する工程と、 前記分離溝の底部中央部及び前記縦横の分離溝によって
分離された前記各単位素子上面の領域を除く前記保護膜
上にレジスト膜を塗布、形成する工程と、 前記レジスト膜が塗布、形成されていない領域の前記保
護膜を除去する工程と、 前記レジスト膜を除去する工程と、 前記溝部底部中央部を切断することにより個別の半導体
素子に分離する工程、とからなるメサ型半導体素子の製
造方法。1. A device for separating a junction between the semiconductor substrate and another semiconductor region having different properties on an upper surface of a semiconductor substrate on which another semiconductor region having different properties is formed for each element unit. A step of forming vertical and horizontal separation grooves, a step of applying a glass to the upper surface of the semiconductor substrate and forming a protective film by baking, and each unit separated by the bottom center part of the separation groove and the vertical and horizontal separation grooves A step of applying and forming a resist film on the protective film except the region of the element upper surface, a step of applying the resist film and removing the protective film in an area where it is not formed, and a step of removing the resist film And a step of separating the individual semiconductor elements by cutting the central portion of the groove bottom portion, and a method of manufacturing a mesa type semiconductor element.
法において、前記半導体基板の上面及び下面の両面に前
記ガラスを塗布、焼成して前記保護膜を形成することを
特徴とするメサ型半導体素子の製造方法。2. The mesa-type semiconductor element manufacturing method according to claim 1, wherein the glass is applied and baked on both upper and lower surfaces of the semiconductor substrate to form the protective film. Manufacturing method of semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20184494A JPH0864557A (en) | 1994-08-26 | 1994-08-26 | Manufacture of mesa type semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20184494A JPH0864557A (en) | 1994-08-26 | 1994-08-26 | Manufacture of mesa type semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864557A true JPH0864557A (en) | 1996-03-08 |
Family
ID=16447833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20184494A Pending JPH0864557A (en) | 1994-08-26 | 1994-08-26 | Manufacture of mesa type semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864557A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000059050A1 (en) * | 1999-03-31 | 2000-10-05 | Seiko Epson Corporation | Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device |
| JP2001044141A (en) * | 1999-07-30 | 2001-02-16 | Nippon Sheet Glass Co Ltd | Method for cutting semiconductor substrate |
| CN100465708C (en) * | 2005-06-30 | 2009-03-04 | 乐金显示有限公司 | Liquid crystal display device and fabrication method thereof |
| CN110328211A (en) * | 2019-06-19 | 2019-10-15 | 东莞高伟光学电子有限公司 | It is a kind of for separating the separation method and chemical reagent of nonmetallic sensor |
-
1994
- 1994-08-26 JP JP20184494A patent/JPH0864557A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000059050A1 (en) * | 1999-03-31 | 2000-10-05 | Seiko Epson Corporation | Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device |
| EP1093169A1 (en) * | 1999-03-31 | 2001-04-18 | Seiko Epson Corporation | Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device |
| EP1093169A4 (en) * | 1999-03-31 | 2002-11-20 | Seiko Epson Corp | Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device |
| US6573157B1 (en) | 1999-03-31 | 2003-06-03 | Seiko Epson Corporation | Method of manufacturing semiconductor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device |
| US6794746B2 (en) | 1999-03-31 | 2004-09-21 | Seiko Epson Corporation | Method of manufacturing semiconductor device, semiconductor device, narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device |
| JP2001044141A (en) * | 1999-07-30 | 2001-02-16 | Nippon Sheet Glass Co Ltd | Method for cutting semiconductor substrate |
| JP4581158B2 (en) * | 1999-07-30 | 2010-11-17 | 富士ゼロックス株式会社 | Semiconductor substrate cutting method |
| CN100465708C (en) * | 2005-06-30 | 2009-03-04 | 乐金显示有限公司 | Liquid crystal display device and fabrication method thereof |
| US8390775B2 (en) | 2005-06-30 | 2013-03-05 | Lg Display Co., Ltd. | Liquid crystal display device with protection film at connection of TCP and therminal and fabrication method thereof |
| CN110328211A (en) * | 2019-06-19 | 2019-10-15 | 东莞高伟光学电子有限公司 | It is a kind of for separating the separation method and chemical reagent of nonmetallic sensor |
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