JPS6221239A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To secure the separation of chip by a method wherein, after the cross part of the scribed line recess with the plated base metal film which spread over into the above-mentioned recessed parts from the cross parts are removed, a plated-layer is provided on the plated base metal film. CONSTITUTION:The element forming surface of a wafer 12 is adhered on a substrate 11, such as a glass substrate, using a bonding agent 13, such as a wax, and scribed line recesses 14 and a recess 15 for heat sink formation are formed. Then a Ti film and an Au film are formed in order on the whole surface of the wafer 12 and a plated base metal (Ti/Au) film 18a is constituted. Then parts of the film 18a which are regions 23 (parts of the Ti/Au film, which are removed) each including the cross part 22 of each recess 14 and part of the film 18a which spreads over into the recess 14 from the cross part 22 are removed. After that, a plated-layer 20 is formed on the film 18a and the substrate is made in a plated heat sink constitution. According to this method, as the base parts of the regions 23 from which the film 18a is removed are the bonding agent 13, the plated-layer 20 is not adhered thereon. As a result, the separation of chip can be securely executed.

Description

[Detailed Description of the Invention] [Summary] Plated heat sink structure
This method prevents gold plating from adhering to unnecessary parts when plating, for example, gold for a heat sink in the process of manufacturing a semiconductor chip with an atsink structure (hereinafter referred to as PHS structure).

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for reliably obtaining individual chips after all steps are completed in the process of obtaining individual chips by etching a wafer. It is.

[Conventional technology]

The PHS structure refers to, for example, a structure in which a heat sink for dissipating heat is formed in the shape of a plate on the back surface of a compound semiconductor chip. Conventionally, after wafer processing is completed and before the wafer is cut into individual chips, a metal with good thermal conductivity such as gold is plated on the back side of the wafer, and then a dicer is used. The wafer was then mechanically cut into individual chips using a wafer.

However, in order to prevent the mechanical impact of a dicer from being applied to the wafer, cutting of the wafer tends to be done chemically, that is, by etching.

This process will be explained with reference to FIG. 3.
As shown in FIG. 1, a wafer 12 is attached onto a substrate, for example, a glass substrate 11, using an adhesive (for example, wax) 13 for bonding. At this time, the thickness of the wafer 12 is 400 mm.
The surface on which the element is formed is adhered to the wax 13. Therefore, the upper surface of the wafer 12 in the figure is actually the back surface of the wafer, that is, the surface on which no elements are formed.

Next, the back side of the wafer is etched away, making the wafer 20 to 30.17 m thick (3rd step).
Figure (b)). The reason for making the wafer so thin is to make it easier to dissipate heat, that is, to improve thermal efficiency.

Next, scribe lines for cutting and analyzing the wafer into solid chips and recesses for forming a heat sink for dissipating heat are formed. Referring to FIG. 3(e), which is a partially enlarged view, 14 is a recess that will become a scribe line, and 15 is a recess for a heat sink. An electrode 16 is formed to release the heat generated by the heated element. Note that the heat sink recess 15 is generally provided in the part of the chip that generates the most heat.

Next, a titanium (Ti) film 17 is first formed on the entire back surface of the wafer.
Next, gold (Au) F1a is formed, and the plating base film (Ti/Au film) 18a for plating is shown in FIG.
Form as shown. This Ti/Au film 18a is formed by continuous vapor deposition.

Next, a resist 19 is partially embedded in the scribe line recess 14 and gold plating is performed, whereby a plating layer for a heat sink, that is, a gold plating layer 20 is formed on the portion excluding the resist (FIG. 3(d)).

The wafer is then removed from the glass substrate and separated into individual chips along the scribe line recesses.

[Problem that the invention seeks to solve]

Resist 1 is applied to the scribe line recess 14 using the method described above.
When filling 9, the thickness of the resist is unstable in the area shown by the dotted line in the plan view of Figure 4, and in some cases gold plating grows on it as shown by the sandy area in Figure 3. It may become slightly thinner. On the other hand, gold plating also grows on the edges of the scribe line recesses, as shown by the sand, and the chips 21a and 21b are stuck together due to the gold plating, requiring special labor to separate the chips 21a and 21b. There is a problem that the chip may be damaged (note that FIG. 3(d) is a cross-sectional view taken along the line ■-■ in FIG. 4).

The present invention was created in view of these points, and the PH
An object of the present invention is to provide a method in which chips can be reliably separated from each other when manufacturing chips having five structures.

[Means for solving problems]

FIG. 1 is a plan view of an embodiment of the invention, which is similar to the plan view of FIG.

In FIG. 1, the intersecting portions 22 (the intersecting portions are indicated by dotted lines in the figure) of the scribe line recesses 14 intersect with each other in most of the intersecting portions and in the portions 23 that enter the respective scribe line recesses from the intersecting portions. Metal film i.e. T
i/ Aul! l! 18a is removed by etching, and therefore, when plating the metal gap layer (gold plating layer) 20 for the heat sink, no gold plating is deposited on the portion 23, and the chips 21a, 21b, ... are gold plated. - Chip 21a because there is no connection due to luck.

The separation of 21b, . . . is ensured.

[Effect]

Since the base of the etched portion 23 of the Ti/Au film 18a is the wax 13, no gold plating is deposited thereon, and the gold plating is spread between adjacent chips as shown in FIG. Since there is no adhesion or connection, the chips can be separated reliably.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

When carrying out the method of the present invention, the conventional method described with reference to FIG. 3(d) is the same.

After completing the steps up to FIG. 3 (dl), the entire Ti/Au film 18a of the portion 23 shown in the plan view of FIG. 1 is removed.

The portion 23 is located at the intersection 22 of the scribe line recess 14 (
occupies most of the area (the area surrounded by the dotted line in Figure 1),
In addition, a portion thereof is set to have a wide enough extent to enter into the scribe line recess 14. For this purpose, the position where the intersection part 22 is rotated about 45 degrees around the center is the part 23.
All you have to do is make it look like this. By extending the portion 23 into the scribe line recess as described above, the bonding of the deposited gold plating as described with reference to FIG. 4 is completely prevented.

To remove the entire Ti/Au film 18a of the portion 23,
A resist is applied to the entire surface of the wafer, and the portion 23 shown in FIG.
A window is opened and the exposed Ti/Au film 18a is etched with a chikuni strip (Au and ) of IP.

FIG. 2 is a cross-sectional view taken along line nn in FIG.
is shown exposed. Ti film Au1i 18a
When gold plating is performed after removing the gold plating layer 20, the gold plating layer 20 is deposited as shown by the dotted line in FIG. 2, but is not deposited on the portion 23 at all. Therefore, for example, by etching the Ti film Au1PJ 18a in the scribe line recess 14 of the wafer, the chips 21a, 21b, . . . can be easily and reliably separated without damaging the chips.

In the above-mentioned method, although resist coating has been done in the conventional example, a step of patterning the resist film as described with reference to FIG. 1 is added. However, in the conventional example, the above-described patterning of the resist can be performed more easily than the trouble of separating chips connected to each other by deposited gold plating.

Note that the shape of the portion 23 is not limited to the example described above, and may be any shape as long as it prevents the deposited gold plating from connecting as described with reference to FIG. 4.

〔Effect of the invention〕

As described above, according to the present invention, when producing chips with a PHS structure, the chips can be separated easily, reliably, and without damaging the chips, which is highly effective in improving manufacturing yield. It is.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line nn in FIG. 1, and FIG. 3 (al
or di is a cross-sectional view showing a conventional process, and FIG. 4 is a plan view of a portion where the scribe line recesses of the wafer in FIG. 3 intersect, showing problems in the conventional example. 1 to 4, 11 is a glass substrate, 12 is a wafer, 13 is wax, 14 is a scribe line recess, 15 is a heat sink forming recess, 16 is an electrode, 17 is a Ti film, 18 is an Au film, 18a is Ti/Au 11%, 19 is resist, 20 is gold plating layer, 21a, 21b, 21c, 21d is chip, 22
23 is the intersection of the scribe line recess, and 23 is the part where the Ti/Au film is removed.岑46 Akira party example side view Figure 1 Country m-n line town prisoner Figure 2 Scry 7゛ line concave #14 Handling example 2■ Camper figure 3

Claims (1)

[Claims] In the process of manufacturing a semiconductor chip with a plated heat sink structure, a wafer (12) attached to a substrate (11) with an adhesive (13) is provided with a scribe line recess (14) to form a heat sink. a step of forming a plating base metal film (18a) on the entire surface of the wafer; a step of forming a plating base metal film (18a) on the entire surface of the wafer;
14) removing the plating base metal film (18a) over the portion that extends inwards, a plating layer (20) on the plating base metal film (18a);
1. A method of manufacturing a semiconductor device, the method comprising the step of forming a semiconductor device.