JPH04144245A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect a chip end surface, and prevent cracks and breaks at the time of handling, by wrapping the dicing region of a substrate with a heat dissipating electrode (PHS) formed on the rear of the substrate. CONSTITUTION:A base metal layer 12 for forming a PHS is formed on the rear side of a thinned GaAs substrate 1, and a resist pattern 11 for selectively forming the PHS metal layer is formed on the rear side, except a part corresponding with a dicing region. A PHS 13 is formed by plating PHS on the base metal layer 12 by electroplating. After the resist pattern 11 used as a mask is eliminated, the metal layer 12 and an electroplated layer 5 in the dicing region are selectively eliminated by etching using the PHS 13 as a mask, and chip dividing is performed. After that, square chips in the divided state are exfoliated from a glass substrate 6, and washed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and more specifically, a semi-insulating GBAB substrate is used to form a γ field effect transistor C or a G
This relates to the divided γ-chip structure in devices such as aA3FET.

[Conventional technology]

Generally, in this type of GaA3FET, etc., a gate electrode, a north electrode, a drain electrode, etc. are provided to reduce thermal resistance and source inductance in the device configuration. The thickness of the plated heat 5 is reduced to about several IO μm, and a through hole is formed from the back side to the source electrode, and a heat dissipation electrode (Plated Heat 5
Inku (hereinafter referred to as PH5) is provided and used.

Here, a cross-sectional view of a conventional GaAsFET is shown in Fig. 3, and the main steps of its manufacturing method are shown in Fig. 4 (a).
) or [f) G shows. That is, in FIG. 3, [1] is a semi-insulating GaAs substrate, +21. +3)
and (4) are gate electrodes, source electrodes, and drain electrodes, respectively, for semiconductor elements formed occupying predetermined positions on the surface of the GaA substrate il+, and ■ is the gate electrode, source electrode, and drain electrode of the GaAs substrate (1). PH5 provided on the back side
The plating base metal layer for formation is PH5 formed via the plating base metal layer. However, in this conventional method, as shown in FIG. , and its gate electrode (2), source electrode (3), and drain electrode (4)
) are formed in a wafer state.
A glass substrate (6) is pasted and placed on the aA3 substrate (1) using pasting wax (7), and in this state GaA3
Cut the board (1) to the desired thickness (about several tens of meters) from the back side.
The first resist pattern (8) is formed on the back surface of the thinned T substrate (see FIG.
)).

Next, using the first resist pattern (8) as a mask, the GaAs substrate (1) is etched to form a through hole (9) that reaches the source electrode (3) from the back side thereof. Figure 4 (c) ), Mani, T used for mask
After removing the first resist pattern (8), a PH5 base metal layer (2) consisting of a gold layer and another metal layer is formed, and a second resist pattern 0η is formed in the corresponding portion of the predetermined dicing area. (Fig. 4(d)). next.

Use the second resist butter/cu) as a mask, and use the PH5
Applying plating (P on the plating base metal layer 03)
H5 (4th fN(e) to form Ll), and
After that, the second resist layer used as a mask is turned 01.
), and from now on, using this PH5QJ as a mask, remove the plating base metal layer Oa by etching.
Although not shown here, the semi-insulating GaAs substrate (1) was then etched into chips to form the semiconductor shown in FIG. You can get the equipment.

[Problem to be solved by the invention]

Conventional GaAsFETs require PH5,
The chip is divided by etching the semi-insulating QBA1 substrate used as a mask. GaA has a sharp end surface of the substrate, which has the disadvantage that the substrate 1111 surface, that is, the end surface of the chip, is easily chipped during subsequent handling of the chip. Etching the T-GaA substrate using PH5 as a mask (in this method, the finished shape of PH5 and the shape after removing the plating base metal layer are amplified to the shape of the main surface of the substrate after chip division). However, there is a problem in that irregular dimensions on the main surface of the substrate and over-etching tend to occur, resulting in a decrease in the yield of chip division.

The purpose of this invention is to solve the above-mentioned problems and to obtain a semiconductor device in which the end face of the chip is not easily chipped when handling the chip, and the chip can be provided with a high yield. ) [Solving the problem 1
A semiconductor device according to the present invention has semiconductor elements and their electrodes formed on the main surface of the substrate, and PH5 is formed on the back surface via a base metal layer. The dicing area of the substrate is covered with the formed PH5. In the semiconductor device, the dicing area of the substrate is covered with the PH5 formed on the back surface of the substrate, so that the heat dissipating electrode (
This protects the chip end face and prevents chips and cracks during handling.

First, since the caAa etching is performed using the resist pattern as a mask, it is possible to eliminate the drop in chip division yield caused by uneven dimensions on the main surface side of the substrate or overetching, and it is possible to perform chip division with a high yield.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a cross-sectional view schematically showing the outline of the chip structure of G, A, FET, which is an embodiment of the present invention.
1 to g) are respective sectional views schematically showing the main manufacturing steps of the chip structure shown in FIG. That is, in FIG. 1, (1) is a semi-insulating CaAa substrate,
+21. (3) and (4) are this GaAa substrate (
(1) is a gate electrode, a source electrode, and a drain electrode for a semiconductor element formed occupying a predetermined position on the main surface, and (5) is a dicing area (a metal selectively formed in this area). It is made of the same material as the back heat dissipation electrode (to).Furthermore, @ is G@ A6 substrate il
One plating base metal layer of PH5 formed on the back side of A3 is formed through the plating base metal layer 02 of PH5. In the method of this embodiment, as shown in FIGS. The gate electrode (2) and the source electrode (
3) and a drain electrode (4), respectively.
First, the surface of the GaA3 substrate (1) corresponding to the dicing area is dry-etched until it reaches the final thickness of the substrate and coated with the same material as the back surface PH5. still,
A through hole (via hole) for grounding the source electrode on the back surface is also formed at the same time (FIG. 2(a)).

Next, each of these electrodes (2) to 4), and a metal layer (5) are formed on each of the Ga layers in the γ-wafer state.
On the front side of the A3 board [11] is wax (7) for pasting.
) to attach the glass substrate (6), and in this state, cut the GaA3 substrate fil to the desired thickness c from the back side.
The layer is thinned by lapping and etching to a thickness of several tens of μm (Fig. 2(b)), and then P is applied to the back side of the four-layered GaA3 substrate (1).
Base metal layer for H5 formation (e.g. Ti:Au) (2)
Then, a γ resist pattern 01) for selectively forming a PH5 metal layer except for the portion corresponding to the dicing area is formed (Fig. 2(c)), and then electrolytic plating is performed. PH5 plating is performed on this plating base metal layer to form PH5Q3 (FIG. 2(d)). Then, remove the resist pattern 0υ used for the mask (71, 2 (e)) L 7=after, P
) (Using S (Ll) as a mask, the metal layer (metal layer (2), e.g., Ti:Au) and the electroplated layer (5) in the dicing area are selectively removed by etching, and chip division is performed (second step). After that, each divided chip is peeled off from the glass substrate (6) and cleaned, thus obtaining the device configuration shown in FIG. 1.

[Effects of the Invention] As described above, according to the present invention, in a semiconductor device in which a semiconductor element and its electrodes are formed on the main surface of a substrate, and PH5 is formed on the back surface side through a base metal layer, The formed PH5 coats the dicing area of the substrate c! -1rT Now, this PH5 coating (this protects the chip end face and prevents chips from chipping, cracking, etc. during handling). Etching of As.

Since the resist pattern is used as a mask, chip division can be performed with good dimensional accuracy and without over-etching. Therefore, when compared to etching of a substrate using PH5 as a mask, as in the conventional case, the formation accuracy, and even the post-etching The dimensions of the substrate itself can be significantly improved.

Etching imbalance within the wafer surface can be eliminated,
Coupled with the wrap-around coating on the back side of the substrate including the die area, PH5I makes it possible to make the chip dimensions uniform, making it possible to perform chip division with high yield.
It has this effect.

[Brief explanation of drawings]

FIG. 1 shows an L to which an embodiment of the semiconductor device according to the present invention is applied.
Figures 2(a) to 2(f) are cross-sectional views schematically showing the outline of the chip structure of the A3FET. Figures 3 and 3 are cross-sectional views schematically showing the outline of the chip structure of conventional (, IA, NET, Figures 4 (a) to f).
3 are respective cross-sectional views sequentially schematically showing the main manufacturing steps of the chip structure of FIG. 3. FIG. In the figure, [1] is a semi-insulating GaA substrate, (2)
is the gate electrode, (3) is the source electrode, (4) is the drain electrode, (5) is the metal layer, (6) is the wax attached to the glass substrate (7), and (8) is the first resist. The pattern, f9) is a through hole reaching the source electrode, aη is a resist pattern for selective PH5 plating, 021 is a base metal layer for plating, and the mark is PH5. In addition, in the figure, the same reference numerals indicate the same parts, and the same characters indicate the phase parts.

Claims (1)

[Claims] 1. A semiconductor device in which a semiconductor and its electrodes are formed on a main surface of a substrate, and a heat dissipation electrode is formed on a back surface side, wherein the heat dissipation electrode is configured to wrap around the semiconductor device.