JP2606940B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a high-frequency high-power GaAs IC having a PHS and a method of manufacturing the same.

[Conventional technology]

FIG. 3 is a cross-sectional view showing a method of manufacturing a conventional high-frequency high-power semiconductor device, and FIG. 4 is a schematic cross-sectional view showing the structure of a conventional high-frequency high-power semiconductor device. In FIG. Separation groove, 2 is an element portion such as a field effect transistor (hereinafter, referred to as FET), 3 is an electrolytic Au plating layer formed in the separation groove 1a, 4 is an attaching wax, 5 is a support plate, 6 is a PHS, 6a Represents burrs formed by dicing cut.

 Next, a manufacturing method will be described.

As shown in FIG. 3 (a), a chip separation groove 1a having a depth of about 40 μm is formed from the first surface side of the semiconductor substrate 1 on which the element portion 2 such as an FET is formed, and an inner wall portion of the separation groove 1a is formed. About 3μ
An m-thick electrolytic Au plating layer 3 is formed. Thereafter, in this state, the first surface of the substrate 1 and the support plate 5 are adhered to each other with wax 4 or the like, and the thickness of the substrate 1 is changed to the second surface side opposite to the first surface of the substrate 1. The electrolytic Au plating layer 3 polished to about 40 μm and formed on the inner wall of the separation groove 1a
Is exposed on the second surface side of the substrate 1 (FIG. 3 (b)).

Next, a plated heat sink (hereinafter referred to as PHS) having a thickness of about 50 μm is formed on the second surface of the substrate 1 by electrolytic Au plating.
6) (FIG. 3 (c)). Subsequently, the substrate 1 is peeled off from the support plate 5, the wax 4 and the like are removed by washing, and then cut with a dicer (FIG. 3 (d)). A semiconductor chip whose outline is shown in FIG. 4 is obtained.

In the conventional semiconductor device configured as described above, PHS6
Is a function as a radiator for dissipating heat generated from the element portion 2 such as an FET formed on the first surface side of the semiconductor substrate 1 to the chip carrier side, and a function of the thin semiconductor substrate 1 peeled off from the support plate 5. It has a function to facilitate handling. Electrolytic Au formed on the inner wall of the separation groove 1a
It has a function of preventing chipping due to handling of the semiconductor chip when mounting the plating layer 3 chip.

[Problems to be solved by the invention]

In the conventional semiconductor device configured as described above and the method of manufacturing the same, burrs 6a are generated on the back side of the PHS6 at the time of dicing cut of the PHS6, which becomes an obstacle at the time of mounting the chip on the chip carrier and causes a reduction in mounting yield. In addition to this, the length of the bonding wire becomes non-uniform and the variation in inductance becomes large, which causes a performance problem that input / output matching is difficult to obtain particularly in high frequency devices.

The present invention has been made to solve the above problems, and can prevent burrs of the PHS metal layer generated at the time of dicer cutting, thereby facilitating chip mounting and input / output matching. It is an object of the present invention to obtain a high-frequency high-output semiconductor device and a manufacturing method thereof.

[Means for solving the problem]

A method of manufacturing a high-frequency high-power semiconductor device having a PHS according to the present invention includes a step of etching a chip separation line portion on a first surface side of a substrate on which an FET or the like is formed to form a separation groove having a depth of about 40 μm. And selectively embedding the separation grooves by electroless Ni plating, and after bonding the substrate to a support plate with wax or the like, the second surface side opposite to the first surface of the substrate has a thickness of about 40 μm. Polishing to expose the bottom of the separation groove to the second surface side of the substrate, and PHS having a thickness of about 40 μm on a portion of the second surface of the substrate other than the chip separation line by selective electrolytic plating such as Au. And a step of separating the substrate into chips by dicing after removing and washing the substrate from the support plate.

Further, a semiconductor device according to the present invention is characterized in that the chip is manufactured by the above method, and the chip has a structure in which a separation side wall of the semiconductor portion is surrounded by a Ni plating layer.

[Action]

In the present invention, since the inside of the chip separation groove is filled with an electroless Ni plating layer having a leveling action and PHS is formed by selective electrolytic plating, the chip separation without cutting the Au plating PHS at the time of dicer cutting. Only the electroless Ni plating layer filled in the groove can be cut. Also Au
Since the plating PHS and the electroless Ni plating layer have a bonding portion around the semiconductor substrate portion of the chip, it can be handled without breaking even a thin wafer peeled off the support plate.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a method of manufacturing a high-frequency high-power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic sectional view showing the structure of the semiconductor device.
Substrate, 1a is a chip separation groove, 2 is an element part such as FET, 4 is a wax for bonding, 5 is a support plate, 6 is a PHS, 7 is a Ni electroless plating layer, and 8 is a photoresist layer. . As shown in FIG. 2, the GaAs substrate 1 part has a Ni plating layer 7 around it in a chip state, and has a structure in which the plating layer 7 and the PHS 6 are joined around the substrate 1. I have.

Next, a process flow for forming a semiconductor device will be described.

FIG. 1A shows that a chip separation groove 1a having a depth of about 40 μm is formed from the first surface side of a GaAs substrate 1 on which an element portion 2 such as an FET is formed, and the chip separation groove 1a is selectively formed in the separation groove 1a. This is a state where the electrolytic Ni plating layer 7 is filled. The electroless Ni plating layer 7 has a desired portion, that is, the inside of the separation groove 1a is activated with a catalytic metal such as Pd, and an insulating film such as a silicon nitride film or a silicon oxide film is formed in a region other than the desired portion. If formed, selective growth is possible.

After the state shown in FIG. 1A, the first surface of the GaAs substrate 1 is attached to a support plate 5 with wax 4 or the like, and
The second surface of the substrate 1 opposite to the first surface is polished until the GaAs substrate 1 has a thickness of about 40 μm, and the electroless Ni plating layer 7 formed inside the separation groove 1a is It is exposed on the second surface side of the substrate 1 (FIG. 1 (b)).

Next, a PHS 6 having a thickness of about 50 μm is formed on the second surface of the GaAs substrate 1 by selective electrolytic Au plating using the photoresist layer 8 as a mask (FIG. 1C). At this time, Au plating
Selective electrolytic Au plating is performed so that the PHS 6 and the electroless Ni plating layer 7 have a joint around the semiconductor substrate portion of the chip.

Subsequently, the GaAs substrate 1 was peeled off from the support plate 5, and the wax 4 and the like were washed and removed.
A semiconductor chip whose outline is shown in the figure is obtained.

In the semiconductor device of the present embodiment configured as described above, since the Ni plating layer 7 is provided around a part of the GaAs substrate of the chip,
Chips do not chip even if they are handled with a collet or tweezers in the mounting process.

Also, the selective plating Au is applied so that the Au plating PHS6 and the electroless Ni plating layer 7 have a joint around the semiconductor substrate 1 part of the chip.
Since the plating is performed, even a thin wafer peeled off from the support plate 5 can be handled without breaking.

Further, in the manufacturing method of this embodiment, the inside of the chip separation groove is filled with an electroless Ni plating layer having a leveling action, and the PHS
Is formed by selective electrolytic plating, so that only the electroless Ni plating layer filled in the chip separation groove can be cut without cutting the Au plating PHS at the time of dicer cutting. As a result, the bottom of the chip can be flattened without burrs due to dicer cutting of the PHS metal layer, and chip mounting and input / output matching can be facilitated.

In the above embodiment, Au plating is used as the PHS. However, any other metal material or alloy having good heat conductivity such as Cu may be used. Also, as a semiconductor substrate
Although a GaAs substrate was used, any semiconductor substrate such as a Si substrate, an InP substrate, or a substrate obtained by epitaxially growing a GaAs substrate layer on a Si substrate may be used.

〔The invention's effect〕

As described above, according to the semiconductor device of the present invention, the chip is surrounded by the Ni plating layer on the semiconductor portion isolation side wall and has a structure in which the chip is joined to the PHS, so that the chip is handled by a collet or tweezers in the mounting process. Also, there is an effect that chips are not chipped and a thin wafer peeled off from the support plate can be handled without breaking.

Further, according to the method for manufacturing a semiconductor device of the present invention, the Au plating PHS is not cut at the time of dicer cutting, and only the electroless Ni plating layer filled in the chip separation groove is cut. This has the effect of preventing the occurrence of burrs and flattening the bottom surface of the chip to improve the workability of mounting and characteristic matching.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a high-frequency high-power semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic sectional view showing the structure of the semiconductor device, and FIG. FIG. 4 is a schematic sectional view showing the structure of a conventional high-frequency high-power semiconductor device. In the figure, 1 is a GaAs substrate, 1a is a chip separation groove, 2 is FE
Element parts such as T, 4 is a sticking wax, 5 is a support plate, 6 is a PHS, 7 is a Ni electroless plating layer, and 8 is a photoresist layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] In a method of manufacturing a high-frequency high-power semiconductor device having a plated heat sink (PHS), a chip separation line portion on a first surface side of a substrate on which an element portion is formed is etched to have a predetermined depth. A step of forming a groove, a step of selectively embedding the separation groove by electroless Ni plating, and a step of attaching the substrate to a support plate, and then, after adhering the substrate to a support plate, a second surface side opposite to the substrate first surface Polishing the substrate to a thickness equal to the predetermined depth, exposing the bottom of the separation groove to the second surface side of the substrate, and selectively electroplating the second surface of the substrate. Forming a PHS having a predetermined thickness on a portion excluding a chip separation line portion; and removing the substrate from the support plate, washing the semiconductor substrate, and separating the chip into chips by dicing. Device manufacturing method . 2. The semiconductor device according to claim 1, wherein said chip has a structure in which a separation side wall of a semiconductor portion is surrounded by a Ni plating layer.