JP2606940B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2606940B2 JP2606940B2 JP2931090A JP2931090A JP2606940B2 JP 2606940 B2 JP2606940 B2 JP 2606940B2 JP 2931090 A JP2931090 A JP 2931090A JP 2931090 A JP2931090 A JP 2931090A JP 2606940 B2 JP2606940 B2 JP 2606940B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- phs
- semiconductor device
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Dicing (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置およびその製造方法に関し、特
にPHSを有する高周波高出力GaAsICおよびその製造方法
に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a high-frequency high-power GaAs IC having a PHS and a method of manufacturing the same.
第3図は従来の高周波高出力半導体装置の製造方法を
示す断面図、第4図は従来の高周波高出力半導体装置の
構成を示す概観断面図であり、図において1は半導体基
板、1aはチップ分離溝、2は電界効果トランジスタ(以
下、FETと称す)などの素子部、3は分離溝1aに形成し
た電解Auメッキ層、4は貼り付け用ワックス、5は支持
板、6はPHS、6aはダイシングカットによるバリをそれ
ぞれ表わしている。FIG. 3 is a cross-sectional view showing a method of manufacturing a conventional high-frequency high-power semiconductor device, and FIG. 4 is a schematic cross-sectional view showing the structure of a conventional high-frequency high-power semiconductor device. In FIG. Separation groove, 2 is an element portion such as a field effect transistor (hereinafter, referred to as FET), 3 is an electrolytic Au plating layer formed in the separation groove 1a, 4 is an attaching wax, 5 is a support plate, 6 is a PHS, 6a Represents burrs formed by dicing cut.
次に製造方法について説明する。 Next, a manufacturing method will be described.
第3図(a)に示したようにFETなどの素子部2を形
成した半導体基板1の第1の面側から深さ約40μmのチ
ップ分離溝1aを形成し、前記分離溝1aの内壁部に約3μ
m厚の電解Auメッキ層3を形成する。その後この状態
で、ワックス4などにより前記基板1の第1の面と支持
板5とを貼り付け、前記基板1の第1の面とは反対側の
第2の面側を前記基板1厚が約40μmとなるまで研磨
し、前記分離溝1aの内壁部に形成した電解Auメッキ層3
を前記基板1の第2の面側に露出させる(第3図
(b))。As shown in FIG. 3 (a), a chip separation groove 1a having a depth of about 40 μm is formed from the first surface side of the semiconductor substrate 1 on which the element portion 2 such as an FET is formed, and an inner wall portion of the separation groove 1a is formed. About 3μ
An m-thick electrolytic Au plating layer 3 is formed. Thereafter, in this state, the first surface of the substrate 1 and the support plate 5 are adhered to each other with wax 4 or the like, and the thickness of the substrate 1 is changed to the second surface side opposite to the first surface of the substrate 1. The electrolytic Au plating layer 3 polished to about 40 μm and formed on the inner wall of the separation groove 1a
Is exposed on the second surface side of the substrate 1 (FIG. 3 (b)).
次に、前記基板1の第2の面上に電解Auメッキにより
約50μm厚のプレーティッドヒートシンク(以下、PHS
と称す)6を形成し(第3図(c))、続いて前記基板
1を支持板5から剥がし、ワックス4などを洗浄除去し
た後、ダイサーでカットし(第3図(d))、第4図に
その概観を示すような半導体チップを得る。Next, a plated heat sink (hereinafter referred to as PHS) having a thickness of about 50 μm is formed on the second surface of the substrate 1 by electrolytic Au plating.
6) (FIG. 3 (c)). Subsequently, the substrate 1 is peeled off from the support plate 5, the wax 4 and the like are removed by washing, and then cut with a dicer (FIG. 3 (d)). A semiconductor chip whose outline is shown in FIG. 4 is obtained.
上記のように構成された従来の半導体装置では、PHS6
は、半導体基板1の第1の面側に形成したFETなどの素
子部2から発生する熱をチップキャリア側に逃がすため
の放熱体としての機能、及び支持板5から剥がした薄い
半導体基板1のハンドリングを容易にするための機能を
有している。また分離溝1aの内壁部に形成された電解Au
メッキ層3チップ実装時において、半導体チップのハン
ドリングによるかけ(チッピング)を防止する機能を有
している。In the conventional semiconductor device configured as described above, PHS6
Is a function as a radiator for dissipating heat generated from the element portion 2 such as an FET formed on the first surface side of the semiconductor substrate 1 to the chip carrier side, and a function of the thin semiconductor substrate 1 peeled off from the support plate 5. It has a function to facilitate handling. Electrolytic Au formed on the inner wall of the separation groove 1a
It has a function of preventing chipping due to handling of the semiconductor chip when mounting the plating layer 3 chip.
上記のように構成された従来の半導体装置およびその
製造方法では、PHS6のダイシングカット時にPHS6側の裏
面側にバリ6aが発生し、チップキャリアへのチップ実装
時の障害となり、実装歩留まり低下の原因となるばかり
か、ボンディングワイヤの長さが不均一となり、インダ
クタンスのばらつきが大きくなるため、特に高周波デバ
イスでは入出力整合が取りにくくなるという性能上の問
題を引き起こす原因となっていた。In the conventional semiconductor device configured as described above and the method of manufacturing the same, burrs 6a are generated on the back side of the PHS6 at the time of dicing cut of the PHS6, which becomes an obstacle at the time of mounting the chip on the chip carrier and causes a reduction in mounting yield. In addition to this, the length of the bonding wire becomes non-uniform and the variation in inductance becomes large, which causes a performance problem that input / output matching is difficult to obtain particularly in high frequency devices.
この発明は上記のような問題点を解決するためになさ
れたもので、ダイサーカット時に発生するPHS金属層の
バリを防止することができ、これによりチップの実装及
び入出力整合を容易に行うことのできる高周波高出力半
導体装置およびその製造方法を得ることを目的とするも
のである。The present invention has been made to solve the above problems, and can prevent burrs of the PHS metal layer generated at the time of dicer cutting, thereby facilitating chip mounting and input / output matching. It is an object of the present invention to obtain a high-frequency high-output semiconductor device and a manufacturing method thereof.
この発明にかかるPHSを有する高周波高出力半導体装
置の製造方法は、FETなどを形成する基板の第1の面側
のチップ分離ライン部をエッチングし、深さ約40μmの
分離溝を形成する工程と、分離溝を無電解Niメッキで選
択的に埋め込む工程と、基板をワックスなどで支持板に
貼り付けた後、基板第1の面とは反対側の第2の面側を
基板厚が約40μmになるまで研磨し分離溝の底部を基板
の第2の面側に露出する工程と、Auなどの選択電解メッ
キによって基板の第2の面のチップ分離ラインを除く部
分上に約40μm厚のPHSを形成する工程と、基板を支持
板から剥がし洗浄した後、ダイシングによりチップに分
離する工程とを含むことを特徴とするものである。A method of manufacturing a high-frequency high-power semiconductor device having a PHS according to the present invention includes a step of etching a chip separation line portion on a first surface side of a substrate on which an FET or the like is formed to form a separation groove having a depth of about 40 μm. And selectively embedding the separation grooves by electroless Ni plating, and after bonding the substrate to a support plate with wax or the like, the second surface side opposite to the first surface of the substrate has a thickness of about 40 μm. Polishing to expose the bottom of the separation groove to the second surface side of the substrate, and PHS having a thickness of about 40 μm on a portion of the second surface of the substrate other than the chip separation line by selective electrolytic plating such as Au. And a step of separating the substrate into chips by dicing after removing and washing the substrate from the support plate.
また、この発明にかかる半導体装置は、上記方法で製
造し、チップを、その半導体部の分離側壁をNiメッキ層
で囲いこんだ構造としたことを特徴とするものである。Further, a semiconductor device according to the present invention is characterized in that the chip is manufactured by the above method, and the chip has a structure in which a separation side wall of the semiconductor portion is surrounded by a Ni plating layer.
この発明においては、チップ分離溝内部にレベリング
作用を有する無電解Niメッキ層を充填し、PHSを選択電
解メッキで形成するようにしたから、ダイサーカット時
にAuメッキPHSをカットせずに前記チップ分離溝内部に
充填した無電解Niメッキ層のみをカットできる。またAu
メッキPHSと無電解Niメッキ層がチップの半導体基板部
周囲に接合部を有するので、支持板から剥がした薄いウ
エハでも割ることなくハンドリングできる。In the present invention, since the inside of the chip separation groove is filled with an electroless Ni plating layer having a leveling action and PHS is formed by selective electrolytic plating, the chip separation without cutting the Au plating PHS at the time of dicer cutting. Only the electroless Ni plating layer filled in the groove can be cut. Also Au
Since the plating PHS and the electroless Ni plating layer have a bonding portion around the semiconductor substrate portion of the chip, it can be handled without breaking even a thin wafer peeled off the support plate.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの発明の一実施例による高周波高出力半導
体装置の製造方法を示す断面図、第2図はその半導体装
置の構成を示す概観断面図であり、図において1はGaAs
基板、1aはチップ分離溝、2はFETなどの素子部、4は
貼り付け用ワックス、5は支持板、6はPHS、7はNi無
電解メッキ層、8はフォトレジスト層をそれぞれ表わし
ている。また、第2図に示すように上記GaAs基板1部は
チップ状態ではその周囲にNiメッキ層7を有し、該メッ
キ層7と上記PHS6とが上記基板1の周囲で接合した構造
となっている。FIG. 1 is a sectional view showing a method of manufacturing a high-frequency high-power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic sectional view showing the structure of the semiconductor device.
Substrate, 1a is a chip separation groove, 2 is an element part such as FET, 4 is a wax for bonding, 5 is a support plate, 6 is a PHS, 7 is a Ni electroless plating layer, and 8 is a photoresist layer. . As shown in FIG. 2, the GaAs substrate 1 part has a Ni plating layer 7 around it in a chip state, and has a structure in which the plating layer 7 and the PHS 6 are joined around the substrate 1. I have.
次に半導体装置形成のプロセスフローについて説明す
る。Next, a process flow for forming a semiconductor device will be described.
第1図(a)はFETなどの素子部2を形成したGaAs基
板1の第1の面側から深さ約40μmのチップ分離溝1aを
形成し、前記分離溝1aの内部に選択的に無電解Niメッキ
層7を充填した状態である。この無電解Niメッキ層7は
所望の部分、つまり前記分離溝1aの内部をPdなどの触媒
金属で活性化しておき、所望の部分以外の領域にシリコ
ン窒化膜,シリコン酸化膜などの絶縁膜を形成しておけ
ば、選択成長が可能である。FIG. 1A shows that a chip separation groove 1a having a depth of about 40 μm is formed from the first surface side of a GaAs substrate 1 on which an element portion 2 such as an FET is formed, and the chip separation groove 1a is selectively formed in the separation groove 1a. This is a state where the electrolytic Ni plating layer 7 is filled. The electroless Ni plating layer 7 has a desired portion, that is, the inside of the separation groove 1a is activated with a catalytic metal such as Pd, and an insulating film such as a silicon nitride film or a silicon oxide film is formed in a region other than the desired portion. If formed, selective growth is possible.
第1図(a)の状態の後、前記GaAs基板1の第1の面
をワックス4などにより支持板5に貼り付け、前記GaAs
基板1の第1の面とは反対側の第2の面側を前記GaAs基
板1厚が約40μmとなるまで研磨し、前記分離溝1aの内
部に形成した無電解Niメッキ層7を前記GaAs基板1の第
2の面側に露出する(第1図(b))。After the state shown in FIG. 1A, the first surface of the GaAs substrate 1 is attached to a support plate 5 with wax 4 or the like, and
The second surface of the substrate 1 opposite to the first surface is polished until the GaAs substrate 1 has a thickness of about 40 μm, and the electroless Ni plating layer 7 formed inside the separation groove 1a is It is exposed on the second surface side of the substrate 1 (FIG. 1 (b)).
次に、前記GaAs基板1の第2の面上にフォトレジスト
層8をマスクとした選択電解Auメッキにより約50μm厚
のPHS6を形成する(第1図(c))。この時、Auメッキ
PHS6と無電解Niメッキ層7がチップの半導体基板部周囲
で接合部を有するように選択電解Auメッキを行う。Next, a PHS 6 having a thickness of about 50 μm is formed on the second surface of the GaAs substrate 1 by selective electrolytic Au plating using the photoresist layer 8 as a mask (FIG. 1C). At this time, Au plating
Selective electrolytic Au plating is performed so that the PHS 6 and the electroless Ni plating layer 7 have a joint around the semiconductor substrate portion of the chip.
続いて上記GaAs基板1を支持板5から剥がし、ワック
ス4などを洗浄除去した後、ダイサーでカットし、第2
図にその概観を示すような半導体チップを得る。Subsequently, the GaAs substrate 1 was peeled off from the support plate 5, and the wax 4 and the like were washed and removed.
A semiconductor chip whose outline is shown in the figure is obtained.
上記のように構成した本実施例の半導体装置では、チ
ップのGaAs基板1部周囲にNiメッキ層7を有するので、
実装工程においてコレットあるいはピンセットなどでハ
ンドリングをしても、チップの欠けが発生しない。In the semiconductor device of the present embodiment configured as described above, since the Ni plating layer 7 is provided around a part of the GaAs substrate of the chip,
Chips do not chip even if they are handled with a collet or tweezers in the mounting process.
また、AuメッキPHS6と無電解Niメッキ層7がチップの
半導体基板1部周囲で接合部を有するように選択電解Au
メッキを行ったので、支持板5から剥がした薄いウエハ
でも割ることなくハンドリングできる。Also, the selective plating Au is applied so that the Au plating PHS6 and the electroless Ni plating layer 7 have a joint around the semiconductor substrate 1 part of the chip.
Since the plating is performed, even a thin wafer peeled off from the support plate 5 can be handled without breaking.
また本実施例の製造方法では、チップ分離溝内部にレ
ベリング作用を有する無電解Niメッキ層を充填し、PHS
を選択電解メッキで形成するようにしたので、ダイサー
カット時にAuメッキPHSをカットせずに前記チップ分離
溝内部に充填した無電解Niメッキ層のみをカットでき
る。これによりPHS金属層のダイサーカットによるバリ
をなくしてチップ底面を平坦化でき、チップの実装及び
入出力整合が容易となる。Further, in the manufacturing method of this embodiment, the inside of the chip separation groove is filled with an electroless Ni plating layer having a leveling action, and the PHS
Is formed by selective electrolytic plating, so that only the electroless Ni plating layer filled in the chip separation groove can be cut without cutting the Au plating PHS at the time of dicer cutting. As a result, the bottom of the chip can be flattened without burrs due to dicer cutting of the PHS metal layer, and chip mounting and input / output matching can be facilitated.
なお、上記実施例ではPHSとしてAuメッキを用いた
が、これにはCuなど熱伝導の良好な他の金属材料あるい
は合金を用いたものでも良い。また半導体基板としては
GaAs基板を用いたが、これはSi基板,InP基板,Si基板上
にGaAs基板層をエピタキシャル成長したものなど半導体
基板であればいずれでもよい。In the above embodiment, Au plating is used as the PHS. However, any other metal material or alloy having good heat conductivity such as Cu may be used. Also, as a semiconductor substrate
Although a GaAs substrate was used, any semiconductor substrate such as a Si substrate, an InP substrate, or a substrate obtained by epitaxially growing a GaAs substrate layer on a Si substrate may be used.
以上のように、この発明にかかる半導体装置によれ
ば、チップをその半導体部分離側壁をNiメッキ層で囲
い、PHSと接合した構造としたので、実装工程において
コレットあるいはピンセットなどでハンドリングをして
も、チップの欠けが発生することはなく、また支持板か
ら剥がした薄いウエハでも割ることなくハンドリングで
きる効果がある。As described above, according to the semiconductor device of the present invention, the chip is surrounded by the Ni plating layer on the semiconductor portion isolation side wall and has a structure in which the chip is joined to the PHS, so that the chip is handled by a collet or tweezers in the mounting process. Also, there is an effect that chips are not chipped and a thin wafer peeled off from the support plate can be handled without breaking.
また本発明の半導体装置の製造方法によれば、ダイサ
ーカット時にAuメッキPHSをカットせず、前記チップ分
離溝内部に充填した無電解Niメッキ層のみをカットする
ようにしたので、PHSの裏面におけるバリの発生を防止
でき、チップ底面を平坦化して実装や特性整合の作業性
を改善できる効果がある。Further, according to the method for manufacturing a semiconductor device of the present invention, the Au plating PHS is not cut at the time of dicer cutting, and only the electroless Ni plating layer filled in the chip separation groove is cut. This has the effect of preventing the occurrence of burrs and flattening the bottom surface of the chip to improve the workability of mounting and characteristic matching.
第1図はこの発明の一実施例による高周波高出力半導体
装置の製造方法を示す断面図、第2図は上記半導体装置
の構成を示す概観断面図、第3図は従来の高周波高出力
半導体装置の製造方法を示す断面図、第4図は従来の高
周波高出力半導体装置の構成を示す概観断面図である。 図において、1はGaAs基板、1aはチップ分離溝、2はFE
Tなどの素子部、4は貼り付け用ワックス、5は支持
板、6はPHS、7はNi無電解メッキ層、8はフォトレジ
スト層である。 なお図中同一符号は同一又は相当部分を示す。FIG. 1 is a sectional view showing a method of manufacturing a high-frequency high-power semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic sectional view showing the structure of the semiconductor device, and FIG. FIG. 4 is a schematic sectional view showing the structure of a conventional high-frequency high-power semiconductor device. In the figure, 1 is a GaAs substrate, 1a is a chip separation groove, 2 is FE
Element parts such as T, 4 is a sticking wax, 5 is a support plate, 6 is a PHS, 7 is a Ni electroless plating layer, and 8 is a photoresist layer. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (2)
する高周波高出力半導体装置の製造方法において、 素子部を形成する基板の第1の面側のチップ分離ライン
部をエッチングし、所定の深さの分離溝を形成する工程
と、 前記分離溝を無電解Niメッキで選択的に埋め込む工程
と、 前記基板を支持板に貼り付けた後、前記基板第1の面と
は反対側の第2の面側を基板厚が上記所定深さと等しい
厚さになるまで研磨し、前記分離溝の底部を前記基板の
第2の面側に露出する工程と、 選択電解メッキによって前記基板の第2の面の前記チッ
プ分離ライン部を除く部分上の上記所定厚さのPHSを形
成する工程と、 前記基板を前記支持板から剥がし、洗浄した後、ダイシ
ングによりチップに分離する工程とを含むことを特徴と
する半導体装置の製造方法。In a method of manufacturing a high-frequency high-power semiconductor device having a plated heat sink (PHS), a chip separation line portion on a first surface side of a substrate on which an element portion is formed is etched to have a predetermined depth. A step of forming a groove, a step of selectively embedding the separation groove by electroless Ni plating, and a step of attaching the substrate to a support plate, and then, after adhering the substrate to a support plate, a second surface side opposite to the substrate first surface Polishing the substrate to a thickness equal to the predetermined depth, exposing the bottom of the separation groove to the second surface side of the substrate, and selectively electroplating the second surface of the substrate. Forming a PHS having a predetermined thickness on a portion excluding a chip separation line portion; and removing the substrate from the support plate, washing the semiconductor substrate, and separating the chip into chips by dicing. Device manufacturing method .
半導体装置において、 上記チップを、その半導体部の分離側壁をNiメッキ層で
囲いこんだ構造としたことを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said chip has a structure in which a separation side wall of a semiconductor portion is surrounded by a Ni plating layer.
Priority Applications (1)
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JP2931090A JP2606940B2 (en) | 1990-02-07 | 1990-02-07 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2931090A JP2606940B2 (en) | 1990-02-07 | 1990-02-07 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
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JPH03232253A JPH03232253A (en) | 1991-10-16 |
JP2606940B2 true JP2606940B2 (en) | 1997-05-07 |
Family
ID=12272650
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JP2931090A Expired - Lifetime JP2606940B2 (en) | 1990-02-07 | 1990-02-07 | Semiconductor device and manufacturing method thereof |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US6940157B2 (en) | 2002-08-21 | 2005-09-06 | Kabushiki Kaisha Toshiba | High frequency semiconductor module, high frequency semiconductor device and manufacturing method for the same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06209058A (en) * | 1993-01-12 | 1994-07-26 | Mitsubishi Electric Corp | Semiconductor device, its manufacture, and its mounting method |
JPH06268112A (en) * | 1993-03-10 | 1994-09-22 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JP2810322B2 (en) * | 1993-07-16 | 1998-10-15 | 株式会社ジャパンエナジー | Method for manufacturing semiconductor device |
JP2625368B2 (en) * | 1993-12-16 | 1997-07-02 | 日本電気株式会社 | Semiconductor substrate |
WO2004090975A1 (en) * | 2003-04-08 | 2004-10-21 | Koninklijke Philips Electronics N.V. | Method of manufacturing semiconductor devices |
JP6027027B2 (en) * | 2011-12-21 | 2016-11-16 | ビービーエスエイ リミテッドBBSA Limited | Semiconductor device, method for manufacturing the same, and semiconductor device combination |
-
1990
- 1990-02-07 JP JP2931090A patent/JP2606940B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6940157B2 (en) | 2002-08-21 | 2005-09-06 | Kabushiki Kaisha Toshiba | High frequency semiconductor module, high frequency semiconductor device and manufacturing method for the same |
Also Published As
Publication number | Publication date |
---|---|
JPH03232253A (en) | 1991-10-16 |
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