JPH07176760A - Wafer having phs structure and its manufacture - Google Patents

Abstract

PURPOSE:To provide a wafer having a PHS structure allowing handling of the wafer and facilitating cutting for chip separation of the wafer and its manufacture. CONSTITUTION:The rear side of a main surface 44 provided with an element of a thin plate semiconductor substrate 42 constituting this wafer 40 is provided with a lower part metal layer 46 ranging over the whole surface of ths wafer 40. Then, a thickness of this lower part metal layer 46 is that allowing handling of this wafer 40 and facilitating cutting of this wafer 40 at the time of chip separation. And, a current film 52 is provided to form the lower part metal layer 46 by a plating method. Further, an upper part metal layer 54 as a heat sink is provided on the non-scribe line region of this lower part metal layer 46.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a wafer as a base of a semiconductor element and a method for manufacturing the same.

[0002]

2. Description of the Related Art When a semiconductor device is operated, heat is generated. This heat needs to be effectively dissipated in the package of the semiconductor device or the like. Therefore, for example, Ga
A PHS (plated heat sink) structure is used in high-power transistors and monolithic ICs that operate in the quasi-microwave to microwave to millimeter wave (several 100 MHz to 100 GHz) band using an As or InP substrate.

In order to facilitate understanding of the present invention, an example of a conventional semiconductor device having a PHS structure will be briefly described below with reference to the drawings. FIG. 5 shows the conventional P
FIG. 3 is a partial cross-sectional perspective view for explaining a semiconductor element using a wafer having an HS structure as a base.

In the PHS structure, the GaAs semiconductor substrate 12 forming the wafer 10 is usually thinned to a thickness of 20 to 100 μm for effective heat dissipation. Then, a thick metal layer (for example, gold) 18 having high thermal conductivity is formed by plating on the back surface side of the main surface 16 on which the functional element 14 is formed of the thinned semiconductor substrate 12 to form a heat sink. Further, the semiconductor substrate (also referred to as a substrate) 12 is provided with a via hole 20 penetrating the substrate 12 and having a diameter of about 10 to 100 μm. Through the via hole 20, the main surface 16 side of the semiconductor substrate 12 and the back surface thereof are electrically and thermally connected. Further, the grounding inductance of the semiconductor element can be reduced by the via hole 20.

A cross-sectional view of a PHS structure having via holes similar to the semiconductor device shown in FIG.
Basics of Field Effect Transistors, 1992, published by The Institute of Electronics, Information and Communication Engineers, pp. 213, FIG. 5.22. In this cross-sectional view, the substrate is thinned to a thickness of 25 μm and
The thickness of the wafer having the S structure is 50 μm. Therefore, it can be seen that the thickness of the metal layer (gold electrode) of the wafer described in this document is 25 μm.

Next, an example of a conventional method of manufacturing a wafer having a PHS structure will be described. 6 (A)-
FIG. 3C is a sectional process diagram for explaining a method for manufacturing a wafer having a conventional PHS structure. FIG. 7A is a sectional process drawing following FIG. 6C. FIG. 7B shows
It is sectional drawing when the board | substrate on a scribe line is not removed. 6 and 7, the structure of the functional element formed on the main surface of the substrate is omitted.

In the method of manufacturing a wafer having the PHS structure shown in FIG. 6, first, a functional element (not shown) is formed on the main surface 16 of the substrate 12, and then the main surface 16 side of the substrate 12 is made of quartz. The support material 22 is attached to the support material 22 using the attachment material 24. Next, the attached substrate 12 is polished from its back surface to be thinned to a thickness of 50 to 100 μm ((A) of FIG. 6).

Next, the via hole 20 is formed in the thinned substrate 12, and the substrate 1 on the scribe line 26 is formed.
Two parts are removed ((B) of FIG. 6).

Next, a current film 28 is formed on the entire surface of the wafer 10 including the substrate-removed portion on the back surface side of the substrate 12 by vapor deposition or sputtering. Then, an Au plating layer 30 is formed on the current film 28 by electroplating. The plated layer 30 serves as a heat sink ((C) of FIG. 6).

Further, by forming the thick plating layer 30 over the entire surface of the wafer 10, the wafer 10 constituted by the substrate 12 which is originally made of a thin compound semiconductor having a high brittleness has a wide area of 2 inches or 3 inches. The strength required for handling in the area can be kept waiting. When plating, the Ni layer can be formed as a plating layer by electroless plating.

Next, the wafer 10 is peeled off from the support material 22 so that the plating layer 30 side becomes an adhesive surface.
Is pasted on the dicing tape 32 ((A) of FIG. 7).

In this conventional example, the semiconductor substrate on the scribe line was removed, but this reduces the internal stress of the substrate and the stress caused by the difference in the coefficient of thermal expansion between the substrate and the plating layer, and warps the substrate. This is to avoid damage. However, as shown in FIG. 7B, the scribe line 26
In some cases, the upper semiconductor substrate is not removed.

P attached to the dicing tape 32
The wafer 10 having the HS structure has a scribe line 26.
Is cut along with and separated into chips. At the time of cutting, a diamond blade (not shown) is usually used as a dicing saw. The diamond blade has a structure in which fine diamond abrasive grains are embedded in a metal piece called a bond or a resin resin.

[0014]

[Problems to be Solved by the Invention] However, PHS
When a metal having a low hardness and a high malleability such as gold (Au) or copper (Cu) is used as the metal layer forming the structure, the metal layer is continuously formed over a long distance using a diamond blade. It is difficult to cut. This is because the metal pieces generated during cutting adhere to the bond of the blade and fill the protrusions of the diamond abrasive grains to flatten them. This phenomenon becomes remarkable when Au having a thickness of several tens of μm or more is used for the metal layer. For example, thickness 20
Approximately 100c when cutting the metal layer made of Au of μm
When a distance of m is cut, chipping of the cut surface starts to occur.
When the thickness of the Au metal layer is 50 μm,
A few cm is the limit. Such chipping of the cut surface not only causes a defective appearance of the chip, but also causes cracks in the semiconductor substrate.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a wafer having a PHS structure and a method of manufacturing the same, which can handle the wafer and can be easily cut for separating the wafer into chips.

[0016]

According to the wafer having the PHS structure of the present invention, the PH which becomes the base of the semiconductor element is
In a wafer having an S (plated heat sink) structure,
A thin metal substrate constituting this wafer is provided with a lower metal layer over the entire surface of this wafer on the back surface side of the main surface on which the elements are provided, and the thickness of this lower metal layer enables handling of this wafer. And a thickness that facilitates cutting of the wafer during chip separation, and an upper metal layer as a heat sink on at least a part of the non-scribe line region of the lower metal layer. .

Further, according to the method of manufacturing a wafer having the PHS structure of the present invention, in manufacturing a wafer as a base of a semiconductor element, a semiconductor substrate having the main surface side provided with the functional element attached to a support material is used. The step of thinning, and the entire back surface side of the main surface of this thinned semiconductor substrate,
A step of forming a lower metal layer having a thickness that enables wafer handling and facilitates cutting of the wafer during chip separation, and a heat sink on at least a portion of the non-scribe line region of the lower metal layer. And a step of forming an upper metal layer as.

However, the handling here means the handling of the wafer from the step of peeling the wafer from the support material to the step of dicing. For example, the handling of the wafer when performing cleaning for removing the wax after peeling from the support material, and the handling of the wafer when performing measurement of the electrical characteristics of the wafer after the cleaning, if necessary.

The handling is possible so that the wafer is not broken by its own weight when the edge of the wafer is lifted, and the wafer has a strength capable of withstanding the tensile stress when the wafer is peeled from the support material. Means that.

[0020]

According to the wafer having the PHS structure and the method of manufacturing the same of the present invention, the lower metal layer which also functions as a heat sink and a reinforcing member for handling the wafer is provided over the entire surface of the wafer. The lower electrode layer has a thickness that allows handling and facilitates cutting of the wafer during chip separation. Then, an upper metal layer as a heat sink is provided in at least a part of the region excluding the scribe line to effectively dissipate the heat.
Therefore, it is possible to obtain a wafer having a PHS structure that can be handled and easily cut without impairing effective heat dissipation.

[0021]

Embodiments of a wafer having a PHS structure and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the sizes, shapes, and arrangement relationships of the respective constituent components to the extent that the present invention can be understood. Therefore, it is obvious that the present invention is not limited to this illustrated example. In the drawings referred to below, hatching showing a cross section is partially omitted.

1. First Example In a first example, an example of a wafer having the PHS structure of the present invention will be described. FIG. 1 is a sectional view for explaining the first embodiment.

In the first embodiment, the wafer 4 having a PHS (plated heat sink) structure, which is the base of the semiconductor element, is used.
0, a lower metal layer 46 is provided over the entire surface of the wafer 40 on the back surface side of the main surface 44 on which the elements (not shown) are provided in the thinned semiconductor substrate 42 constituting the wafer 40. In this embodiment, the via hole 48
The semiconductor substrate 42 portion on the scribe line 50 is removed, and the lower metal layer 46 is also provided on the removed portions 48 and 50.

The thickness of the lower metal layer 46 is such that the wafer 40 can be handled and the wafer 40 can be easily cut at the time of chip separation. In this embodiment, the current film 52 for forming the lower metal layer 46 by the plating method is provided.

On the non-scribe line area of the lower metal layer 46, the upper metal layer 5 as a heat sink is formed.
It has 4. Therefore, the wafer in the scribe line 50 portion is held by the current film 52 and the lower metal layer 46.

2. Second Example In a second example, an example of a method of manufacturing a wafer having a PHS structure of the present invention will be described.

FIGS. 2A to 2C are sectional process diagrams of the first half for explaining the second embodiment. (A) of FIG.
FIG. 3C is a sectional process drawing of the latter half of FIG. 2C.

In the second embodiment, when manufacturing a wafer as a base of semiconductor elements, first, the GaAs semiconductor substrate 42 is provided with a quartz support material 56 on the side of the main surface 44 on which the functional elements (not shown) are provided. Then, it is attached using the attaching material 58. As the attaching material 58, a suitable wafer attaching wax may be used. Next, the back surface side of the main surface 44 of the semiconductor substrate 42 is lapped by using a polishing machine to thin the semiconductor substrate 42 to a thickness of 30 to 100 μm ((A) of FIG. 2).

Next, in this embodiment, a resist pattern (not shown) having an opening on the region where the via hole 48 is to be formed and on the scribe line 50 is formed on the semiconductor substrate 42, and this resist pattern is used as an etching mask. Then, etching is performed by a reactive ion etching (RIE) method or the like to remove the semiconductor substrate 42 portion on the via hole 48 and the scribe line 50 ((B) of FIG. 2).

Next, titanium (Ti) and gold (Au) are sequentially formed as the current film 52 over the entire rear surface side of the main surface 44 of the semiconductor substrate 42 including the via holes 48 and the scribe lines 50. . In forming the current film 52, a conventionally well-known metal thin film forming method such as a vapor deposition method may be used, and the thickness of the current film 52 may be determined by electrolytic plating described later.
The thickness may be selected so that the current density is uniform on the entire surface of the wafer 40. In this embodiment, the thickness is 500 A ° (A
° represents Angstrom) Ti layer (not shown)
And a layer of Au (not shown) with a thickness of 1000 A °.

Next, the current film 5 is formed over the entire rear surface of the main surface 44 of the thinned semiconductor substrate 42.
A lower metal layer 46 made of Au by plating on
To form. The thickness of the lower electrode layer 46 is set so that the wafer 40 can be handled and the wafer 40 can be easily cut at the time of chip separation.
The thickness is 0 μm ((C) in FIG. 2).

Next, a mask pattern 60 made of resist or polyimide is formed on the scribe line 50 of the lower electrode layer 46 by using the photolithography method.
The mask pattern 60 is made of, for example, aluminum (A
R) using O ₂ gas with the metal vapor deposition layer of 1) as a mask
It may be formed by the IE method (FIG. 3A).

Next, an upper metal layer 54 as a heat sink made of Au is formed on the lower metal layer 46 of the opening 62 of the mask pattern 60 by electroplating. In this embodiment, the thickness of the upper metal layer is set to 50 μm in order to effectively dissipate the heat generated in the semiconductor device to the package and the like.
m. Next, the mask pattern 60 is removed to remove the PHS.
The structure is obtained ((B) of FIG. 3).

Next, the wafer 40 having the PHS structure is peeled from the supporting material ((C) of FIG. 3).

3. Modified Example Next, a modified example of the second embodiment will be described. FIGS. 4A to 4C are cross-sectional process diagrams of a modified example following FIG. 2C. In this modification, the steps up to the step of forming the lower metal layer 46 are the same as those in the second embodiment, and therefore the description thereof will be omitted.

After forming the lower metal layer 46, in this modification, the applied resist is flattened, and after patterning the resist, the resist is etched to etch the semiconductor substrate on the scribe line. The mask pattern 60a remains and is formed only on the removed portion (FIG. 4).
(A)).

Next, the opening 62 of the mask pattern 60a.
On the lower metal layer 46 of a, in the same manner as in the second embodiment, A
An upper metal layer 54a as a heat sink made of u is formed. Next, the mask pattern 60a is removed to remove the PHS.
A structure is obtained ((B) of FIG. 4).

Next, the wafer 40a having the PHS structure is formed.
Is separated from the support material ((C) of FIG. 4).

In each of the above-described embodiments, the present invention is described by using the specific material and manufactured under the specific conditions. However, the present invention can be modified and modified in many ways. For example, in the above-described embodiment, the upper metal layer is provided on the entire surface of the wafer except on the scribe line,
In the present invention, the upper metal layer may be provided only on at least a part of the non-scribe line region, for example, on the via hole.

The optimum value of the thickness of the upper metal layer depends on the type and thickness of the semiconductor substrate and the size of the device. For example, when the thickness of the GaAs substrate is thinner than 30 μm, the thickness of the upper metal layer may be thinner than 50 μm.

[0041]

According to the wafer having the PHS structure and the method of manufacturing the same of the present invention, the entire surface of the wafer is
A lower metal layer is provided that also serves as a heat sink and a stiffener that enables wafer handling. The lower metal layer has a thickness that allows handling and facilitates cutting of the wafer during chip separation. Then, an upper metal layer as a heat sink is provided in at least a part of the region excluding the scribe line to effectively dissipate the heat. Therefore, without compromising the effective dissipation of heat,
PHS that can be handled and easily cut
A structured wafer can be obtained.

Further, the present invention is suitable for use in, for example, a wafer including a compound semiconductor substrate which has low thermal conductivity and high brittleness.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2A to FIG. 2C are sectional process drawings of the first half provided for explaining the second embodiment of the present invention.

3A to 3C are cross-sectional process diagrams of the second half following FIG. 2C.

4A to 4C are sectional process diagrams of a modified example following FIG. 2C.

FIG. 5 is a partial cross-sectional perspective view for explaining a conventional semiconductor device having a PHS structure.

6A to 6C are cross-sectional process charts for explaining a method for manufacturing a wafer having a conventional PHS structure.

FIG. 7A is a sectional process diagram following FIG. 6C. FIG. 6B is a cross-sectional view when the substrate portion on the scribe line is not removed.

[Explanation of symbols]

 10: Wafer 12: Semiconductor substrate (substrate) 14: Functional element (element) 16: Main surface 18: Metal layer 20: Via hole 22: Support material 24: Attachment material 26: Scribing line 28: Current film 30: Plating layer 32: dicing tape 40: wafer 42: semiconductor substrate 44: main surface 46: lower metal layer 48: via hole 50: scribe line 52: current film 54: upper metal layer 56: support material 58: adhesive material 60, 60a: Mask pattern 62, 62a: opening

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 29/41 H01L 23/36 Z 8826-4M 29/44 B

Claims (2)

[Claims] 1. A PHS (plating) which is a base of a semiconductor device.
In a wafer having an ed heat sink) structure, a lower metal layer is provided over the entire surface of the wafer on the back surface side of the main surface on which the elements are provided in the thinned semiconductor substrate that constitutes the wafer, and the thickness of the lower metal layer. The thickness of the wafer such that the wafer can be handled and the wafer can be easily cut during chip separation, and the upper metal as a heat sink is provided on at least a part of the non-scribe line region of the lower metal layer. A structure of a wafer having a PHS structure, characterized in that it comprises a layer. 2. A step of thinning a semiconductor substrate in which a main surface side provided with a functional element is attached to a supporting material in manufacturing a wafer as a base of a semiconductor element, and the main step of thinning the semiconductor substrate. A step of forming a lower metal layer having a thickness that enables handling of the wafer and facilitates cutting of the wafer at the time of chip separation over the entire surface on the back surface side of the front surface, and non-scribing of the lower metal layer. A step of forming an upper metal layer as a heat sink on at least a part of the line region, and a method of manufacturing a wafer having a PHS structure.