JPH06244437A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To prevent a wafer from damage during probing. CONSTITUTION:Probe regions 48 and 50 are adjacent to each chip area 44 for one integrated circuit 46. Objects 64 and 66 of probing on the surface of the chip area 44 are connected with intermediate terminals 52 and 54 on the probe regions 48 and 50. The intermediate terminals are connected through via holes 60 and 62 to probe terminals 56 and 58 on the reverse side of the probe regions 48 and 50. According to this arrangement, it is possible, with a reinforcing member attached to the front surface of a wafer, to connect the objects 64 and 66 to the probe through probe terminals 56 and 58 on the reverse side.

Description

Detailed Description of the Invention

[0001]

This invention relates to the structure of semiconductor wafers.

[0002]

2. Description of the Related Art When manufacturing a monolithic microwave IC or a power device using a compound semiconductor such as GaAs, after the fabrication process of the front side structure of a semiconductor wafer is completed,
A method is widely adopted in which the semiconductor wafer is polished from the back side to be thin, thereby reducing the thermal resistance of the semiconductor wafer. In addition to this, a via hole penetrating the semiconductor wafer is provided to connect the integrated circuit element on the front side of the wafer to the ground terminal on the back side of the wafer through this via hole, thereby further reducing the thermal resistance and reducing the ground inductance. Reduction methods are also often used. In the manufacturing process of such a wafer backside structure, first, the front side of the semiconductor wafer is attached to a support material such as a sapphire plate or a glass plate via a wax or a resin. After that, the semiconductor wafer is thinned by polishing or grinding from the back side. As a standard, the semiconductor wafer is thinned to a thickness of about 20 to 100 μm. Next, via holes are formed in the semiconductor wafer using photolithography and etching techniques. Next, a metal layer as a ground terminal is formed on the backside of the wafer by vapor deposition, sputtering or electrolytic plating, and the process for producing the backside structure of the wafer is completed.

FIG. 6 is a plan view and a cross-sectional view schematically showing the structure of a main part of a semiconductor wafer which has completed the manufacturing process of the back side structure. FIG. 6B shows a cross section taken along line VIB-VIB of FIG.

A semiconductor wafer 10 shown in FIG. 1 includes a semiconductor substrate 12, FETs 14 and 16 and pads 18 and 20 provided on the front side of the substrate 12, a ground terminal 22 provided on the back side of the substrate 12, and a via hole penetrating the substrate 12. 24 and 26 are provided. The FET 14 includes an active layer 28, a source electrode 30, a gate electrode 32, and a drain electrode 34 provided on the active layer 28.
FET 16 has active layer 29 and active layer 2
9 has a drain electrode 34, a gate electrode 36, and a source electrode 38. These FETs 14 and 16 have a common drain electrode 34. Further, the gate electrodes 32 and 36 are connected to the common gate pad 18, and the drain electrode 34 is connected to the drain pad 20. And board 1
2 The source electrodes 30 and 38 on the front side are connected to the ground terminal 22 on the back side of the substrate 12 via the via holes 24 and 26.

As described above, in the process of manufacturing the back side structure, bonding the semiconductor wafer to the support material is
(1) Preventing the semiconductor wafer from being damaged by impact during the polishing or grinding of the semiconductor wafer and the steps thereafter.
(2) Since the semiconductor wafer is less likely to be damaged, it can be easily handled and an automatic transfer type wafer processing apparatus can be used. (3) The thinned semiconductor wafer is prevented from warping (for example, 3 inches). A GaAs wafer having a diameter of several millimeters will be warped if not bonded together. (4) It has the advantage of being able to uniformly heat or cool the entire wafer during heating or cooling. It is an indispensable means when handling wafers.

When the manufacturing process of the backside structure of the wafer is completed, the inside of the wafer is probed with an automatic prober in order to evaluate the device characteristics. Generally, since the mounting terminals formed on the front surface of the wafer are generally used as probe terminals,
In probing, the front surface of the wafer is peeled off from the support, and wax or resin is removed from the wafer by organic cleaning, and then probing is performed.

Since thinned semiconductor wafers are extremely fragile,
While the wafer is still attached to the support material, it is divided into several pieces by dicing (there may be at least chip-divided), and then the support material is peeled off from the wafer. To prevent. Alternatively, after peeling the support material from the wafer, the back side of the wafer is attached to the conductive support material with a conductive adhesive agent, and probing is performed in the state of being adhered, whereby the wafer is vacuum-sucked or handled during probing. Prevent it from being damaged.

[0008]

However, although dividing the semiconductor wafer before peeling it from the support material secures strength by reducing the area of the wafer, in the end, the divided individual wafers are separated. There is a new problem that the relative positions are easily confused after the wafer is peeled off, and the number of probing steps is increased by the number of divided wafers. Therefore, in order to perform probing efficiently, it is desirable to divide the wafer as little as possible. However, to prevent damage to extremely brittle semiconductor wafers,
There is no choice but to divide the wafer.

In order to solve the above-mentioned conventional problems, an object of the present invention is to provide a semiconductor wafer capable of probing from the backside of a wafer with a supporting material for reinforcement attached to the front side of the wafer. To do.

[0010]

In order to achieve this object, a semiconductor wafer of the present invention comprises a substrate, a plurality of chip regions provided on the substrate, and an integrated circuit provided in the chip region, and further comprises a chip. A probe region provided adjacent to the region, a relay terminal provided on the substrate front side of the probe region, a probe terminal provided on the substrate back side of the probe region, and a via hole penetrating the substrate of the probe region, the chip region The integrated circuit element to be probed on the front surface side of the substrate is connected to the probe terminal through the relay terminal and the via hole in the probe region.

[0011]

According to this structure, the main circuit elements of the integrated circuit, for example, active elements, passive elements, pads or wirings are provided on the front side of the substrate in the chip area. A probe region is provided adjacent to the chip region, and a relay terminal, a via hole, and a probe terminal are provided in the probe region. The relay terminal is provided on the front side of the substrate, the probe terminal is provided on the back side of the substrate, and the via hole is provided through the substrate in the probe region. Then, the integrated circuit element to be probed on the front side of the substrate in the chip region is connected to the relay terminal on the front side of the substrate in the probe region and the probe terminal on the back side of the substrate through the via hole penetrating the substrate.

Therefore, even when the front side of the substrate is bonded to the support member, the probe and the probing target can be electrically connected by bringing the probe (probe) into contact with the probe terminal on the back side of the substrate.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings are merely schematic representations so that the present invention can be understood, and therefore the present invention is not limited to the illustrated examples.

1 (A) and 1 (B) are a plan view and a cross-sectional view schematically showing the structure of a main part of an embodiment of the present invention.
FIG. 1B shows a cross section taken along line IB-IB in FIG. FIG. 2 is a bottom view schematically showing the configuration of the main part of the embodiment of the present invention.

The semiconductor wafer 40 of this embodiment is a substrate 42.
And a chip area 44 provided on the substrate 42 and a chip area 4
4, the semiconductor wafer 40 further includes probe regions 48 and 50 provided adjacent to the chip region 44, and relay terminals 52 and 54 provided on the substrate front side of the probe regions 48 and 50. The probe terminals 56 and 58 provided on the back side of the substrate of the probe regions 48 and 50, and the via hole 6 penetrating the substrate 42 of the probe regions 48 and 50.
0 and 62. Then, integrated circuit elements (hereinafter referred to as probing elements) 64 and 66 to be probed on the front side of the substrate of the chip area 44 are connected to the probe areas 48 and 5.
No. 0 relay terminals 52 and 54 and via holes 60 and 62 are connected to the probe terminals 56 and 58.

In this embodiment, the substrate 42 is a GaAs substrate, and the substrate 42 is provided with a chip region 44 and a plurality of other chip regions 44 (not shown).
An integrated circuit 46 for one chip is formed on the substrate. Integrated circuit 46
The MMIC (M onolithic M icrowave I ntegrated C ircui
t).

The integrated circuit 46 includes FETs 68, 70, a probing element 64, which are provided on the front surface side of the substrate in the chip region 44.
66, capacitors, resistors, wirings and other circuit components not shown, via holes 72 and 74 penetrating the substrate 42 in the chip region 44, and the chip region 44.
And a ground terminal 76 provided on the back side of the substrate.

The FET 68 has an active layer 78 and a source electrode 80, a gate electrode 82 and a drain electrode 84 provided on the active layer 78, and the FET 70 has an active layer 79 and a drain electrode 84 and a gate electrode 86 provided on the active layer 79. And a source electrode 88. These FETs 68 and 70 have a common drain electrode 84. Probing element 6
A gate pad 4 connects the gate electrodes 82 and 86 with the probing element 64 common to them. The probing element 66 is a drain pad and connects the drain electrode 84 to the probing element 66. The source electrodes 80 and 88 on the front side of the substrate are connected to the ground terminal 76 on the back side of the substrate via the via holes 72 and 74.

Then, probe regions 48 and 50 are provided for some or all of the plurality of chip regions 44. The planar shapes of the chip area 44 and the probe areas 48 and 50 are rectangular.

The probe area 48 corresponds to the corresponding chip area 4
4 is provided adjacent to one side on the probing element 64 side. Further, the relay terminal 52 and the probe terminal 56 are provided on the front side and the back side of the substrate in the probe region 48, and the via hole 60 is provided by penetrating the substrate 42 in the probe region 48. Then, the probing element 64 is connected to the relay terminal 52 on the front side of the substrate, and the relay terminal 52 is connected to the probe terminal 56 on the back side of the substrate via the via hole 60.

The probe region 50 is provided adjacent to the other side of the corresponding chip region 44 on the probing element 66 side. Further, a relay terminal 54 and a probe terminal 58 are provided on the substrate front side and the substrate back side of the probe region 50, and the substrate 42 of the probe region 50 is penetrated to form a via hole 62.
To provide. Then, the probing element 66 is connected to the relay terminal 54 on the front side of the substrate, and the relay terminal 54 is connected to the probe terminal 58 on the back side of the substrate via the via hole 62.
Ground terminal 76, probe terminals 56 and 58 on the back side of the substrate
Are electrically separated from each other.

3 to 5 are sectional views showing stepwise a backside manufacturing process of the semiconductor wafer of this embodiment, and these drawings show sections corresponding to the section shown in FIG. 1 (B).

First, the elements to be formed on the front surface side of the semiconductor wafer 40, here, the FETs 68 and 70, the probing elements 64 and 66, which are provided on the front surface side of the chip region 44, the capacitors (not shown), resistors, wirings and other integrated circuit configurations. Elements, a relay terminal 52 provided on the substrate front side of the probe region 48, and a relay terminal 54 provided on the substrate front side of the probe region 50 are formed (FIG. 3A). In a later step, the via holes 60, 62 of the probe regions 48, 50 are formed at the positions corresponding to the relay terminals 52, 54. The planar shape of these relay terminals 52, 54 is defined by the front surface end of the via holes 60, 62. These relay terminals 52 and 54 are formed so as to be larger than the opening diameter of the portion. Similarly, in the subsequent process, the source electrodes 8 of the FETs 68 and 70 are formed.
Via holes 72 and 74 of the chip region 44 are formed at positions corresponding to 0 and 88, respectively, and these source electrodes 80 and 8 are formed.
These source electrodes 80 and 88 are formed so that the planar shape of 8 is larger than the opening diameter of the via hole 72 and 74 at the front end of the substrate.

Next, a supporting material 90 for reinforcement is attached to the front side of the substrate 42 via an attaching material 92. The support material 90 is a sapphire plate or a glass plate, and the adhesive material 92 is a wax or a resin (FIG. 3 (B)).

Next, the back side of the substrate 42 is polished or ground to thin the substrate 42 (FIG. 4A). When the thickness of the substrate 42 reaches a predetermined thickness, polishing or grinding is completed.

Next, using photolithography and etching techniques, via holes 60 and 62 penetrating the substrate 42 in the probe regions 48 and 50 and via holes 72 and 74 penetrating the substrate 42 in the chip region 44 (see FIG. And (see FIG. 4B). These via holes are formed by partially etching away the substrate 42 from the back side to the front side of the substrate 42, exposing the relay terminals 52, 54 through the via holes 60, 62 of the probe regions 48, 50, and the chip region. 44 via holes 72, 74
The source electrodes 80 and 88 are exposed through. In plan view, the via holes 72, 74 in the chip region 44 and the active layers 78, 79 are prevented from overlapping each other.

Next, the probe terminals 56 and 58 are formed on the substrate rear sides of the probe regions 48 and 50 and the ground terminal 76 is formed on the substrate rear side of the chip region 44 by vapor deposition, sputtering or electrolytic plating. 5), the manufacturing process of the wafer backside structure is completed, and the semiconductor wafer 40 having the structure shown in FIG. 1 is obtained. A metal layer made of gold is formed as the probe terminals 56 and 58 and the ground terminal 76.

As can be understood from the above description, in the process for manufacturing the front side and the back side of the semiconductor wafer 40 of this embodiment, only the design of the pattern shape of the mask used in the conventional semiconductor wafer is changed, and other processes are performed in the conventional method. Can be done in the same way as. Therefore, the semiconductor wafer 40 of this embodiment has an advantage that it does not complicate the manufacturing process.

After the wafer backside structure manufacturing process is completed, the probe terminal 56 on the backside of the substrate is used as a probe (probe) for the gate electrodes 82 and 86 on the frontside of the substrate even if the support material 90 is still attached. The gate voltage can be supplied by bringing them into contact with each other, and the drain voltage can be supplied to the drain electrode 84 on the front side of the substrate by bringing the probe terminal 58 on the back side of the substrate into contact with the probe, and further to the source electrodes 80, 88 on the front side of the substrate. In other words, it can be grounded by bringing the ground terminal 76 on the back side of the substrate into contact with the probe. Therefore, the probing (here, the inspection of the operating characteristics of the FETs 72 and 74) can be performed with the support material 90 attached to the front surface of the substrate, and as a result, the semiconductor wafer 40 can be effectively prevented from being damaged during the probing. In addition, the working efficiency of probing can be improved more than ever before.
When performing the probing, the probing may be performed in a state where the semiconductor wafer 40 is not divided at all. Alternatively, the supporting member 90 may be attached to the semiconductor wafer 40 and the probing may be performed after the division is performed to some extent. You may do it.

Based on the result of probing, the quality of each integrated circuit 46 in the semiconductor wafer 40 and the grade of quality can be judged, or the non-defective product distribution and the quality distribution of the integrated circuit 46 in the wafer 40 can be known. Therefore, since the semiconductor wafer 40 can be divided into individual chips and further the individual chips can be sorted in a state where the non-defective products and the quality distribution are known in advance, the work efficiency of the division and the sorting can be improved.

After the probing is completed, the semiconductor wafer 40 is diced or scribed using the boundary between the chip region 44 and the probe regions 48, 50 as a scrub line to obtain individual chips. Probe area 4
Since the relay terminals 52 and 54, the probe terminals 56 and 58, and the via holes 60 and 62 formed in 8, 50 are finally separated from the integrated circuit 46 in the chip area 44,
Each element of these probe regions 48 and 50 is integrated circuit 46.
The effect on the electrical characteristics of can be ignored.

The present invention is not limited to the above-mentioned embodiment, and therefore, the shape of each component, the arrangement position,
The number of arranged elements, dimensions, forming method, forming material, wiring method, and other conditions can be arbitrarily changed.

For example, in the above-described embodiment, the integrated circuit circuit element (probing element) to be probing is F
Although it has been described as the gate pad and drain pad of the ET, the probing element may be a resistor, a capacitor, other passive elements, a part of an active element other than the FET, or a wiring. At this time, it is preferable to provide a probe terminal for each value or type of the applied potential, and connect the probing element to which the common potential is applied to the common probing terminal.

As a method of connecting the relay terminal in the probe area and the probing element in the chip area, various wiring techniques known in the art other than multilayer wiring may be used. Further, the integrated circuit in the chip area may be a circuit other than the MMIC.

[0035]

As is apparent from the above description, according to the semiconductor wafer of the present invention, the probing element on the substrate front side of the chip area (integrated circuit element to be probing) is relayed to the substrate front side of the probe area. The probe terminal on the back side of the substrate is connected through a via hole penetrating the terminal and the substrate.

Therefore, the back side of the substrate is processed while the front side of the substrate is bonded to the supporting material, and then the probing can be performed in the bonded state without peeling off the supporting material. It is possible to prevent the wafer from being damaged. In addition, since it is not necessary to divide the semiconductor wafer into smaller areas to prevent damage during probing, or to reduce the size to the conventional size even if the semiconductor wafer is divided, probing is much easier than before. The number of steps can be reduced, and thus the probing work efficiency can be increased.

Further, since the probe area is provided adjacent to the chip area, and the relay terminal, the via hole and the probe terminal are provided in the probe area, when the integrated circuit in the chip area is divided into individual chips after the completion of probing, each chip is divided into chips. And the probe region can be separated. Therefore, after the semiconductor wafer is divided into individual chips, the influence of the relay terminals, via holes, and probe terminals in the probe region on the operating characteristics of the individual chips can be ignored.

[Brief description of drawings]

1 (A) and 1 (B) are a plan view and a cross-sectional view schematically showing a main part configuration of an embodiment of the present invention.

FIG. 2 is a bottom view schematically showing a main part configuration of an embodiment of the present invention.

3 (A) and 3 (B) are cross-sectional views of the essential part schematically showing the backside manufacturing process of the semiconductor wafer of the example.

4A and 4B are cross-sectional views of a main part schematically showing a backside manufacturing process of the semiconductor wafer of the example.

FIG. 5 is a main-portion cross-sectional view schematically showing the backside manufacturing process of the semiconductor wafer of the example.

6 (A) and 6 (B) are a plan view and a cross-sectional view schematically showing a configuration of a main part of a conventional semiconductor wafer.

[Explanation of symbols]

 40: Semiconductor wafer 42: Substrate 44: Chip area 46: Integrated circuit 48, 50: Probe area 52, 54: Relay terminal 56, 58: Probe terminal 60, 62: Via hole 64, 66: Integrated circuit element to be probed

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 E 8427-4M 21/338 29/812

Claims (2)

[Claims] 1. A semiconductor wafer comprising a substrate, a plurality of chip regions provided on the substrate, and an integrated circuit provided on the chip region, a probe region provided adjacent to the chip region, and the probe. An integrated circuit to be probed on the front side of the substrate in the chip area, including a relay terminal provided on the front side of the substrate in the area, a probe terminal provided on the back side of the substrate in the probe area, and a via hole penetrating the substrate in the probe area. A semiconductor wafer comprising: an element connected to a probe terminal through a relay terminal and a via hole in the probe region. 2. The integrated circuit has an FET provided on the front side of the substrate, a ground terminal provided on the back side of the substrate, and a via hole penetrating the substrate in the chip region, and a source electrode of the FET via the via hole in the chip region. 2. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is connected to a ground terminal, and the drain pad and the gate pad of the FET are elements for probing an integrated circuit.