JPH07321343A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable micromachining of via holes, reduce parasitic capacitance of transistors and wires, and form substrates with thin films with excellent reproducibility. CONSTITUTION:A first AlGaAs etching stopper layer 2, a GaAs middle layer 3, a second AlGaAs etching stopper layer 4, and an active layer 5, are formed on a GaAs sunbstrate 1 in this order. A MESFET 6 having a gate electrode 8 and source/drain electrodes 7, 9 is formed thereon. A quartz plate 10 is bonded to its element formation surface, and the substrate 1 is removed by polishing and etching. The etching stopper layer 2 and the middle layer 3 are selectively etched to form the larger-diameter section 12 of a via hole. The second etching stopper layer 4 and the active layer 5 are selectively etched to form the smaller- diameter section of the via hole. A back electrode 14 is formed, and the quartz plate 10 is stripped off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, a heat-generating element is formed on a compound semiconductor having a low thermal conductivity, and heat emitted from the element is formed on the back surface of the substrate. It was made to dissipate from the back electrode,
The present invention relates to a semiconductor device having a so-called PHS (Plated Heat Sink) structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, GaAs having particularly poor thermal conductivity
In such compound semiconductors, the semiconductor substrate has been thinned and a back electrode (ground electrode) has been formed on the back surface of the substrate in order to improve the heat dissipation of the semiconductor element formed on the front surface of the semiconductor substrate. In addition, as a method of grounding the source, the method of forming a via hole under the source electrode and directly grounding the source electrode by this method has lower wiring resistance and inductance than other grounding methods, so high frequency characteristics are important. It is adopted when it is done. When this via-hole connection system is adopted, the thinning of the substrate is also necessary for making the via-holes finer and improving the coverage with the via-holes.

FIG. 4 is a sectional view of a conventional semiconductor device of this type. As shown in the figure, an active layer 5 made of GaAs is formed on a GaAs substrate 1, and a gate electrode 8 that forms a Schottky junction with the active layer 5 is formed on the active layer.
And a source electrode 7 and a drain electrode 9 which are in ohmic contact with the source electrode 7 and the drain electrode 9.
T (Metal Semiconductor Field Effect Transistor) 6
Are formed. Below the source electrode 7, a via hole 13a penetrating the GaAs substrate 1 and the active layer 5 is provided, and the source electrode 7 is connected to the back surface electrode 14 by a conductor embedded in the via hole.

The semiconductor device shown in FIG. 4 is formed as follows. The GaAs substrate 1 has a thickness of, for example, about 600 μm in the case of a 3 ″ φ wafer in order to prevent the occurrence of defects such as substrate cracks during device formation. The active layer 5 is epitaxially grown on this substrate. The gate electrode 8 is made of a material that forms a Schottky junction, and then the source electrode 7 and the drain electrode 9 are made of a material that makes ohmic contact.
Are formed by the lift-off method.

Next, the back surface of the GaAs substrate 1 is polished to a thickness of about 100 μm. Next, the back surface of the substrate is etched to a thickness of 10 to 40 μm, and the GaAs substrate 1 and the active layer 5 under the source electrode 7 are selectively etched to form a via hole 13a. Then, the back electrode 14 is formed by vapor deposition of a base metal layer and electrolytic plating.

In the semiconductor device formed as described above, since the in-plane uniformity in the polishing and etching processes on the back surface of the substrate is low, the variation in the substrate thickness becomes extremely large, for example, the thickness of the substrate. Variations in heat dissipation characteristics and in turn variations in element characteristics increase. In order to deal with this point, Japanese Patent Application Laid-Open No. 61-168966 proposes a method in which an etching stop layer is provided on a GaAs substrate and an active layer is provided thereon.

That is, as shown in FIG. 5, an etching stopper layer 2a made of AlGaAs is formed on a GaAs substrate 1, and an active layer 5 is formed thereon. Then, a transistor is formed on the active layer 5, and the GaAs substrate 1 or the GaAs substrate and the etching stop layer 2a are removed by polishing and etching. According to this method, the etching can be automatically stopped at the etching stop layer by utilizing the difference in etching rate between the GaAs substrate and the etching stop layer when the substrate is etched.
The film thickness of the remaining substrate can be accurately controlled.

Further, Japanese Patent Laid-Open No. 3-62930 discloses that
A technique has been proposed in which an etching stopper layer is provided between a GaAs substrate and an active layer, and a via hole is formed from the substrate surface side. In this conventional example, after the epitaxial substrate is formed as shown in FIG. 5, M is formed on the active layer as shown in FIG.
The ESFET 6 is formed. Then, selective etching is performed from the surface of the substrate using the etching stopper layer 2a as a stopper to form a via hole 13b. After forming the metal layer 15 in the via hole 13b, the substrate is etched again using the etching stopper layer 2a as a stopper to remove the ME.
The back surface side of the etching stop layer 2a under the SFET 6 is exposed, then the etching stop layer in this portion is removed by etching, and the back surface electrode 14 is formed by a conventional method.

[0009]

In recent years, there has been a demand for miniaturization of MESFETs in accordance with the tendency of applied devices to be lighter, shorter and thinner. Therefore, in the MESFET adopting the via-hole connection method, it is an essential requirement to reduce the thickness of the substrate in order to miniaturize the device. If the board is thick,
For example, when a via hole is formed by a wet method, the lateral spread of the opening becomes large and a large margin must be taken, so that the source electrode has to be made large. This is because when the via hole is formed by the method, the aspect ratio becomes high and the coverage is deteriorated, so that a void is generated in the via hole.

On the other hand, regarding the substrate thickness of the transistor formation region excluding the source electrode formation portion, the thinner the substrate, the more advantageous it is. However, when the film is thinned over a wide area, the strength of the substrate is lowered and the semiconductor element portion is cracked, and the ground capacitance of the transistor is increased to hinder high-speed operation. Especially MMIC
In (Monolithic Microwave IC), the characteristic is significantly deteriorated due to the influence of the increase of the parasitic capacitance of the wiring. Therefore, it is desirable that the substrate thickness be different between the via hole portion and the other active regions, but the above-described conventional example in which the etching stop layer is provided below the active layer cannot meet this demand. .

The present invention has been made in view of this point, and an object of the present invention is to obtain uniform substrate thickness,
In addition to ensuring reproducibility, the substrate thickness in the via hole part and the substrate thickness in other regions can be controlled independently to make the via hole finer, improve the mechanical strength of the substrate, and reduce the parasitic capacitance. It is to be able to achieve reductions at the same time. Thus, it is intended to make it possible to manufacture a small-sized semiconductor device having excellent high frequency characteristics with good reproducibility.

[0012]

In order to achieve the above object, according to the present invention, a transistor (6) having a source electrode (7), a drain electrode (9) and a gate electrode (8) on the surface thereof is formed. An active layer (5) having a small diameter via hole (13) formed under the source electrode, and a second etching formed under the active layer and having a small diameter via hole at the same position as the active layer. A blocking layer (4), a semiconductor intermediate layer (3) formed under the second etching blocking layer and having a large diameter via hole (12) formed under the source electrode, and a semiconductor intermediate layer under the semiconductor intermediate layer. A first etching stop layer (2) formed and having a large-diameter via hole formed at the same position as the semiconductor intermediate layer, and at least a region below the transistor on the lower surface of the first etching stop layer. Formed on A semiconductor device having a back electrode (14) connected to the source electrode via the small-diameter via holes and via holes of the large diameter, is provided.

Further, according to the present invention, (a) a first etching stop layer (2), a semiconductor intermediate layer (3), a second etching stop layer (4) and an active layer on a semiconductor substrate (1). (5) sequentially growing step, (b) forming a transistor (6) by forming a gate electrode (8), a source electrode (7) and a drain electrode (9) on the active layer, and (b) c) etching using the first etching stop layer as a stopper to remove at least the semiconductor substrate under the transistor; and (d) the first etching stop layer under the source electrode and the semiconductor intermediate layer. Is selectively removed to form a large diameter via hole (12) exposing the lower surface of the second etching stop layer, and (e) the second etching stop layer under the source electrode and By selectively removing the serial active layer small diameter via hole exposing a lower surface of the source electrode (1
3) and (f) a back surface electrode (14) connected to the source electrode through the large diameter via hole and the small diameter via hole on the lower surface of the first etching stop layer. And a method of manufacturing a semiconductor device having a step of forming.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. As shown in the figure, the semiconductor substrate has a first etching stopper layer 2 of Al _0.4 Ga _0.6 As with a film thickness of 1 μm, a GaAs intermediate layer 3 with a film thickness of 30 μm, and a film thickness of 0 with Al _0.2 Ga _0.8 As. It is formed by four semiconductor layers, that is, the second etching stopper layer 4 having a thickness of 0.5 μm and the active layer 5 having a thickness of 0.5 μm and made of GaAs. A gate electrode 8 that forms a Schottky junction with the active layer 5 and a source electrode 7 and a drain electrode 9 that are in ohmic contact with the active layer are formed on the active layer 5, and a MESFET 6 is formed there. A via hole having a large diameter portion 12 of 30 μmφ and a small diameter portion 13 of 5 μmφ is formed under the source electrode 7, and a back surface connected to the source electrode 7 through the via hole (12, 13) on the back surface of the substrate. The electrode 14 is formed.

In the semiconductor device having such a structure, the substrate thickness of the portion where the small diameter portion 13 of the via hole is formed and the substrate thickness of the other portion can be set independently, so that the via hole of the small diameter is formed. The thickness of the substrate (4, 5) in which the metal is formed can be made sufficiently thin to prevent the generation of voids during the formation of the metal film and realize the reduction of the diameter of the via hole. It is possible to select the thickness of the substrate in the region (1) so that the mechanical strength is not impaired and the parasitic capacitance does not significantly affect the characteristics. Therefore, according to the present embodiment, it becomes possible to manufacture a semiconductor device having a small size and excellent high frequency characteristics with high yield.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. Note that FIG.
(A)-(d) is process sectional drawing which showed the manufacturing method of the semiconductor device of 1st Example in order of process. First, FIG.
As shown in (a), GaAs having a thickness of 600 μm
MOCVD (Metal Organic Chemical Vapor) on substrate 1
Deposition method is used to form an Al _0.4 Ga _0.6 As layer as the first etching stop layer 2 to a thickness of 1.0 μm, and then GaAs is grown to a thickness of 30 μm to form GaA.
s Intermediate layer 3 is formed.

Further, after forming an Al _0.2 Ga _0.8 As layer with a thickness of 0.5 μm as the second etching stop layer 4, GaAs doped with Si as an n-type impurity to about 1 × 10 ¹⁷ cm ^−3. Is grown to a film thickness of 0.5 μm to form an active layer 5. Next, the gate electrode 8 is formed by vapor deposition and lift-off of the Schottky metal, and then the source electrode 7 and the drain electrode 9 are formed by vapor deposition and lift-off of the ohmic metal to manufacture the MESFET 6.

Next, as shown in FIG. 2B, the MESF
The quartz plate 1 is formed by using wax 11 on the surface on which ET6 is formed.
Paste it on 0. Then, the back surface of the GaAs substrate 1 is made to have a thickness of 80 μm by using a mechanical polishing method. After that, the substrate 1 is etched up to the first etching stop layer 2 using ammonia and hydrogen peroxide while the substrate 1 is attached to the quartz plate 10. Etching with a mixed solution of ammonia and hydrogen peroxide solution is slow in the Al _0.4 Ga _0.6 As layer having an Al composition ratio of 0.4, and is almost the same in the first etching stop layer 2 after etching the GaAs substrate 1. Stop.

Next, as shown in FIG. 2 (c), the first etching stop layer 2 is formed in the via hole forming region by 30 μm.
It is covered with an etching protection film having a φ opening and is plasma-etched using a chlorine compound gas to form Al _0.4 G.
The a _0.6 As layer (first etching stop layer 2) and then the GaAs intermediate layer 3 are selectively removed by plasma etching using a mixed gas of chlorine and a fluorine compound. To form. The etching at this time almost stops when the second etching stop layer 4 is exposed.

Next, as shown in FIG. 2D, the back surface of the substrate is covered with an etching protection film having an opening of 5 μmφ in a small-diameter via-hole forming region, and a plasma similar to the etching in the step of FIG. 2C is formed. The second etching stop layer 4 and the active layer 5 are selectively etched and removed by etching to form the small diameter portion 12 of the via hole exposing the back surface of the source electrode 7. After removing the etching protection film, Ti / Pt / Au is deposited on the entire back surface by sputtering, and Au is plated to a thickness of 50 μm on the entire back surface to form the back electrode 14.

Finally, the quartz plate 10 attached to the surface of the substrate
Is peeled off in heated trichloroethylene to obtain the semiconductor device having the PHS structure shown in FIG. In the above embodiment, the Al composition ratio of the first etching stop layer was made larger than that of the second etching stop layer because the first etching stop layer functions as an etching stopper for the thicker GaAs layer. Because it is, and also the second
This is because by suppressing the Al composition ratio of the etching stopper layer to be low, this layer can function as a buffer layer for the active layer.

FIG. 3 is a sectional view of a semiconductor device according to the second embodiment of the present invention. In the manufacturing process of the embodiment shown in FIG.
Etching is performed in the same manner as in the manufacturing method for the first embodiment shown in FIG. 2, but in the process of FIG.
After mechanically polishing the As substrate 1 to a thickness of 80 μm,
The structure is such that the thickness of the semiconductor substrate in the other regions is kept thick by etching away only the substrate in the region where the MESFET 6 and the via hole are formed without sticking to the quartz plate. In this embodiment, the GaAs substrate 1 is 80 μm.
Since it has a thickness of m, the electrode can be formed on the back surface of the substrate without being attached to the quartz plate. According to this embodiment, the heat generating FET portion and the via hole portion requiring fine processing can be thinned to secure heat dissipation and fine processing, and the ground capacitance of the wiring can be reduced. It becomes possible to construct an MMIC having excellent frequency characteristics.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made without departing from the scope of the present invention. For example, in the embodiment, the film formation of the semiconductor layer was performed by the MOCVD method, but instead of this, M
Other film forming techniques such as BE (Molecular Beam Epitaxy) can be used, and the etching method can be performed by using a gas other than the gas in the embodiment, and an etching method other than the plasma etching method can be adopted. You can also

[0024]

As described above, according to the present invention, the first etching stop layer, the semiconductor intermediate layer, the second etching stop layer and the active layer are formed on the semiconductor substrate and the semiconductor substrate is removed. Therefore, by using the first etching stop layer, the substrate of the heat-generating MESFET portion can be thinned independently to the extent that the strength of the substrate does not decrease and within the allowable range of the parasitic capacitance. Also, by providing the second etching stop layer, the portion such as a via hole that requires fine processing can be thinned to a thickness that can be fine processed independently of the thickness of the substrate in other regions. Becomes Therefore, according to the present invention, it is possible to provide a small-sized semiconductor device having excellent heat dissipation and high frequency characteristics, and it is possible to provide an advantageous means for manufacturing a high frequency, high output IC.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view for explaining the manufacturing method of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a first conventional example.

FIG. 5 is a sectional view of a semiconductor substrate for explaining a manufacturing method of a second conventional example.

FIG. 6 is a sectional view of a third conventional example.

[Explanation of symbols]

 1 GaAs Substrate 2 First Etching Blocking Layer 2a Etching Blocking Layer 3 GaAs Intermediate Layer 4 Second Etching Blocking Layer 5 Active Layer 6 MESFET 7 Source Electrode 8 Gate Electrode 9 Drain Electrode 10 Quartz Plate 11 Wax 12 Large Diameter of Via Hole Part 13 Small diameter part of via hole 13a, 13b Via hole 14 Back surface electrode 15 Metal layer

Claims (4)

[Claims] 1. An active layer in which a transistor having a source electrode, a drain electrode and a gate electrode is formed on a surface thereof, and a via hole having a small diameter is formed under the source electrode, and the active layer formed under the active layer. A second etching stop layer having a small-diameter via hole formed at the same position; and a semiconductor intermediate layer formed under the second etching stop layer and having a large-diameter via hole formed under the source electrode, A first etching stop layer formed under the semiconductor intermediate layer and having a large-diameter via hole formed at the same position as the semiconductor intermediate layer; and a region at least under the transistor on the lower surface of the first etching stop layer. And a back electrode connected to the source electrode through the small diameter via hole and the large diameter via hole. The semiconductor device according to. 2. A semiconductor substrate having an opening below the transistor is provided below the first etching stop layer,
The back surface electrode integrally formed with the back surface electrode formed on the back surface of the first etching stop layer below the transistor extends to the back surface of the semiconductor substrate. The semiconductor device described. 3. The active layer and the semiconductor intermediate layer are G
aAs, the first and second etching stop layers are formed of AlGaAs, and the Al composition ratio of the first etching stop layer is higher than that of the second etching stop layer. The semiconductor device according to claim 1. 4. A step of (1) sequentially growing a first etching stop layer, a semiconductor intermediate layer, a second etching stop layer and an active layer on a semiconductor substrate, and (2) a gate electrode on the active layer. Forming a transistor by forming a source electrode and a drain electrode; and (3) etching using the first etching stop layer as a stopper to remove at least the semiconductor substrate under the transistor, (4) Selectively removing the first etching stop layer and the semiconductor intermediate layer under the source electrode to form a large diameter via hole exposing the lower surface of the second etching stop layer; and (5). The second etching stop layer and the active layer under the source electrode are selectively removed to form a small diameter via hole exposing the lower surface of the source electrode. And (6) forming a back electrode connected to the source electrode through the large-diameter via hole and the small-diameter via hole on the lower surface of the first etching stop layer. A method of manufacturing a semiconductor device, comprising: