JPH02214127A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent this device from being chipped off and broken when it is handled by a method wherein a dicing region of a substrate is covered with a heat-dissipating electrode formed on the rear of the substrate in such a way that the region is wrapped. CONSTITUTION:A gate electrode 2, a source electrode 3 and a drain electrode 4 are provided respectively for a semiconductor element which is situated on a main face of a semiinsulating GaAs substrate 1 and is formed so as to occupy a prescribed position; a formation metal layer 5 is formed selectively in this dicing region; a plated substratum metal layer 12 for PHS formation use is formed on the rear side of the GaAs substrate 1. A PHS-plated heat-dissipating electrode 13 is provided via the plated substratum metal layer 12 in such a way that the GaAs substrate 1 is wrapped. When the dicing region of the substrate 1 is covered with the heat-dissipating electrode 13 so as to wrap the region, an end face of a chip is protected effectively by a coating by the heat- dissipating electrode 13. Thereby, it is possible to satisfactorily prevent the chip from being chipped off, broken and the like when the chip is handled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same. This invention relates to improvements in the chip structure and its manufacturing method.

(Prior art) Generally, in this type of GaAs-FET, gate electrodes, source electrodes, drain electrodes, etc. are provided in order to reduce thermal resistance and source inductance in the device configuration. The thickness of the semi-insulating GaAs substrate is made as thin as several tens of μm, and a through hole to the source electrode is formed from the back side of the substrate.
5ink (hereinafter also referred to as PH5) is installed and used.

FIG. 3 shows the general structure of such a conventional GaAs-FET, and FIGS. 4(a) to 4(f) show the main steps of its manufacturing method.

That is, in the conventional configuration shown in FIG. 3, reference numeral 1 indicates a semi-insulating GaAs substrate, 2, 3 . and 4 is this GaA
A gate electrode, a source electrode, and a drain electrode are respectively provided on the surface of the GaAs substrate l and occupy predetermined positions to form a semiconductor element, and 12 is a PH5 provided on the back side of the GaAs substrate l. A plating base metal layer 13 for formation is a heat dissipation electrode formed via this plating base metal layer 12.

However, in the conventional method, as shown in FIGS. 4(a) to 4(f), first, semi-insulating GaAs is
On the main surface of the substrate 1, a semiconductor element and its gate electrode 2. In addition to forming a source electrode 3 and a drain electrode 4 (FIG. 4(a)), this semiconductor element and GaA in the wafer state on which each electrode was formed
A glass substrate 6 is attached onto the s-substrate 1 using a pasting wax 7.
In this state, wrap the GaAs substrate from the substrate side to the desired thickness (about several tens of μm).
Then, the first resist pattern 8 is formed on the back surface of the thinned substrate (FIG. 4(b)).

Subsequently, using the first resist pattern 8 as a mask, the GaAs substrate 1 is etched to form a through hole 9 that reaches the source electrode 3 from the back side thereof (FIG. 3(C)). After removing the first resist pattern 8 used as a mask, a PIIS plating base metal layer 12 consisting of a gold layer and other metal layers is formed, and a second resist pattern is formed in a corresponding portion of a predetermined dicing area. 11 (see figure (d)).

Next, using the second resist pattern +1 as a mask, PHS plating is performed to form a heat dissipation electrode (PH5) 13 on the plating base metal layer 12.
)) Then, after removing the second resist pattern 11 used as a mask, this heat dissipation electrode 1 is removed.
3 as a mask, the plating base metal layer 12 is removed by etching (FIG. 1(f)).Next, although not shown in this process, the semi-insulating GaAs substrate 1 is etched as desired. The chips are divided, and in this way the device configuration shown in FIG. 3 is obtained.

[Problem to be solved by the invention]

As mentioned above, in manufacturing the conventional GaAs-FET, the heat dissipating electrode (PH5) 13 is used as a mask and the semi-insulating GaAs substrate l is etched to perform chip division. , the cross-sectional structure of the chip constructed in this way is the third
As is clear from the diagram configuration, GaA in the divided chip
The end surface of the s-substrate 1 has a sharply pointed shape, which has the disadvantage that the end surface of the substrate, that is, the end surface of the chip, is easily chipped during subsequent chip handling. When the GaAs substrate 13 is used as a mask, the finished shape of the heat dissipation electrode 13 and the shape after removing the plating base metal layer 12 are as follows.
The shape of the main surface of the substrate after chip division is increased, which tends to cause irregularities in the dimensions of the main surface of the substrate, over-etching, etc., resulting in a decrease in the yield of chip division. Since the top layer of the resist pattern is normally made of a gold layer, it tends to seep under the second resist pattern 11 for selective electrolytic plating, which tends to cause gold plating connections, making chip division difficult. There were problems such as.

This invention was made to solve these conventional problems, and that is the purpose.

The present invention has made it possible to provide chips with a high yield, with chip end faces that are difficult to miss and with good dimensional accuracy when handling chips. An object of the present invention is to provide a semiconductor device of this type and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention has a semiconductor element and its electrodes formed on the main surface of a substrate,
A semiconductor device in which a heat dissipation electrode is formed on the back side of the substrate via a base metal layer, characterized in that the heat dissipation electrode formed on the back surface of the substrate wraps and covers the dicing area of the substrate. It is something.

Further, the method for manufacturing a semiconductor device according to the present invention provides a method for manufacturing a semiconductor device in which a semiconductor element and its electrodes are formed on the main surface of the substrate, and a heat dissipation electrode is formed on the back surface side through a base metal layer. A process of selectively forming an easily etched metal layer on the surface corresponding to the dicing area, and lapping and etching the substrate in wafer form from the back side to thin the layer to a desired thickness. , and selectively forming a through hole reaching at least the metal layer corresponding to the dicing area, and forming a resist pattern on the back surface portion of the metal layer exposed by the through hole, and using the resist pattern as a mask. make use of,
a plating base metal layer on the back surface of the substrate including the inner surface of the through hole;
Next, the method includes at least a step of sequentially and selectively forming heat dissipation electrodes, and a step of sequentially and selectively etching the metal layer corresponding to the dicing area and the substrate after removing the resist pattern to divide into chips. It is characterized by this.

[Function] That is, in the present invention, in a semiconductor device in which a semiconductor element and its electrodes are formed on the main surface of the substrate, and a heat dissipation electrode is formed on the back surface side via a base metal layer, the heat dissipation formed on the back surface of the substrate is provided. Since the electrode covers the dicing area of the substrate, the heat dissipating electrode protects the chip end face and prevents chipping or cracking during handling. Therefore, an easily etched metal layer was formed on one main surface (front side), and this wafer-like substrate was thinned to the desired thickness by lapping and etching from the back side. selectively forming a through hole reaching at least the metal layer corresponding to the dicing area from the back side of the substrate, further forming a resist pattern on the back side of the metal layer exposed by the through hole, and Using this resist pattern as a mask, a plating base metal layer and then a heat dissipation electrode are formed on the back surface of the substrate including the inner surface of the through hole, so after removing the resist pattern, the metal layer corresponding to the dicing area and When dividing a substrate into chips by sequentially etching the substrate, the accuracy of forming through holes is higher than in conventional etching of a substrate using a heat dissipation electrode as a mask.

This not only improves the dimensional accuracy of the substrate itself after etching, but also eliminates the unbalance of etching within the eight surfaces of the urchin, and in combination with the wrapping of the back side of the substrate including the dicing area by the heat dissipation electrode, It becomes possible to make the chip dimensions uniform, and it is possible to achieve chip division with a high yield.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to FIGS. 1 and 2.

Figure 1 is a cross-sectional view schematically showing the outline of a GaAs-FET chip structure to which this embodiment is applied, and Figures 2 (a) to g) are sequential schematic diagrams showing the main manufacturing steps of the same chip structure. 1 and 2, the same reference numerals as in the conventional example shown in FIGS. 3 and 4 indicate the same or corresponding parts.

That is, in the embodiment configuration shown in FIG. 1, the symbol l indicates a semi-insulating GaAs substrate, 2, 3 . and 4 is this GaA
A gate electrode, a source electrode, and a drain electrode are respectively formed on the main surface of the substrate 1 occupying a predetermined position for the semiconductor element, and 5 is a gate electrode, a source electrode, and a drain electrode formed selectively in the dicing area of the same. 1.
2 is a PI(S) provided on the back side of the GaAs substrate l.
The plating base metal layer 13 for forming the plating base metal layer 13 is made of P so as to wrap around the GaAs substrate l via this plating base metal layer 12.
This is a heat dissipation electrode formed by HS plating.

Therefore, in this embodiment method, as shown in FIG. 2(a) or axis), first, semi-insulating GaA
A gate electrode 2, a source electrode 3, and a drain electrode 4 are formed on the main surface of the s-substrate l, occupying the desired positions (FIG. 2(a)), and this GaA
On the surface corresponding to the dicing area of the S substrate 1, a metal layer 5 of a highly conductive metal 1, such as gold, which can be easily removed by etching and also serves as a power supply layer for concave S plating to be described later, is deposited. Although not shown in the figure, for example, it is selectively formed by known means such as a vapor deposition method using a resist pattern as a mask and a lift-off method (see (b) in the same figure).
).

Then, each of these electrodes 2 to 4. A glass substrate 6 is pasted on the front side of the GaAs substrate 1 in a wafer state with the metal layer 5 formed thereon using wax 7 for pasting, and in this state, the GaAs substrate 1 is placed on the back side. Wrapping from to the desired thickness (approximately several tens of μm) indicated by the broken line.

and etching to make the layer thinner (Figure (C)
)) After that, a first resist pattern 8 is formed on the thinned GaAs substrate surface side, and using this as a mask, the GaAs substrate surface is subjected to a chipping process, and the source is exposed from the back surface side. Electrode 3. Then, each through hole 9a, 9b reaching the metal layer 5 corresponding to the dicing area is selectively formed, and again using the first resist pattern 8 as a mask, a metal such as Ti (titanium) is evaporated. Then, the vapor-deposited metal layers 10.10a and 10b are formed respectively (FIG. 4(d)).

Then, the first resist pattern 8 used for the mask is
At the same time, the vapor-deposited metal layer portion 10 thereon is lifted off and removed, and the part corresponding to the dicing area on the back surface of the metal layer 5 exposed in the through hole 9b is
Only on the selectively left deposited metal layer portion 10b is the PH
A second resist pattern 11 is formed to serve as a mask for the selective formation of S plating, and the vapor-deposited metal layer portion 10a on the source electrode gi3 passing through the through hole 9a is removed by appropriate etching (see FIG. e)) Then, electroless plating (for example, Ni, Au, etc.) is performed to
A vapor deposited metal layer portion t covered with a resist pattern 11 of
Ga including the inner surface of each through hole 9a, 9b except for ab
PHS plating base metal layer 1 on the entire surface of the As substrate l
2 is formed, and then PHS plating is performed on this plating base metal layer 12 by electrolytic plating using the metal layer 5 as a power supply layer to form a heat dissipation electrode (P) 13 (
Figure (f)).

Then, after removing the second resist pattern +1 used as the mask, using the heat dissipation electrode 13 as a mask, the vapor deposited metal layer portion 10b corresponding to the dicing area and the metal layer 5 are sequentially removed by etching. Figure (g))
, Subsequently, although not shown in this S, the semi-insulating Ga
The As substrate 1 is etched as planned to divide the chips into chips, and then each of the 9-divided chips is placed on a glass substrate 6.
In this way, the device structure shown in FIG. 3 is obtained.

Therefore, in the case of this embodiment, one main surface (front surface) is included in the dicing area where the GaAs substrate is divided into substrates.
An easily etched metal layer 5, which also serves as a power supply layer for PHS plating, is formed on one side of the GaAs substrate, and the metal layer 5 is reached by surface etching of the GaAs substrate using the first resist pattern 8 as a mask from the other back side. Since the through hole 9b is formed and the heat dissipation electrode (PH5) 13 is formed on the plating base metal layer 12° using the mask of the second resist pattern, the heat dissipation electrode (PH5) 1 is formed as in the conventional method.
When compared with the case of etching the GaAs substrate 1 using No. 3 as a mask, the formation accuracy of the through hole 9b and, by extension, the dimensional accuracy of the GaAs substrate 1 itself after etching can be improved, making it possible to make the chip dimensions uniform. At the same time, the unbalance of etching within the eight surfaces of the sea urchin is eliminated, and together with the prevention of plating connections during PHS plating due to the interposition of the vapor-deposited metal layer 10b using titanium, which is difficult to adhere to with electrolytic plating, It is possible to perform chip division with a high yield, and the GaAs substrate 1 substrate surface is separated by a heat dissipation electrode (PH5
) Since the chip is wrapped by 13, the end face of the chip is protected and it is possible to prevent chipping or cracking during handling.

In the above embodiment, gold is used as the metal layer in the dicing area, but by using a gold/titanium layer, even if the vapor-deposited metal layer of titanium under the second resist pattern is omitted, the PHS It is possible to prevent plating connections.Also, although a Ni/Au layer was formed by electroless plating as a base metal layer for plating, a titanium/gold/titanium layer was deposited by sputtering, etc., and then a second The same functions and effects as described above can also be obtained by forming a resist pattern and removing unnecessary titanium layers.

(Effects of the Invention) As detailed above, according to the present invention, in a semiconductor device in which a semiconductor element and its electrodes are formed on the main surface of a substrate, and a heat dissipation electrode is formed on the back surface side through a base metal layer. Since the heat dissipation electrode formed on the back surface of the substrate wraps around the dicing area of the board, the coating with the heat dissipation electrode can effectively protect the chip end face, preventing chips from chipping or cracking during handling. In addition, in the dicing area where the substrate is divided into chips, an easily etched metal layer is formed on the main surface (front surface) side of the wafer. Wrapping from the back side.

After etching and thinning the layer to the desired thickness,
Similarly, through-holes reaching at least the metal layer corresponding to the dicing area are selectively formed from the backside of the substrate, and a resist pattern is selectively formed on the backside portion of the metal layer exposed by the through-holes. Using this resist pattern as a mask, a plating base metal layer and then a heat dissipation electrode are formed on the back surface of the substrate including the inner surface of the through hole, so after removing this resist pattern, the corresponding dicing area is When dividing the chip by sequentially etching the metal layer and the substrate, the formation accuracy and even the through-hole formation will be lower when compared to etching the substrate using a heat dissipation electrode as a mask as in the conventional case. In addition to significantly improving the dimensional accuracy of the substrate itself after etching, it also eliminates the unbalance of etching within the wafer surface, and in combination with the wrap-around coating of the back side of the substrate including the dicing area by the heat dissipation electrode. It has excellent features such as making it possible to make the chip dimensions uniform and allowing chip division to be carried out with a high yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view schematically showing the outline of the chip structure of a GaAs-FET to which an embodiment of the semiconductor device according to the present invention is applied, and FIGS. Each is a cross-sectional view schematically showing the manufacturing process sequentially, and FIG. 3 is a cross-sectional view schematically showing an outline of the chip structure of a conventional GaAs-FET, and FIG. 4(a)
to f) are cross-sectional views sequentially schematically showing the main manufacturing steps of the same chip structure. ! ... Semi-insulating GaAs substrate, 2... Gate electrode, 3... Source electrode, 4... Drain electrode,
5...Metal layer, 6...Glass substrate, 7...
Pasting wax, 8...first resist pattern, 9a...through hole reaching source electrode, 9b...
・Through hole reaching the metal layer, 10... Vapor deposited metal layer portion on the first resist pattern, 10a... Vapor deposited metal layer portion on the back side of the source electrode, 10b... Corresponding to the dicing area on the back surface of the metal layer vapor deposited metal layer portion, 11... second resist pattern, 12... plating base metal layer, 1
3... Heat dissipation electrode (ptts). Agent Masuo Oiwa Diagram Figure te/)/ /'l;4'Jm's Wazu 7th Diagram Figure 4

Claims (2)

[Claims] (1) In a semiconductor device in which a semiconductor element and its electrodes are formed on the main surface of the substrate, and a heat dissipation electrode is formed on the back surface side via a base metal layer, the heat dissipation electrode formed on the back surface of the substrate allows dicing of the substrate. What is claimed is: 1. A semiconductor device characterized in that the semiconductor device is configured by covering the area so as to wrap around the area. (2) In manufacturing a semiconductor device in which a semiconductor element and its electrodes are formed on the main surface of the substrate, and a heat dissipation electrode is formed on the back side via a base metal layer, on the surface of the substrate corresponding to the dicing area, A step of selectively forming a metal layer that is easy to etch, and lapping and etching the substrate in the wafer state from the back side to thin the layer to a desired thickness, and at least forming a metal layer corresponding to the dicing area. a step of selectively forming a through hole that extends through the hole, and forming a resist pattern on the back surface portion of the metal layer exposed by the through hole, and using this resist pattern as a mask to cover the inner surface of the through hole. a step of sequentially and selectively forming a plating base metal layer and then a heat dissipation electrode on the back surface of the substrate containing the substrate, and after removing the resist pattern, sequentially and selectively etching the metal layer corresponding to the dicing area and the substrate; 1. A method of manufacturing a semiconductor device, the method comprising at least the step of dividing into chips.