JPH01130544A - Wiring of semiconductor device - Google Patents

Wiring of semiconductor device

Info

Publication number
JPH01130544A
JPH01130544A JP29010587A JP29010587A JPH01130544A JP H01130544 A JPH01130544 A JP H01130544A JP 29010587 A JP29010587 A JP 29010587A JP 29010587 A JP29010587 A JP 29010587A JP H01130544 A JPH01130544 A JP H01130544A
Authority
JP
Japan
Prior art keywords
film
wiring
layer
films
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29010587A
Other languages
Japanese (ja)
Inventor
Matsunori Mori
森 松倫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29010587A priority Critical patent/JPH01130544A/en
Publication of JPH01130544A publication Critical patent/JPH01130544A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To alleviate the stress caused by the upper and the lower layers of a wiring by a silicon film as well as to prevent the elimination of an aluminum film by a method wherein the wiring is formed in such a manner that a layer of aluminum film is pinched by two silicon film layers. CONSTITUTION:A vapor growth film 2 is formed by patterning on a semiconductor substrate 1, and a wiring 4 of three-layer structure, contacting to the substrate 1, is formed through the intermediary of a contact hole 3. An Si film 5 is formed on the lower layer of wiring 4, and an Al film 6 is formed thereon in such a manner that the hole 3 will be buried by the film 4. Besides, an Si film 7 is formed on the top layer of the wiring 4, a three-layer Al film 6 is formed in such a manner that it is pinched by the two layers of Si films 5 and 7. Then, a PSG film 8 is laminated on the wiring 4. Accordingly, the stress caused by the films 2 and 8 is alleviated by the films 5 and 7 of the wiring 4, and the shifting of the film 6 by said stress is suppressed. As a result, the elimination of the Al film can be prevented.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体基板に形成された半導体集積回路素子を
接続する半導体装置の配線に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wiring of a semiconductor device that connects semiconductor integrated circuit elements formed on a semiconductor substrate.

[従来の技術] 従来、半導体装置においては、その半導体素子間等を電
気的に接続するために、アルミニウム(Aβ)をスパッ
タリングすることにより所定の膜厚に形成したAJ薄膜
が配線として使用されている。
[Prior Art] Conventionally, in semiconductor devices, an AJ thin film formed to a predetermined thickness by sputtering aluminum (Aβ) has been used as wiring to electrically connect semiconductor elements. There is.

[発明が解決しようとする問題点] しかしながら、上述した従来の半導体装置の配線におい
ては、その配線の下地として気相成長膜が形成されてい
る場合において、その上層としてPSG膜(リンを含有
するシリコン酸化膜)を形成すると、下層及び上層の膜
から作用する応力により配線のAJ膜が局所的に消滅し
てしまう虞れがあるという問題点がある。
[Problems to be Solved by the Invention] However, in the wiring of the conventional semiconductor device described above, when a vapor phase growth film is formed as the base of the wiring, a PSG film (containing phosphorus) is used as the upper layer. If a silicon oxide film is formed, there is a problem that the AJ film of the wiring may be locally destroyed due to stress acting from the lower and upper films.

本発明はかかる問題点に鑑みてなされたものであって、
配線構成膜の消滅が回避された半導体装置の配線を提供
することを目的とする。
The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a wiring for a semiconductor device in which disappearance of a wiring-constituting film is avoided.

[問題点を解決するための手段] 本発明に係る半導体装置の配線は、半導体基板に形成さ
れた集積回路素子を接続する半導体装置の配線において
、アルミニウム膜とシリコン膜とのいずれか一方の膜の
1層が他方の膜の2層に挟まれた3層構造を有すること
を特徴とする。
[Means for Solving the Problems] In the semiconductor device wiring according to the present invention, which connects integrated circuit elements formed on a semiconductor substrate, one of an aluminum film and a silicon film is used. It is characterized by having a three-layer structure in which one layer of the film is sandwiched between two layers of the other film.

[作用] 本発明においては、配線は、1層のアルミニウム膜を2
層のシリコン膜で挾むか、又は1層のシリコン膜を2層
のアルミニウム膜で挾む3層構造を有している。アルミ
ニウム膜をシリコン膜で挟んだ場合は、配線の上層及び
下層に配設される膜からの応力をシリコン膜が緩和する
ので、アルミニウム膜が消滅することはない。一方、シ
リコン膜をアルミニウム膜で挟んだ場合は、アルミニウ
ム膜の粒界にシリコンが拡散して析出することによりア
ルミニウム膜め移動が抑制され、アルミニウム膜の消滅
が防止される。
[Function] In the present invention, the wiring consists of two layers of aluminum film.
It has a three-layer structure in which two layers of silicon films are sandwiched between each other, or one layer of silicon film is sandwiched between two layers of aluminum films. When an aluminum film is sandwiched between silicon films, the silicon film relieves stress from films disposed above and below the wiring, so the aluminum film does not disappear. On the other hand, when a silicon film is sandwiched between aluminum films, silicon diffuses and precipitates in the grain boundaries of the aluminum film, thereby suppressing migration of the aluminum film and preventing disappearance of the aluminum film.

[実施例] 次に、本発明の実施例について添付の図面を参照して説
明する。
[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

第1図は本発明の第1の実施例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.

半導体基板1上に気相成長膜2がパターン形成されてお
り、この気相成長膜2に設けられたコンタクトホール3
を介して半導体基板1と接触するようにして3層構造の
配線4が形成されている。
A vapor phase growth film 2 is patterned on a semiconductor substrate 1, and a contact hole 3 provided in this vapor growth film 2
A three-layer interconnection 4 is formed so as to be in contact with the semiconductor substrate 1 via.

この配線4の最下層には、Siを200乃至400人の
膜厚にスパッタリングすることによりSi膜5が形成さ
れている。なお、コンタクトホール3は気相成長膜2の
上にスパッタリングSi膜5を形成した後、両膜をパタ
ーンエツチングすることにより設けられている。
A Si film 5 is formed on the bottom layer of the wiring 4 by sputtering Si to a thickness of 200 to 400 layers. Note that the contact hole 3 is provided by forming a sputtering Si film 5 on the vapor-phase grown film 2 and then pattern-etching both films.

そして、Si膜5の形成後にAβを所定の膜厚にスパッ
タリングすることにより、コンタクトホール3を埋める
ようにしてAρ膜6が形成されている。
Then, by sputtering Aβ to a predetermined thickness after forming the Si film 5, an Aρ film 6 is formed to fill the contact hole 3.

更に、配線4の最上層として、Stを200乃至400
人の膜厚にスパッタリングすることにより、Si膜7が
形成されている。このようにして、Aρ膜6を2層のS
i膜5,7が挾む3層構造の配線4が設けられる。
Furthermore, as the top layer of the wiring 4, St is 200 to 400.
The Si film 7 is formed by sputtering to a thickness equal to that of the average thickness. In this way, the Aρ film 6 is formed into two layers of S
A three-layer interconnection 4 sandwiched by i-films 5 and 7 is provided.

この配線4の上には、PSG膜(リンを含有するシリコ
ン酸化膜)8が積層されている。
A PSG film (silicon oxide film containing phosphorus) 8 is laminated on this wiring 4.

このように構成された半導体装置の配線においては、P
SG膜8及び気相成長膜2からの応力は配線4の第1層
目及び第3層目のSi膜5,7が緩和し、この応力によ
るAl膜6の移動を抑制する。従って、AJ膜6の消滅
が防止される。
In the wiring of a semiconductor device configured in this way, P
The stress from the SG film 8 and the vapor growth film 2 is relaxed by the first and third Si films 5 and 7 of the wiring 4, and the movement of the Al film 6 due to this stress is suppressed. Therefore, disappearance of the AJ film 6 is prevented.

次に、第2図の断面図に基いて、本発明の第2の実施例
に5ついて説明する。
Next, a second embodiment of the present invention will be described based on the sectional view of FIG.

この実施例は、配線9の構造が第1の実施例の配線4と
異なる。なお、第2図において第1図と同一物には同一
符号を付して説明を省略する。
In this embodiment, the structure of the wiring 9 is different from the wiring 4 of the first embodiment. In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

この配線9においては、最下層のAρ膜10がコンタク
トホール3を埋めるようにしてスパッタリング形成され
ている。このAβ膜10は配線9の所定の膜厚の約1/
2の膜厚を有する。Ajl膜1膜上0上、SLを200
乃至400人の膜厚にスパッタリングすることにより、
S1膜11が形成されている。そして、配線9の最上層
には、同様にスパッタリングにより、配線9の所定の膜
厚の約1/2の膜厚を有するAρ膜12が形成されてい
る。
In this wiring 9, the lowest layer Aρ film 10 is formed by sputtering so as to fill the contact hole 3. This Aβ film 10 is approximately 1/1/2 of the predetermined film thickness of the wiring 9.
It has a film thickness of 2. Ajl film 1 film 0 on top, SL 200
By sputtering to a film thickness of 400 to 400 mm,
An S1 film 11 is formed. Then, on the uppermost layer of the wiring 9, an Aρ film 12 having a thickness approximately 1/2 of the predetermined thickness of the wiring 9 is formed by sputtering as well.

この第2の実施例においては、配線9の第2層のSi膜
11からSiが第1層及び第3層のAI膜10.12の
粒界を拡散していき、A1膜10゜12中に析出する。
In this second embodiment, Si from the second layer Si film 11 of the wiring 9 diffuses through the grain boundaries of the first and third layer AI films 10. It precipitates out.

これにより、気相成長膜2及びPSG膜8からの応力を
受けてもA、f膜10゜12は移動せず、その消滅が防
止される。
As a result, even when subjected to stress from the vapor-phase grown film 2 and the PSG film 8, the A and f films 10.12 do not move and are prevented from disappearing.

[発明の効果] 以上説明したように本発明によれば、配線がSi膜とA
J膜との3層構造を有するから、AJ膜をSi膜で挾む
場合には配線の上層及び下層からの応力をSi膜が緩和
することによりAJ膜の消滅が防止されると共に、Si
膜をA(膜で挾む場合にはSiがA1膜中の粒界を拡散
して析出することにより、Aβ膜の移動が抑制されAρ
膜の消滅が防止される。このように、本発明は゛配線の
A1膜の消滅が回避されるという効果を奏し、半導体装
置の製造上極めて実益が高い。
[Effects of the Invention] As explained above, according to the present invention, the wiring is made of Si film and A
Since it has a three-layer structure with the J film, when the AJ film is sandwiched between the Si films, the Si film alleviates the stress from the upper and lower layers of the wiring, preventing the AJ film from disappearing, and also preventing the AJ film from disappearing.
When the film is sandwiched between A1 films, Si diffuses through the grain boundaries in the A1 film and precipitates, suppressing the movement of the Aβ film and Aρ
Disappearance of the film is prevented. As described above, the present invention has the effect of preventing the disappearance of the A1 film of the wiring, and is extremely useful in manufacturing semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を示す縦断面図、第2図
は本発明の第2の実施例を示す縦断面図である。 1;半導体基板、2;気相成長膜、3;コンタクトホー
ル、4.9;配線、5.7.11;Si膜、6,10.
12;A1膜、8.PSG膜出願出願人本電気株式会社
FIG. 1 is a longitudinal sectional view showing a first embodiment of the invention, and FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention. 1; Semiconductor substrate, 2; Vapor phase growth film, 3; Contact hole, 4.9; Wiring, 5.7.11; Si film, 6, 10.
12; A1 membrane, 8. PSG membrane application applicant Hondenki Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板に形成された集積回路素子を接続する
半導体装置の配線において、アルミニウム膜とシリコン
膜とのいずれか一方の膜の1層が他方の膜の2層に挟ま
れた3層構造を有することを特徴とする半導体装置の配
線。
(1) In semiconductor device wiring that connects integrated circuit elements formed on a semiconductor substrate, a three-layer structure in which one layer of either an aluminum film or a silicon film is sandwiched between two layers of the other film. Wiring for a semiconductor device characterized by having the following.
(2)前記一方の膜がアルミニウム膜であることを特徴
とする特許請求の範囲第1項に記載された半導体装置の
配線。
(2) The wiring for a semiconductor device according to claim 1, wherein the one film is an aluminum film.
(3)前記一方の膜がシリコン膜であることを特徴とす
る特許請求の範囲第1項に記載された半導体装置の配線
(3) The wiring for a semiconductor device according to claim 1, wherein the one film is a silicon film.
JP29010587A 1987-11-17 1987-11-17 Wiring of semiconductor device Pending JPH01130544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29010587A JPH01130544A (en) 1987-11-17 1987-11-17 Wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29010587A JPH01130544A (en) 1987-11-17 1987-11-17 Wiring of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01130544A true JPH01130544A (en) 1989-05-23

Family

ID=17751861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29010587A Pending JPH01130544A (en) 1987-11-17 1987-11-17 Wiring of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01130544A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245255A (en) * 1984-05-21 1985-12-05 Hitachi Ltd Wiring structure of semiconductor device
JPS6255962A (en) * 1985-09-05 1987-03-11 Matsushita Electronics Corp Semiconductor device
JPS6292340A (en) * 1985-10-17 1987-04-27 Nec Corp Manufacture of semiconductor device
JPS634648A (en) * 1986-06-25 1988-01-09 Toshiba Corp Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245255A (en) * 1984-05-21 1985-12-05 Hitachi Ltd Wiring structure of semiconductor device
JPS6255962A (en) * 1985-09-05 1987-03-11 Matsushita Electronics Corp Semiconductor device
JPS6292340A (en) * 1985-10-17 1987-04-27 Nec Corp Manufacture of semiconductor device
JPS634648A (en) * 1986-06-25 1988-01-09 Toshiba Corp Semiconductor device

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