JPS60245255A - Wiring structure of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of the p-n junction of a semiconductor substrate and the decrease in withstand voltage by a method wherein the whole constructed in three layers by forming thin Si-containing films above and below an Al film made of pure Al, and is then connected to the semiconductor substrate via lower thin film. CONSTITUTION:After a gate oxide film 2 and a field oxide film 3 are formed on a p type Si substrate 1, a poly Si film is formed and patterned into a gate electrode 4. An n type source-drain region 5, interlayer insulation films 6, 7, and a contact hole 8 are formed; next, a poly-Si film 9 is thinly formed by CVD, and an Al film 10 is some thickly formed thereon. A poly Si film 11 is thinly formed by another CVD, thus constructing the whole in three layers with the upper and lower poly Si films 9, 11 and the Al film 10; then, the wiring is completed by required patterning. This manner prevents the direct connection of the Al film with the Si substrate, the suck-up of silicon, and Al diffusion; accordingly, the decrease and breakdown in withstand voltage of the p-n junction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention [Technical Field] The present invention relates to a wiring structure for a semiconductor device, and particularly to a wiring structure that improves the reliability of A-e wiring.

[Background technology]

In semiconductor devices such as IC and LSI, A wiring is used for connection between the semiconductor substrate and circuit elements formed on it, but in recent years, this A-e film for human-e wiring has been developed by CV D (Ch
chemical vapor deposition
) has been proposed. That is, although the conventional A film is formed by a so-called vapor deposition method,
On the other hand, the CVD method is often used to form polysilicon films and other insulating films in the manufacturing process of semiconductor devices. Therefore, when forming the A1 film, it is necessary to transfer the wafer in the CVD apparatus to the vapor deposition apparatus, which is not desirable in terms of work efficiency and causes problems such as adhesion of foreign substances. Therefore, the A membrane is CVD in the CVD equipment.
If formed by the D method, various films including A4 films can be formed without moving the wafer, and work efficiency and reliability can be improved.

However, since the A-e film formation method using the CVD method that has been proposed so far is a method of forming by thermally decomposing TIBA (tri-isobutyl aluminum), the formed A-e film is pure A2. Therefore, unlike vapor deposition or sputtering methods, it is difficult to form a film containing Si, for example, A, E, etc.

Therefore, according to the inventor's study, if this film is used as a wiring and connected to a diffusion layer of a semiconductor substrate, etc., Si in the semiconductor substrate will be reduced to A! during heat treatment. A phenomenon occurs in which It is sucked up into the patterned film, or conversely, It is diffused into the semiconductor substrate.
It is thought that the pn junction of the semiconductor substrate is destroyed or the withstand voltage is lowered. Furthermore, if time elapses with the AA wiring exposed, A/hillock migration is likely to occur, and it is considered that reliability is likely to decrease, such as increased A4 wiring resistance and disconnection.

Regarding the CVD technology of AJ3 film, for example,
rsolid 5tate Technology/
Published in the 1982 Japanese Power issue of the Japanese version [-
Low-pressure chemical vapor deposition of A-e, A-e-S i alloys for conductor metallization J (M, J, Cook,
R, A, He1necke, R, C, 5tern,
J, W, C, Maes).

[Purpose of the invention]

The purpose of the present invention is to prevent the destruction of the p-n junction of a semiconductor substrate and the decrease in withstand voltage, and also to prevent A! A! was formed using the CVD method to prevent hillock migration. An object of the present invention is to provide a wiring structure that can improve the reliability of wiring.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, thin Si-containing films are formed on the lower and upper sides of an Ai film made of pure Al to form a three-layer structure as a whole, and the structure is configured so that connection with the semiconductor substrate can be achieved through the lower thin film. By doing so, it is possible to prevent breakdown of the pn junction in the semiconductor substrate and decrease in breakdown voltage, and also to prevent hillock migration, thereby achieving improved reliability.

〔Example〕

1 and 2 show an embodiment in which the present invention is applied to an M, O8 type field effect transistor (MOSFET), and FIG. 2 is an enlarged view of the main part of FIG. 1.

That is, for example, a gate oxide film 2 is formed on a p-type silicon substrate 1.
After forming field oxide film 3, a polysilicon film is formed by CVD and patterned to form gate electrode 4. Next, P (phosphorus) and A s,
, (Arsenic) or the like is ion-implanted using a self-alignment method and activated, thereby forming n-type source/drain regions 5. On top of that, surface oxidation and P
Interlayer insulating films 6 and 7 are formed by SG CVD, and contact holes 8 are formed therein by lithography.

Next, a thin polysilicon film 9 is formed by CVD method,
A slightly thicker AJ film 10 is formed thereon by the CVD method. this person! TIBA is used to form the film 10, and Ae is deposited according to the following formula.

(s C4Ho) s k-13→A2↓+3 (i
-c4H8) -F-H, >265°C Thereafter, the polysilicon film 11 was thinned (
After forming, the entire upper and lower polysilicon films 11°9 and AAA are formed.
A three-layer structure is formed using lO2, and the wiring is completed by performing predetermined patterning. Note that an annealing process is performed after forming the upper polysilicon film 11.

Therefore, the wiring structure configured in this way, that is, A!
According to the wiring, the A2 film 10 is not directly connected to the diffusion layer (source/drain regions 5, 5) of the silicon substrate 1, but is connected via the lower polysilicon film 9. There is. Therefore, it is possible to prevent silicon from being sucked up from the silicon substrate 1 to the wiring, and also to prevent A! Diffusion of A2 from the film 10 into the silicon substrate 1 can be prevented, thereby preventing destruction of the p-n junction between the source/drain regions 5 and a decrease in breakdown voltage. On the other hand, by performing an annealing treatment after forming the upper polysilicon film 11, the silicon in the upper polysilicon film 11 is sucked into AAAi0 to form Ai St. This makes it possible to more reliably prevent the suction of silicon from the silicon substrate 1, which occurs in a chain reaction due to the suction of silicon from the lower polysilicon film 9, while the A! The occurrence of hillock migration can be suppressed, A
[It is possible to prevent an increase in resistance or disconnection of the film 10 or the A-e wiring. Further, the upper polysilicon film 11 prevents the M film 10 from being exposed, and A! It also functions as a protective film for the membrane.

Note that the lower polysilicon film 9. A-e film 10° upper polysilicon film 11 and annealing process are all done in one C
Wafers (
The silicon substrate 1) is not taken out of the CVD apparatus (this is advantageous in terms of work efficiency and prevention of foreign matter adhesion).

〔effect〕

(1) Since the AA wiring has a three-layer structure consisting of the central Ap film and the silicon films provided on the upper and lower sides, the A and 8 films are connected to the silicon substrate via the lower silicon film. In other words, direct connection between the A1 film and the silicon substrate is prevented, and the AA film is pure A! Even if it is formed from A, 11? This prevents the spread of p.
- It is possible to prevent a decrease in the breakdown voltage of the n-junction and its destruction.

(Since the 21AA wiring has a three-layer structure, the AA film absorbs silicon from the upper silicon film and
The composition is pure A! Now let's move on to what's easy to happen! It is possible to suppress the occurrence of hillock migration, prevent an increase in resistance and disconnection, and improve reliability.

(By making the 31A-e wiring a three-layer structure, problems such as p-n junction breakdown voltage and migration can be prevented even if pure Al material is used for the central A! film.
It can be formed by the D method, and a series of C and D processes can be performed together with the upper and lower silicon films, thereby improving work efficiency and suppressing the adhesion of foreign matter.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the central A!
Is the film trimethylaluminum A-4i? A photo-CVD method using decomposition of (CH3)5 using an Ar+ laser may also be used. Furthermore, although it is effective to form the A4 film by CVD, it is of course possible to form it by sputtering or vacuum evaporation. Further, the upper and lower silicon films are not limited to polysilicon films, but may be formed of amorphous silicon, and the upper film may be a film of Si3N4 or the like as long as it is a protective film containing silicon. good. Of course, if the semiconductor substrate is something other than silicon, the above,
It is important to change the underlying membrane as well.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the wiring structure for connecting the source and drain of MOSFET, which is the background field of application, but the invention is not limited to this. It can be applied to general wiring structures of semiconductor devices such as transistors.

[Brief explanation of drawings]

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is an enlarged view of the main parts. 1... Semiconductor substrate, 2... Gate oxide film, 3...
Field oxide film, 4... Gate electrode, 5... Source/drain region, 9... Lower polysilicon film, 10
...A! Film, 11... Upper polysilicon film.

Claims (1)

[Claims] 1. A made of pure aluminum! A wiring structure for a semiconductor device, characterized in that semiconductor thin films are formed on the upper and lower sides of a wiring film to form a three-layer structure, and the AA wiring film is connected to a semiconductor substrate via the lower semiconductor thin film. 2. The wiring structure of a semiconductor device according to claim 1, which is formed by a CVD method with an A7 pattern. 3. The wiring structure for a semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is a silicon substrate, and the upper and lower semiconductor thin films are polysilicon films.