JPS58184742A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To connect between a lower layer wiring and an upper layer wiring with a wiring material buried in a through hole, to enhance yield of a wiring system, and moreover to hold the upper part of the through hole flat by a method wherein the PR process is supplemented by one process per one wiring layer. CONSTITUTION:After a lower layer wiring 201 is formed on a semiconductor substrate 205, an interlayer insulating film 202 is adhered, the interlayer insulating film is etched using a resist 207 as the mask to open a through hole 206. At this time, the wiring material 208 of nearly the same thickness with the film 202 is adhered, and a resist 209 is formed only on the through hole. Then the wiring material 208 is removed leaving the through hole part using the resist 209 as the mask. At this time, isotropic etching is applied for etching of the wiring material 208, and by holding properly the margin of the resist 209 between the through hole opening part, the shape buried the opening part with the wiring material 210 can be formed, and the surface can be flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, particularly to the formation of through-hole portions in a multilayer wiring system of an integrated circuit.

Conventionally, the method of connecting upper layer wiring and lower layer wiring in a multilayer wiring system of a semiconductor device is to attach a lower layer wiring material to a semiconductor substrate, form a lower layer wiring system using a photoetching method, and then form an interlayer insulating film by vapor phase growth. A method is used in which a through hole is opened at a desired position using a photoetching method, an upper layer wiring material is deposited, and an upper layer wiring system is formed using a photoetching method. ing. According to this method, the inside of the through hole is stepped from the outside of the through hole by the thickness of the interlayer insulating film, and as a result, the upper layer wiring may be cut at the end of the through hole, and the lower layer wiring and the upper layer wiring may not be electrically connected. .

This is one of the causes of a decrease in yield of integrated circuits having multilayer wiring systems. Furthermore, as a method for improving the above-mentioned cut at the end of the through hole in the upper layer wiring, there is a conventional method of creating a slope at the end of the through hole when opening the through hole. However, even with this method, there is still a difference in level between the inside of the through hole and the outside of the through hole.
If upper-layer wiring passes through this part, wire breakage may occur due to the step, and if upper-layer wiring is not passed over the through-hole, the degree of freedom in wiring design will be reduced.

The present invention uses conventional semiconductor device manufacturing equipment to improve the connection between lower layer wiring and upper layer wiring at the through-hole portion of a multilayer wiring system, and to flatten the top of the through hole to enable multilayer wiring with a high degree of freedom. The purpose is to make people happy.

That is, a process of photoetching a through hole in the nine interlayer insulating film grown on the lower wiring system of the present invention, filling the through hole with a wiring material, and removing the wiring material other than the through hole. and forming an upper layer wiring on the through hole filled with the wiring material.

The present invention will be explained below using the drawings. FIG. 1 is a sectional view of a through-hole portion of a two-layer wiring system formed according to the prior art. After forming a lower layer wiring 101 on a semiconductor substrate 105 by a photo-etching method, an interlayer insulating film 102 made of silicon nitride, for example, is deposited by a vapor phase epitaxy method, and a through hole 106 is formed at a desired position by photolithography. Openings are made by etching. Thereafter, an upper layer wiring material 103 is deposited, a wiring system is formed by photoetching, and finally a protective film 104 is deposited by vapor phase growth.

FIG. 2 shows a method according to one embodiment of the present invention. As an example, a case of a two-layer wiring system will be shown. After forming a lower layer wiring 201 on a semiconductor substrate 205 according to the conventional technique, an interlayer insulating film 202 is attached, and the interlayer insulating film is etched using a photoresist 207 as a mask to open a through hole 206 (FIG. 2). (A)). Here, a wiring material 208 having a thickness approximately equal to that of the glabella insulating film 202 is deposited, and a photoresist 2 is applied only over the through hole by photowork.
09 (FIG. 2(B)). Next, using the photoresist 209 as a mask, the wiring material 208 is removed leaving the through hole portion. At this time, wiring material 2'1:.

By applying Kfi isotropic etching and taking an appropriate margin between the photoresist 209 and the through-hole opening, only the through-hole opening can be filled with the wiring material 210, and the surface is similar to the one shown in FIG. It can be done easily (Figure 2 (C)).

At this time, if necessary, after removing the resist 209, the layered wiring material 210 may be etched to adjust the shape. After filling the through hole with the wiring material 210, the upper layer wiring material 21 is filled with the wiring material 210.
1 is deposited, an upper layer wiring system is formed by the 7# etching method, and a lumbar protection membrane 212 is deposited by the vapor phase growth method to complete the two-layer wiring system (Fig. jI2 (D)).

Above, we have explained the 2-layer wiring system, but the 3-layer, 4-layer
Through-hole portions in the case of multilayer wiring systems such as layers can also be formed in the same manner.

FIG. 3 shows a case where the present invention is applied to a 3NjI arrangement IN system. That is, the first layer wiring 30 is placed on the semiconductor substrate 301.
1. 2nd layer wiring 3o2. The third layer wiring 303 is formed by the method of the present invention.

As is clear from the above explanation, the original FIiJFiPRj:
(adding one process per wiring) A method of connecting lower layer wiring and upper layer wiring with wiring material that fills through holes, increasing the fraction of the wiring system and keeping the surface of the through hole flat. is provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a two-layer wiring system according to the prior art. FIG. 2 is a cross-sectional view showing one embodiment of the present invention, taking a two-layer wiring system as an example. FIG. 3 is a sectional view showing another embodiment of the present invention, taking a three-layer wiring system as an example. In addition, in the figure, 101, 201, river...lower layer wiring, 10
2.202...Interlayer insulating film, 103...
・Upper layer wiring, 104.212... Retention film, 10
5,205... Semiconductor substrate, 106,206.
River...through hole, 207...dan photoresist,
208, 210... Wiring material, 209...
. . . Photoresist, 211 . . . Lower wiring material. Z 1 Kasumi 2θ5 2θf, replacement? (2) , io, 3.3ρ7 4.3 Figure'1゜

Claims (1)

[Claims] a step of opening a through hole by photoetching in the interlayer insulating film grown on the lower wiring system; a step of filling the through hole with a wiring material and removing the wiring material in a portion other than the through hole; 1. A method for manufacturing a semiconductor device, comprising the step of forming an upper layer wiring on a through hole filled with a wiring material.