JP2705556B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a wiring layer of an air bridge structure, and more particularly to a semiconductor integrated circuit device suitable for a multilayer air bridge structure.

[0002]

2. Description of the Related Art FIG. 11 is a perspective view showing an example of a conventional semiconductor integrated circuit device having such a wiring structure. this is,
This is described in JP-A-4-127453. A first layer wiring 22 is formed on a lower inorganic insulating film (SiO ₂ ) 21 formed on a semiconductor substrate 20. A first interlayer inorganic insulating film 23 is formed on the first layer wiring 22.
Through the second layer wiring 2 in a direction crossing the first layer wiring 22 through
4 are formed. The first interlayer inorganic insulating film 23 is located only at the intersection of the first layer wiring 22 and the second layer wiring 24, and a cavity is formed between the first layer wiring 22 and the second layer wiring 24 except at the intersection. .

Next, a part of the manufacturing process of the structure shown in FIG. 11 will be described with reference to FIG. FIG. 12 is a sectional view taken along line MM in FIG. First, as shown in FIG. 12A, a lower inorganic insulating film 21 is formed on a semiconductor substrate 20, and a first wiring layer and a first interlayer inorganic insulating film are formed thereon. By applying an etching technique, the first interlayer inorganic insulating film 23 is formed, and the first layer wiring layer is etched with the same pattern to form the first layer wiring 22. Then, the first interlayer organic insulating film 25 is applied on the entire surface, and this is etched back until the surface of the first interlayer inorganic insulating film 23 is exposed.

Next, as shown in FIG. 12B, a via hole 26 is formed at a desired position in the first interlayer inorganic insulating film 23 by using a photolithography technique and an etching technique. Then, after forming the second-layer wiring layer 24 ', the second-layer wiring 24 is formed by using a photolithography technique and an etching technique. Next, as shown in FIG. 12C, the first interlayer inorganic insulating film 23 is patterned by etching using a mask (not shown) and the second wiring 24 as a mask. And FIG.
As shown in (d), the first interlayer organic insulating film 25 is removed by isotropic etching, and a cavity 27 is formed.

As described above, the first interlayer inorganic insulating film 23 is etched with the same mask as that of the first layer wiring 22 so as to be left only on the first layer wiring 22 and further flattened with the first interlayer organic insulating film 24. After forming the second layer wiring 24 orthogonal to the first layer wiring 21, the first interlayer inorganic insulating film 23 is etched again, so that the first interlayer inorganic insulating film 23 is formed only at the intersection between the first layer wiring 22 and the second layer wiring 24. Pillars of the insulating film 23 are formed. Also,
By removing the first interlayer organic insulating film 25 by isotropic etching, a cavity 2 is formed between the first layer wiring 22 and the second layer wiring 24.
7, an air bridge structure is formed between the first-layer wiring 22 and the second-layer wiring 24, which is connected by a pillar only at the intersection, and the wiring capacity can be greatly reduced.

[0006]

In this conventional semiconductor integrated circuit device, the first interlayer insulating film for forming a cavity between the first layer wiring and the second layer wiring is formed by the first layer wiring and the first layer wiring. Since it is formed only at the intersection of the two-layer wiring, when the second-layer wiring exists alone or in a region where the distance between the first-layer wirings is wide, a cavity is formed below the second-layer wiring, or the lower insulating film is formed. Or either state. When a cavity is formed under the second layer wiring, the second wiring is in a floating state over a long distance, and there is a possibility that a defect such as a short circuit due to peeling or deformation of the wiring may occur.

Further, when the second-layer wiring is in contact with the lower-layer insulating film, a step formed between a region in which the second-layer wiring is on the first-layer wiring and a region in contact with the lower-layer insulating film has a step difference. The sum of the film thickness of the wiring and the film thickness of the first interlayer insulating film causes a problem in focus margin and step coverage in the photolithography process of the second layer wiring, and furthermore, the capacitance with the region below the lower insulating film is reduced. It becomes large and causes a decrease in performance. Further, when a thin second-layer wiring is formed on a thick first-layer wiring, the first interlayer insulating film exists over the entire intersection, so that the first-layer wiring and the second-layer wiring between the first-layer wiring and the second-layer wiring are formed. There is a problem that the effect of reducing the capacity is reduced. An object of the present invention is to improve wiring capacitance in a wiring structure having two or more layers,
It is another object of the present invention to provide a semiconductor integrated circuit device in which an upper layer wiring is kept flat and various problems which occur in a manufacturing process are solved.

[0008]

According to a method of manufacturing a semiconductor integrated circuit device of the present invention, a first insulating film is formed on a semiconductor substrate by a grid.
And the lattice pitch of the first insulating film
Forming a first layer wiring at a position shifted by a half pitch;
A second insulating film on the substrate in the same lattice shape as the first insulating film.
Forming, and the lattice pitch and half pitch of the second insulating film.
2nd layer wiring in the direction crossing the 1st layer wiring
Forming a wire, and forming the first layer wiring and the second layer wiring.
And etching the first and second insulating films.
Process. Here, in the case of a structure with three or more layers
Means that, in addition to the above steps, an Nth
Is formed in the same lattice as the first insulating film.
And the same position as the first layer wiring on the Nth insulating film.
Forming an N-th layer wiring, and further forming an (N + 1) -th
Forming an edge film in the same lattice as the first insulating film;
At the same position as the second layer wiring on the (N + 1) th insulating film.
Forming an (N + 1) th layer wiring;
Nth and (N + 1) th insulation using the N + 1 layer wiring as a mask
Etching the film.

[0009]

[0010]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a perspective view conceptually showing a first embodiment of the present invention, and shows a semiconductor integrated circuit device having a two-layer wiring structure. A silicon nitride film (Si ₃ N ₄ film) 2 as a protective film and an etching stopper is provided on a silicon substrate 1.
The first aluminum wiring 3 has columnar Cs formed at equal pitches.
An air bridge structure is provided which extends in a predetermined direction on the first columnar insulating film 4 made of the VD oxide film 5 and is separated from the silicon nitride film 2 at a required interval by the first columnar insulating film 4. ing. Here, the first aluminum wiring 3
Silicon nitride film 6 as an etching stopper underneath
Are formed.

A second aluminum wiring 7 formed on the first aluminum wiring 3 extends in a direction orthogonal to the first aluminum wiring 3 and is formed on the first aluminum wiring 3.
Similarly to the above, the second columnar insulating film 8 formed on the silicon nitride film 2 with a thickness larger than that of the first columnar insulating film 4 and at an equal pitch is separated from the silicon nitride film 2 at a large interval. It has an air bridge structure. Here, the second columnar insulating film 8 is formed of the columnar CVD oxide film 5.
, A silicon nitride film 6 and a columnar CVD oxide film 9. Also, the second aluminum wiring 7
Silicon nitride film 1 as an etching stopper underneath
0 is formed.

Therefore, according to this structure, the first aluminum wiring 3 and the second aluminum wiring 7 do not come in contact with any part other than the columnar insulating films 4 and 8, and the periphery is a cavity 13. There is no insulating film between the wiring 3 and the second aluminum wiring 8, and the wiring capacity is greatly reduced. However, although not shown in FIG. 1, when the first aluminum wiring 3 and the second aluminum wiring 8 are electrically connected, the second aluminum wiring 8 is formed to have a downwardly convex shape at the intersection of the two. And is connected to the first aluminum wiring 3. The first aluminum wiring 3
When one or both of the first and second aluminum wirings 8 have a large width, interlayer insulation may be left between the wirings.

Next, a method of manufacturing the wiring structure shown in FIG. 1 will be described. First, as shown in FIG. 2A, a silicon nitride film 2 and a CVD oxide film 5 'are grown on a silicon substrate 1. Then, as shown in FIG. 2B, CVD of the entire chip area is performed using a photolithography technique and an oxide film etching technique.
The oxide film 5 'is patterned in a lattice shape shifted by a half pitch from the first aluminum wiring 3 to be formed later, and is formed by a lattice CVD method.
An oxide film 5 ″ is formed. Thereafter, a silica coating film 11 is formed on the entire surface of the wafer.
It is shown in (c). FIG. 2B is a sectional view taken along line AA of FIG.
It becomes a line sectional view. Here, in order to form the lattice-shaped CVD oxide film 5 ″ at a uniform pitch on the entire surface of the semiconductor device, the silica coating film 11 is uniformly and flatly formed on the entire surface. In this case, a polyimide film is used instead of the silica coating film. Or the like may be used.

Next, as shown in FIG. 3A, the silica coating film 11 is cured by baking, and the flat silica coating film 11 is entirely etched to expose the surface of the lattice-shaped CVD oxide film 5 ″. After that, a silicon nitride film 6 and a first aluminum wiring layer 3 'are grown on the entire surface, where contacts are formed to connect the silicon substrate 1 and the first aluminum wiring 3, although not shown. After the silicon nitride film 6 is grown and before the first aluminum wiring layer 3 'is formed, the silicon nitride film 6, the lattice-like CVD oxide film 5 "or the silica coating film 11 is formed by using a photolithography technique and an etching technique. First, a contact hole is opened in the silicon nitride film 2. The via holes are filled by growing the first aluminum wiring layer 3 'or by burying tungsten or the like to form contact portions.

Then, as shown in FIG. 3B, the first aluminum wiring layer 3 'is patterned by photolithography and aluminum etching to form the first aluminum wiring 3. FIG. 3C shows the planar structure, and FIG. 3B is a sectional view taken along the line BB. As can be seen, the first aluminum wiring 3 is
Here, the wiring is formed in the vertical direction in the figure, and is formed so as to have the same pitch dimension over the entire surface of the semiconductor device, but a half pitch shifted from the lattice-shaped CVD oxide film 5 ″.

Next, as shown by a broken line in FIG.
On the surface where the first aluminum wiring 3 and the silicon nitride film 6 are exposed, a CVD oxide film 9 ′ is grown to be thicker than the first aluminum wiring 3. And the lattice C
Using the mask used to form the VD oxide film 5 ", using a photolithography technique and an etching technique, a second lattice C which overlaps the lattice CVD oxide film 5" online.
A VD oxide film 9 "is formed. Further, the silicon nitride film 6 other than the lower portion of the first aluminum wiring 3 and the second lattice-like CVD oxide film 9" is etched, and then a silica coating film 12 is formed to cover the surface. Flatten.

Subsequently, as shown in FIG. 4B, the entire surface is etched from the upper surface of the silica coating film 12 to planarize the second lattice-like CVD oxide film 9 ″. A silicon nitride film 10 is formed, and FIG.4 (c) is a plan view thereof, and FIG.4 (b) is a cross-sectional view taken along the line CC.
In the case where a through hole connecting the first aluminum wiring 3 and the second aluminum wiring is formed here, an opening is formed in the silica coating film 12 and the silicon nitride film 10 in the same manner as in the formation of the contact.

Next, as shown in FIG. 5A, a second aluminum wiring layer 7 'is grown on the entire surface, and a direction orthogonal to the wiring direction of the first aluminum wiring 3 is formed by using photolithography technology and aluminum etching technology. The second aluminum wiring 7 and the silicon nitride film 10 are patterned at the same pitch as the first aluminum wiring 3 and at a half pitch from the second lattice-like CVD oxide film 9 ″. FIG. 5B shows the planar structure.

FIGS. 6 (a), 6 (b) and 6 (c) show sectional views taken along lines EE, FF and GG in FIG. 5 (d), respectively. To second aluminum wiring 7
Is used as a mask, until the first aluminum wiring 3 is exposed, the portions other than the second lattice-like CVD oxide film 9 ″ under the second aluminum wiring 7 and the silica coating film 12 are etched. Further, as the etching proceeds, the first aluminum wiring 3 is exposed, and thereafter the lattice-shaped CVD oxide film is formed using the second aluminum wiring 7 and the first aluminum wiring 3 as a mask until the silicon nitride film 2 on the silicon substrate 1 is exposed. 5 ", the silica coating film 10 is etched. Thus, under the second aluminum wiring 7, the silicon nitride film 10, the second columnar CVD oxide film 9, the silicon nitride film 6, and the second columnar insulating film 8, in which the columnar CVD oxide film 5 is online, are formed at a constant pitch. It is formed on a silicon nitride film 2 on a substrate 1.

The region where the second columnar insulating film 8 does not exist is the silica coating film 12 or 11 or the silica coating film 1.
A first aluminum wiring 3 surrounded by 2 and 11 exists. The region where only the first aluminum wiring 3 is present is formed under the first aluminum wiring 3 at a constant pitch on the silicon nitride film 2 on the silicon substrate 1 by the columnar CVD oxide film 5.
Thus, a region of the silica coating film 11 sandwiched between the pillars is formed. Furthermore, by performing isotropic wet etching of hydrofluoric acid or the like for a short time, only the silica coating films 11 and 12 whose etching rate is much faster than the CVD oxide film are etched.

As a result, the portions of the silica coating films 11 and 12 became cavities 13 and were supported by the first aluminum wiring 3 having an air bridge structure supported by the first columnar insulating film 4 and the second columnar insulating film 8. A second aluminum wiring 7 having an air bridge structure is formed. Therefore, the first aluminum wiring 3 and the second aluminum wiring 7 are independently supported by the columnar insulating films 4 and 8 having different heights on the silicon nitride film 2 on the silicon substrate 1, and especially in the wiring having the minimum line width. Since only the space is provided between the first aluminum wiring 3 and the second aluminum wiring 7, the wiring capacity can be greatly reduced.

Next, a three-layer wiring structure according to a second embodiment of the present invention is shown in FIG. The structure up to the second aluminum wiring 7 is the same as that of the first embodiment, but the third aluminum wiring 14 is wired in a direction orthogonal to the second aluminum wiring 7, that is, in the same direction as the first aluminum wiring 3. 1
The wirings are arranged on the same line at the same pitch as the aluminum wiring 3. The third aluminum wiring 14 is composed of a second columnar CVD oxide film 9, a silicon nitride film 10, and a third columnar CVD oxide film 16 formed at the same position as the first columnar insulating film 4 on the first aluminum wiring 3. An air bridge structure in which no insulating film is formed between the third aluminum wiring 14 and between the first aluminum wiring 3 and the second aluminum wiring 7 is formed on the third columnar insulating film 15, and the three layers have very small wiring capacitance. It becomes a wiring structure. However, here, the second aluminum wiring 7 or the third aluminum wiring 14
Is thick, an interlayer insulating film may be formed between the second aluminum wiring 7 and the third aluminum wiring 14 in some cases.

Next, a method of manufacturing a three-layer wiring structure will be described. The steps up to manufacturing the two-layer wiring structure are shown in FIGS.
Are the same as those shown in FIG. Next, as shown in FIG. 8A and FIG. 8B, which are cross-sectional views taken along line HH and line II in FIG. Using a process similar to that of
A D oxide film 5 ″, a second lattice CVD oxide film 9 ″, and a third lattice CVD oxide film 16 ″ that is online and flattened and whose recesses are filled with a silica coating film 17 are formed. After the film 18 and the third aluminum wiring layer are grown, the third aluminum wiring layer and the silicon nitride film 18 are patterned using photolithography and etching techniques, and are patterned on the same line as the first aluminum wiring 3 at the same pitch. 3 Aluminum wiring 14 is formed.

Then, using a process similar to the process of FIG.
An oxide film is left only under the third aluminum wiring 14, the second aluminum wiring 7, and the first aluminum wiring 3 by anisotropic etching of the oxide film from above, and silica is applied at a high etching rate by isotropic wet etching for a short time. Only the film is etched, and FIG. 9 (a), (b), (c)
As shown in the cross-sectional views of the JJ line, the KK line, and the LL line in FIG. 10 respectively, in addition to the first aluminum wiring 3 and the second aluminum wiring 7, Third columnar CV formed at the same position as one columnar insulating film 4
D oxide film 16, silicon nitride film 18, second columnar CVD
Third aluminum wiring 14 is formed on third columnar insulating film 15 made of oxide film 9 and silicon nitride film 10.

Here, when the first aluminum wiring 3 does not exist under the third aluminum wiring 14, the columnar CVD oxide film 5 formed on the silicon nitride film 2 on the silicon substrate 1 at an equal pitch, the silicon nitride Membrane 6, second columnar C
VD oxide film 9, silicon nitride film 10, third columnar CVD
Third aluminum wiring 14 is formed on third columnar insulating film 15 made of oxide film 16 and silicon nitride film 18. It should be noted that a multilayer wiring having an air bridge structure can be manufactured by the same process even when four or more wiring layers are used.

[0026]

As described above, according to the present invention, the first layer wiring is formed on the first columnar insulating film formed at equal pitches on the substrate, and the second layer wiring is formed on the first layer wiring on the substrate. By forming the first pillar-shaped insulating film on the second pillar-shaped insulating film higher than the first pillar-shaped insulating film formed in the region where the wiring is not formed, the first pillar-shaped insulating film except for the wide wiring portion, the contact portion, and the through hole portion is formed.
Both the layer wiring and the second layer wiring are independently connected to each other only by the substrate and the columnar insulating film. An insulating film is not formed between the first layer wiring and the second layer wiring, and an air bridge structure is formed. Can be greatly reduced. Wiring is the same height
It has sufficient strength because it is supported by the columnar insulating film at the same pitch and at the same pitch , and when the upper layer wiring is laid independently for a long time as in the conventional structure, the wiring does not peel off or float, and the step does not occur. Will not occur. Alternatively, even when the lower layer wiring has a large width, the interlayer film is not formed over the entire intersection as in the conventional example, and the capacitance can be further reduced. Also,
Wiring can be formed flat, and it can be used for manufacturing multilayer wiring.
Focus margin and step coverage in the photolithography process
This is advantageous in terms of ledge and the like. Furthermore, when it is not necessary to significantly reduce the wiring capacitance, the distance between the substrate and the first layer wiring, the distance between the substrate and the second layer wiring, Since the distance from the second layer wiring can be reduced, it is easy to planarize when forming the interlayer insulating film, and the aspect ratio of contact holes and through holes can be reduced, and the wiring step coverage of these holes can be reduced. Can be greatly improved without using special techniques such as metal embedding in the hall.

Further, in the manufacturing method of the present invention, the insulating film is patterned by using the lattice mask, the wiring is formed thereon, and then the insulating film is etched to form the columnar insulating film. Therefore, the mask can be shared, and the manufacturing can be simplified. In a grid pattern formed of an insulating film such as a CVD oxide film serving as a columnar insulating film, openings having the same shape are present between the lattices, so that a coating film filling the openings is uniformly formed on the entire surface of the wafer. And the result is that there is no pattern dependency of the film thickness peculiar to the coating film.

[Brief description of the drawings]

FIG. 1 is a perspective view conceptually showing a first embodiment of the present invention.

FIG. 2 is a first view illustrating a method of manufacturing the structure of FIG. 1 in the order of steps;

FIG. 3 is a second view illustrating a method of manufacturing the structure of FIG. 1 in the order of steps;

FIG. 4 is a third view illustrating a method of manufacturing the structure of FIG. 1 in the order of steps;

FIG. 5 is a fourth view illustrating a method of manufacturing the structure of FIG. 1 in the order of steps;

FIG. 6 is a fifth view illustrating a method of manufacturing the structure of FIG. 1 in the order of steps;

FIG. 7 is a perspective view conceptually showing a second embodiment of the present invention.

FIG. 8 is a first view illustrating a method of manufacturing the structure of FIG. 7 in the order of steps;

FIG. 9 is a second view illustrating a method of manufacturing the structure of FIG. 7 in the order of steps;

FIG. 10 is a third view illustrating a method of manufacturing the structure of FIG. 7 in the order of steps;

FIG. 11 is a perspective view conceptually showing an example of a conventional wiring structure.

12 is a diagram showing a method of manufacturing the wiring structure in FIG. 11 in the order of steps;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 1st aluminum wiring 4 1st columnar insulating film 7 2nd aluminum wiring 8 2nd columnar insulating film 13 cavity 14 3rd aluminum wiring 15 3rd columnar insulating film

Claims (2)

(57) [Claims] A first insulating film is formed on a semiconductor substrate in a grid pattern.
Forming, and the lattice pitch and half pitch of the first insulating film.
Forming a first layer wiring at a position shifted by
Forming a second insulating film in the same lattice as the first insulating film
And the pitch and half pitch of the second insulating film
The second layer wiring is shifted in a direction intersecting the first layer wiring at the shifted position.
Forming the first layer wiring and the second layer wiring.
And etching the first and second insulating films.
A semiconductor integrated circuit device characterized by including
Production method. 2. A first insulating film formed on a semiconductor substrate in a lattice pattern.
Forming, and the lattice pitch and half pitch of the first insulating film.
Forming a first layer wiring at a position shifted by
Forming a second insulating film in the same lattice as the first insulating film
And the pitch and half pitch of the second insulating film
The second layer wiring is shifted in a direction intersecting the first layer wiring at the shifted position.
Forming a N-th (N is an odd number of 3 or more)
Forming an insulating film in the same lattice as the first insulating film;
And the N-th insulating film on the N-th insulating film at the same position as the first-layer wiring.
Forming a layer wiring, and forming an (N + 1) th insulating film thereon
Forming the same lattice as the first insulating film;
On the (N + 1) -th insulating film, the (N + 1) -th
Forming a layer wiring, the first layer wiring and the second layer wiring.
Line, Nth layer wiring and (N + 1) th layer wiring as masks
The first, second, Nth, and N + 1th insulating films are etched.
Semiconductor integrated circuit, comprising:
Device manufacturing method.