JPH05235183A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05235183A
JPH05235183A JP7252892A JP7252892A JPH05235183A JP H05235183 A JPH05235183 A JP H05235183A JP 7252892 A JP7252892 A JP 7252892A JP 7252892 A JP7252892 A JP 7252892A JP H05235183 A JPH05235183 A JP H05235183A
Authority
JP
Japan
Prior art keywords
wiring
metal wiring
aerial
film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7252892A
Other languages
Japanese (ja)
Inventor
Akira Mese
章 目瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7252892A priority Critical patent/JPH05235183A/en
Publication of JPH05235183A publication Critical patent/JPH05235183A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To connect wirings at a shortest distance needless of passing through any relay points even if the wiring is a long aerial wiring by providing an insulator strut beneath the aerial metallic wiring. CONSTITUTION:A metallic wiring 2 comprising Ti/Al/Ti/Pt/Au about 500nm thick silicon or gallium arsenic is formed on a semiconductor substrate 1. A strut comprising a silicon film 3, 2mum thick, a silicon film 4 0.5mum thick and a silicon oxide film 5, 2mum thick is formed on a substrate 1. Through these procedures, even a long aerial wiring can be connected at the shortest distance needless of passing through any relay points.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層配線構造を有する
半導体装置に関し、特に、マイクロ波帯以上の高周波数
用もしくは高速スイッチング用に用いられる半導体装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly to a semiconductor device used for high frequencies in the microwave band or higher or for high speed switching.

【0002】[0002]

【従来の技術】マイクロ波帯以上の高い周波数において
は配線の容量およびインダクタンスの影響が著しくな
り、これが信号の伝達の妨げとなるため、しばしば空中
に金属配線を通す手法が用いられる。また、1nsより
短い高速スイッチング動作においても、配線容量等の影
響で動作速度は素子が本来持っている特性まで速くなら
ないことがある。このような場合にも、空中に金属配線
を通す手法が有効となってくる。
2. Description of the Related Art At high frequencies in the microwave band and above, the influence of wiring capacitance and inductance becomes significant, which interferes with signal transmission. Therefore, a method of passing metal wiring through the air is often used. Further, even in a high-speed switching operation shorter than 1 ns, the operating speed may not reach the characteristics originally possessed by the element due to the influence of the wiring capacitance and the like. Even in such a case, the method of passing the metal wiring in the air becomes effective.

【0003】従来の金属配線を空中に通す半導体装置の
多層配線構造は、図5に示すように、シリコンやガリウ
ム・ヒ素等からなる半導体基板1の上に金属配線2が形
成され、基板1および金属配線2上に保護膜として酸化
シリコン膜7が形成され、その酸化シリコン膜7に明け
られたコンタクト孔を介して金属配線2と接続された空
中金属配線6が形成されたものである。
As shown in FIG. 5, a conventional multi-layer wiring structure of a semiconductor device in which metal wiring is passed through the air is such that a metal wiring 2 is formed on a semiconductor substrate 1 made of silicon, gallium arsenide or the like, and the substrate 1 and A silicon oxide film 7 is formed on the metal wiring 2 as a protective film, and an aerial metal wiring 6 connected to the metal wiring 2 through a contact hole formed in the silicon oxide film 7 is formed.

【0004】[0004]

【発明が解決しようとする課題】上述した従来の空中配
線構造では、空中金属配線の支えが両端の2ケ所しかな
いため、空中に通した長さが長くとれず、配線長が長い
場合はその途中で、図5に示すように、中継配線として
の金属配線2に何度も接続しなけらばならない。このた
め空中金属配線のインダクタンスやキャパシタンスが増
え、空中配線のメリットが減殺されてしまっていた。
In the above-described conventional aerial wiring structure, since the support of the aerial metal wiring is only at two places at both ends, the length of the metal wire in the air cannot be long, and if the wiring length is long, the On the way, as shown in FIG. 5, the metal wiring 2 as a relay wiring must be connected many times. For this reason, the inductance and capacitance of the aerial metal wiring have increased, and the merit of the aerial wiring has been diminished.

【0005】また、従来の空中金属配線構造では、ペレ
ットを運ぶ吸着ノズルが上部から接すると空中金属配線
が変形し、下層の金属配線と短絡するという事故が起き
ることがあり、また、短絡事故を起こさないまでも変形
によりインダクタンスやキャパシタンスが増加するた
め、ペレットの取り扱いを自動化することが困難であっ
た。
Further, in the conventional aerial metal wiring structure, when the adsorption nozzle for carrying pellets comes into contact with the nozzle from above, the aerial metal wiring may be deformed to cause a short circuit with the lower layer metal wiring. It is difficult to automate the handling of pellets because the inductance and capacitance increase due to deformation even if they do not occur.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
空中金属配線と、基板または金属配線上の酸化シリコン
膜もしくは窒化シリコン膜との間に、酸化シリコン膜、
窒化シリコン膜等からなる支柱を設けたものである。
The semiconductor device of the present invention comprises:
Between the aerial metal wiring and the silicon oxide film or the silicon nitride film on the substrate or the metal wiring, a silicon oxide film,
It is provided with a pillar made of a silicon nitride film or the like.

【0007】[0007]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は、本発明の第1の実施例を示す断面
図である。シリコンもしくはガリウム・ヒ素等からなる
半導体基板1上に、厚みが500nm程度のTi/Al
/Ti/Pt/Auからなる金属配線2が形成され、基
板上に2μm厚の酸化シリコン膜3、0.5μm厚の窒
化シリコン膜4、2μm厚の酸化シリコン膜5からなる
支柱が形成されている。そして、金属配線2−2間を接
続する空中金属配線6が、この支柱を跨ぐ形状に形成さ
れている。空中金属配線6は、Pt/Auからなり、厚
みはそれぞれ40nm程度と1μm程度であり、その幅
は1乃至数μm程度である。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. On a semiconductor substrate 1 made of silicon, gallium, arsenic or the like, Ti / Al having a thickness of about 500 nm
/ Ti / Pt / Au is formed on the metal wiring 2, and pillars made of a silicon oxide film 3 having a thickness of 2 μm, a silicon nitride film 4 having a thickness of 0.5 μm, and a silicon oxide film 5 having a thickness of 2 μm are formed on the substrate. There is. Then, the aerial metal wiring 6 connecting between the metal wirings 2-2 is formed in a shape straddling the pillar. The air metal wiring 6 is made of Pt / Au and has thicknesses of about 40 nm and about 1 μm, respectively, and its width is about 1 to several μm.

【0008】図2は、本発明の第2の実施例の断面図で
ある。本実施例では、配線層が全部で3層あり、最下層
の金属配線2上には、上部が平坦な酸化シリコン膜7が
1、2μmの膜厚に設けられている。その上にTi/P
t/Auからなる厚さ500nm程度の金属配線2aが
設けられ、その上は膜厚500nmの窒化シリコン膜8
で被覆されている。
FIG. 2 is a sectional view of the second embodiment of the present invention. In this embodiment, there are three wiring layers in total, and the silicon oxide film 7 having a flat upper surface is provided on the lowermost metal wiring 2 to have a film thickness of 1 or 2 μm. Ti / P on it
A metal wiring 2a made of t / Au and having a thickness of about 500 nm is provided, and a silicon nitride film 8 having a thickness of 500 nm is provided on the metal wiring 2a.
Is covered with.

【0009】窒化シリコン膜8上には、膜厚2μm程度
の酸化シリコン膜3と、その上に設けられた約10nm
厚の保護膜9とから構成される支柱が立てられている。
保護膜9はTi/Ptの2層膜で形成されている。空中
金属配線6は窒化シリコン膜8に形成されたコンタクト
孔を介して金属配線2aと接続され、また保護膜9と密
着して形成されている。この空中金属配線の構造は先の
実施例と同様である。
A silicon oxide film 3 having a thickness of about 2 μm is formed on the silicon nitride film 8, and a film having a thickness of about 10 nm is formed thereon.
A pillar composed of a thick protective film 9 is erected.
The protective film 9 is formed of a two-layer film of Ti / Pt. The air metal wiring 6 is connected to the metal wiring 2 a through a contact hole formed in the silicon nitride film 8 and is formed in close contact with the protective film 9. The structure of this aerial metal wiring is similar to that of the previous embodiment.

【0010】図3は、本発明の第3の実施例を示す断面
図である。本実施例では、半導体基板1、金属配線2上
に膜厚2μmの酸化シリコン膜7と膜厚約30nm窒化
シリコン膜8が形成されている。窒化シリコン膜8上に
は膜厚2μmの酸化シリコン膜3からなる支柱が形成さ
れている。この支柱と空中金属配線6との間には狭い間
隙が設けられている。
FIG. 3 is a sectional view showing a third embodiment of the present invention. In this embodiment, a silicon oxide film 7 having a film thickness of 2 μm and a silicon nitride film 8 having a film thickness of about 30 nm are formed on the semiconductor substrate 1 and the metal wiring 2. A pillar made of a silicon oxide film 3 having a film thickness of 2 μm is formed on the silicon nitride film 8. A narrow gap is provided between the pillar and the aerial metal wiring 6.

【0011】図4は、本発明の第4の実施例を示す断面
図である。この実施例では、金属配線2を被覆する酸化
シリコン膜7上に窒化シリコン膜4と酸化シリコン膜5
とからなる支柱が2本立てられている。
FIG. 4 is a sectional view showing a fourth embodiment of the present invention. In this embodiment, the silicon nitride film 4 and the silicon oxide film 5 are formed on the silicon oxide film 7 covering the metal wiring 2.
Two columns composed of and are set up.

【0012】[0012]

【発明の効果】以上説明したように、本発明は、空中金
属配線下に絶縁物の支柱を設けたものであるので、本発
明によれば、長い空中配線でも中継点を経由させる必要
がなくなり、最短距離で配線間を接続することができる
ようになる。従って、本発明によれば、空中配線を低容
量、低インダクタンスに形成することができ、半導体装
置の高周波特性を改善することができる。また、空中配
線に中継点が不要となったことにより、設計の自由度が
増す。さらに、ペレット取り扱い時における空中配線の
変形が起こりにくくなるので、自動化を容易に実施でき
るようになる。
As described above, according to the present invention, the pillars of the insulator are provided under the aerial metal wiring. Therefore, according to the present invention, it is not necessary to pass through the relay point even in the long aerial wiring. , It becomes possible to connect the wires with the shortest distance. Therefore, according to the present invention, the aerial wiring can be formed with low capacitance and low inductance, and the high frequency characteristics of the semiconductor device can be improved. In addition, the freedom of design is increased by eliminating the need for relay points in the aerial wiring. Further, since it is difficult for the aerial wiring to be deformed when handling the pellets, automation can be easily implemented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す断面図。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】本発明の第3の実施例を示す断面図。FIG. 3 is a sectional view showing a third embodiment of the present invention.

【図4】本発明の第4の実施例を示す断面図。FIG. 4 is a sectional view showing a fourth embodiment of the present invention.

【図5】従来例の断面図。FIG. 5 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体基板 2、2a 金属配線 3、5、7 酸化シリコン膜 4、8 窒化シリコン膜 6 空中金属配線 9 保護膜 1 Semiconductor Substrate 2, 2a Metal Wiring 3, 5, 7 Silicon Oxide Film 4, 8 Silicon Nitride Film 6 Aerial Metal Wiring 9 Protective Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 金属配線の一部を空中に通す半導体装置
において、空中金属配線下には絶縁物の支柱が設けられ
ていることを特徴とする半導体装置。
1. A semiconductor device in which a part of a metal wire is passed through the air, wherein a pillar of an insulator is provided under the air metal wire.
JP7252892A 1992-02-21 1992-02-21 Semiconductor device Pending JPH05235183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7252892A JPH05235183A (en) 1992-02-21 1992-02-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7252892A JPH05235183A (en) 1992-02-21 1992-02-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05235183A true JPH05235183A (en) 1993-09-10

Family

ID=13491931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7252892A Pending JPH05235183A (en) 1992-02-21 1992-02-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05235183A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193125A (en) * 1993-12-24 1995-07-28 Nec Corp Semiconductor integrated circuit device and its manufacture
JP2010258202A (en) * 2009-04-24 2010-11-11 Renesas Electronics Corp Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193125A (en) * 1993-12-24 1995-07-28 Nec Corp Semiconductor integrated circuit device and its manufacture
JP2010258202A (en) * 2009-04-24 2010-11-11 Renesas Electronics Corp Semiconductor device and manufacturing method thereof

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