JPH03293728A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03293728A JPH03293728A JP9586290A JP9586290A JPH03293728A JP H03293728 A JPH03293728 A JP H03293728A JP 9586290 A JP9586290 A JP 9586290A JP 9586290 A JP9586290 A JP 9586290A JP H03293728 A JPH03293728 A JP H03293728A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- unconnected
- lower layer
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 230000001788 irregular Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 239000011248 coating agent Substances 0.000 abstract description 7
- 238000000576 coating method Methods 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は多層配線を有する半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device having multilayer wiring.
従来の半導体装置においては、以下のような方法で形成
される。すなわち、第３図（ａ）、■に示すようにシリ
コン基板１上に必要素子を形成した後、この素子を接続
する第１の金属配線、例えばアルミニウム配線３を０．
５Ｐ程度の厚さで配線として必要な分だけ形成する。次
に、配線間絶縁膜として例えば酸化膜５を５０００人程
度成長させた後、平坦化を行うため、塗布膜６を３００
０人程度全面に塗布し、異方性エツチングにより選択的
に残した後、再び例えば酸化膜７を５０００ Ａ程度成
長させる。A conventional semiconductor device is formed by the following method. That is, after forming the necessary elements on the silicon substrate 1 as shown in FIG.
The thickness of about 5P is formed in the amount necessary for wiring. Next, after growing an oxide film 5 of about 5,000 layers as an inter-wiring insulating film, for example, a coating film 6 of 300 layers is grown for planarization.
After applying it to the entire surface and leaving it selectively by anisotropic etching, for example, an oxide film 7 is grown again at a thickness of about 5000 A.
次に、前記第１のアルミニウム配線３と接続するための
スルーホール８を開孔した後、第２の金属配線、例えば
アルミニウム配線９を１μ程度の厚さで形成する。図中
、２は酸化膜である。Next, after forming a through hole 8 for connection to the first aluminum wiring 3, a second metal wiring, for example an aluminum wiring 9, is formed to a thickness of about 1 μm. In the figure, 2 is an oxide film.
〔発明が解決しようとする課厘１
前述した従来の半導体装置では、下層配線である第１ア
ルミニウム配線３は、配線として必要な分だけ形成され
ており、その間隔は最小間隔１．５１１程度から数十μ
までまばらである。[Problem to be Solved by the Invention 1] In the conventional semiconductor device described above, the first aluminum wiring 3, which is the lower layer wiring, is formed as much as necessary as the wiring, and the interval between them is from the minimum interval of about 1.511 to Several tens of μ
It is sparse.
一般に、多層配線を行う場合、下層配線の間隔が広いと
、例えば′塗布膜６で平坦化を行っ７ど場合でも、第３
図（ａ）、（ｂ）に示すように、完全な平坦化ができず
、第２アルミニウム配線９のステップカバレッジに影響
を与える。Generally, when performing multilayer wiring, if the spacing between the lower layer wiring is wide, the third
As shown in FIGS. (a) and (b), complete planarization cannot be achieved, which affects the step coverage of the second aluminum wiring 9.
本発明の目的は前記課題を解決した半導体装置を提供す
ることにある。An object of the present invention is to provide a semiconductor device that solves the above problems.
前記目的を達成するため、本発明に係る半導体装置にお
いては、下層配線と上層配線との組合せからなる多層配
線構造の半導体装置であって、下層配線は、不規則な隙
間箇所に未接続配線を形成し、その上面に形成される配
線層間絶縁膜を平坦化させたものであり、
上層配線は、前記平坦化された配線層間絶縁膜上に形成
されたものである。In order to achieve the above object, the semiconductor device according to the present invention has a multilayer wiring structure consisting of a combination of lower layer wiring and upper layer wiring, and the lower layer wiring has unconnected wiring in irregular gaps. The upper layer wiring is formed on the planarized wiring interlayer insulation film.
〔実施例］ 以下、本発明の一実施例を図により説明する。〔Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図（ａ）は本発明の一実施例を示す平面図、第１図
（ハ）は第１図（ａ）のＡ−Ａ ’線断面図である。FIG. 1(a) is a plan view showing one embodiment of the present invention, and FIG. 1(c) is a sectional view taken along the line AA' in FIG. 1(a).
図において、シリコン基板ｌ上に必要素子が形成され、
素子を接線する被接続第１アルミニウム配線（下層配線
）３．第２アルミニウム配線（上層配線）９が多層構造
に積層形成される。In the figure, necessary elements are formed on a silicon substrate l,
3. Connected first aluminum wiring (lower layer wiring) tangent to the element; A second aluminum wiring (upper layer wiring) 9 is formed in a multilayered structure.
本発明は多層配線のうち下層配線３．３・・・相互間の
不規則な隙間箇所に同一高さの未接続の配線４を形成さ
せて隣接する下層配線３，３相互間の不規則な間隔を狭
ばめることにより、下層配線３，３上に渡って形成され
る配線層間絶縁膜５を平坦化させ、その平坦化された配
線層間絶縁膜５上に上層配線９を積層形成したものであ
る。２は酸化膜である。The present invention forms unconnected wiring 4 of the same height in irregular gaps between the lower wiring 3. By narrowing the interval, the wiring interlayer insulating film 5 formed over the lower layer wirings 3 and 3 was flattened, and the upper layer wiring 9 was laminated on the flattened wiring interlayer insulation film 5. It is something. 2 is an oxide film.
次に半導体装置の形成方法について説明する。Next, a method for forming a semiconductor device will be explained.
シリコン基板ｌ上に必要素子を形成した後、この素子と
接続する第１の金属配線、例えばアルミニウム配線３を
０．５μ程度の厚さで形成する。このとき、本来配線と
して必要な分易外の配線３，３間の不規則な隙間箇所に
も未接続のアルミニウム配線４を同時に設け、下層配線
となるアルミニウム配線３，４の間隔が一様に、例えば
１．５１１程度に狭くなるように形成する。前記未接続
アルミニウム配線４は、配線ピッチに沿って形成するの
が好ましい。After forming the necessary elements on the silicon substrate 1, a first metal wiring, for example, an aluminum wiring 3, connected to the elements is formed with a thickness of about 0.5 μm. At this time, unconnected aluminum wires 4 are also provided at the same time in irregular gaps between the wires 3 and 3 outside of the wiring, which are originally required as wiring, so that the intervals between the aluminum wires 3 and 4, which are the lower layer wires, are uniform. , for example, to have a narrow width of about 1.511. The unconnected aluminum wiring 4 is preferably formed along the wiring pitch.
次に下層配線３，４上に配線層間絶縁膜として酸化膜５
を形成し塗布膜６を塗布し、次にスルーホール８を開孔
した後、上層配線である第２アルミニウム配線９を厚さ
１．０μ程度で形成する。Next, an oxide film 5 is formed as an interlayer insulating film on the lower wirings 3 and 4.
After forming and applying a coating film 6, and then opening a through hole 8, a second aluminum wiring 9, which is an upper layer wiring, is formed with a thickness of about 1.0 μm.
前述した実施例で述べたように未接続のアルミニウム配
線４は、例えば、自動配置配線等を行う場合は、配線ピ
ッチに沿って設け、また、接続された配線３と同一幅で
形成するのが好ましいが、第２図に示すように、未接続
配線４を設けるべき幅が配線ピッチの２つ以上分に相当
する場合には、幅の広い未接続配線４を用いても良い。As described in the above embodiment, when performing automatic placement and wiring, for example, it is recommended that the unconnected aluminum wiring 4 be provided along the wiring pitch and be formed to have the same width as the connected wiring 3. However, as shown in FIG. 2, if the width of the unconnected wiring 4 corresponds to two or more wiring pitches, a wide unconnected wiring 4 may be used.
また、配線層間絶縁膜の形成方法に関しては、前述した
実施例に限られるものではなく、塗布膜６を用いずに単
層膜による形成を行っても良い。Further, the method for forming the wiring interlayer insulating film is not limited to the above-described embodiment, and may be formed using a single layer film without using the coating film 6.
〔発明の効果］
以上説明したように本発明では、配線として用いない未
接続の金属線を、配線として用いる金属線の間に設ける
ことにより、下層配線となる金属線のすき間を狭くし、
その結果その上に形成される配線層間絶縁膜の平坦化を
十分行うことが可能となる。すなわち、狭いすき間の場
合、塗布膜を用いれば完全に埋め込むことが可能となり
、また、塗布膜を用いなくても、単層の絶縁膜の厚さを
厚くすることで同様に埋め込める。その結果として、完
全な平坦性が得られるわけである。[Effects of the Invention] As explained above, in the present invention, by providing unconnected metal wires that are not used as wiring between the metal wires that are used as wiring, the gap between the metal wires that become the lower layer wiring is narrowed,
As a result, it becomes possible to sufficiently planarize the wiring interlayer insulating film formed thereon. That is, in the case of a narrow gap, it is possible to completely fill it by using a coating film, and it is also possible to fill it in the same way without using a coating film by increasing the thickness of a single layer insulating film. The result is perfect flatness.
第１図（ａ）は本発明の一実施例を示す平面図、第１図
（ロ）は第１図（ａ）のＡ−Ａ ′線断面図、第２図は
本発明の別の実施例を示す平面図、第３図（ａ）は従来
例を示す平面図、第３図■は第３図（ａ）のＢ−Ｂ′線
断面図である。
１・・シリコン基板 ２．５．７・・・酸化膜
３．４．９・・・アルミニウム配線 ６・・・塗布膜８
・・・スルーホールFIG. 1(a) is a plan view showing one embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line A-A' in FIG. 1(a), and FIG. 2 is a plan view showing an embodiment of the present invention. 3(a) is a plan view showing a conventional example, and FIG. 3(2) is a sectional view taken along the line B-B' in FIG. 3(a). 1...Silicon substrate 2.5.7...Oxide film 3.4.9...Aluminum wiring 6...Coating film 8
...Through hole
Claims (1)
構造の半導体装置であって、 下層配線は、不規則な隙間箇所に未接続配線を形成し、
その上面に形成される配線層間絶縁膜を平坦化させたも
のであり、 上層配線は、前記平坦化された配線層間絶縁膜上に形成
されたものであることを特徴とする半導体装置。(1) A semiconductor device with a multilayer wiring structure consisting of a combination of lower layer wiring and upper layer wiring, in which the lower layer wiring forms unconnected wiring in irregular gaps,
1. A semiconductor device, wherein a wiring interlayer insulating film formed on an upper surface of the semiconductor device is planarized, and an upper layer wiring is formed on the flattened wiring interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9586290A JPH03293728A (en) | 1990-04-11 | 1990-04-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9586290A JPH03293728A (en) | 1990-04-11 | 1990-04-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03293728A true JPH03293728A (en) | 1991-12-25 |
Family
ID=14149172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9586290A Pending JPH03293728A (en) | 1990-04-11 | 1990-04-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03293728A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313417A (en) * | 1990-07-25 | 1994-05-17 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| JP2009044080A (en) * | 2007-08-10 | 2009-02-26 | Toshiba Corp | Nonvolatile semiconductor memory, and manufacturing method thereof |
-
1990
- 1990-04-11 JP JP9586290A patent/JPH03293728A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313417A (en) * | 1990-07-25 | 1994-05-17 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| JP2009044080A (en) * | 2007-08-10 | 2009-02-26 | Toshiba Corp | Nonvolatile semiconductor memory, and manufacturing method thereof |
| JP4504402B2 (en) * | 2007-08-10 | 2010-07-14 | 株式会社東芝 | Nonvolatile semiconductor memory device |
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