JPS63260054A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize a wiring width and an occupation area of a contact hole formation part, by forming a plurality of wiring layers on a semiconductor substrate through respective layer insulation films and next by connecting the upper and lower parts of these wiring layers to each other on sides of the wiring layers through a common contact. CONSTITUTION:A pattern of a first wiring layer 1 is formed in a prescribed shape on a semiconductor substrate, and a layer insulation film 6 is formed on the first wiring layer 1. In succession, a second wiring layer 3 is formed on this layer insulation film 6 and further a layer insulation film 7 is formed thereon. Next, a contact hole 9 is opened on a prescribed position. When the contact hole 9 is opened in this way, the second wiring layer 3 and the first wiring layer 1 are respectively formed in locally cut shapes. When a reduced- pressure CVD method is used to make a conductive material grow all over the surface of the semiconductor substrate including an inner wall of the contact hole and to fill the contact hole with this conductive material, a common contact is formed to connect the first wiring layer with the second wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a connection structure of multilayer internal wiring.

[Conventional technology]

FIGS. 5(a) and 5(b) are respectively a plan view of a wiring connection part in a conventional semiconductor integrated circuit device and its c-c'
In the cross-sectional view, for example, in the case of a three-chip arrangement, the first wiring layer 1
A first contact hole is provided above and the second wiring layer 3 is connected to it, and then a second contact 4 is provided again on the second wiring 713 and a third wiring layer 5 is connected to it. Take the m-structure. Here, 6 and 7 indicate interlayer insulating films, respectively.

[Problem that the invention seeks to solve]

Therefore, in this conventional connection structure, the line width of the lower layer wiring in the contact hole forming portion is designed to be always larger than the contact hole, taking into account the misalignment during exposure and the amount of overetching during etching. Therefore, where contact holes are formed, the line width of the lower wiring layer becomes wider than the line width of other wiring areas, and the wiring pitch of the lower wiring increases in the contact hole formation area, so high-density wiring is possible. cannot be formed.

Furthermore, as is clear from Fig. 5, if there is an upper layer wiring to be connected, it is necessary to form a contact hole on the lower wiring layer each time, which not only increases the number of manufacturing steps but also requires the formation of contact holes. Since the area also increases each time, the formation of high-density wiring is similarly inhibited. This tendency becomes more pronounced as wiring becomes more multilayered.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device having a wiring connection structure that can minimize the wiring width of a contact hole forming portion and the area occupied by the wiring.

[Means for solving problems]

According to the present invention, a semiconductor 4A integrated circuit device includes a semiconductor substrate, a plurality of wiring layers each formed on the semiconductor substrate via an interlayer insulating film, and at least one pair of upper and lower wirings of the wiring layer. and a wiring connection portion that connects the layers to each other via a common contact on the side surface of the wiring layer.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIGS. 1(a), 1(b), and 1(c) are a plan view, a sectional view taken along the line AA', and a connection state diagram, respectively, of a wiring connection portion showing one embodiment of the present invention.

According to this embodiment, the semiconductor integrated circuit device of the present invention has a first
．． Second. Each third wiring layer 1.3.5 and the third wiring layer 5
and a common contact 8 formed in the same process. Here, 6 and 7 are interlayer insulating films, respectively, as in the conventional case. As is clear from this embodiment, all the wiring layers to be connected share one contact 8 and are connected to each other only by the side portions. Therefore, the connection between the wires can be completed with an extremely small number of steps without increasing the line width of the lower layer wires or increasing the occupied area as in the prior art. That is, the manufacturing process itself of the semiconductor integrated circuit device is also simplified.

FIGS. 2(a) and 2(b) are partial process diagrams for manufacturing the above embodiments, and as shown in FIG. 1(a), the first wiring layer 1 is formed on a semiconductor substrate (not shown). A pattern is first formed into a predetermined shape, and then a glabellar insulating film 6 is formed on the pattern. Next, a second wiring layer 3 is formed in a predetermined pattern on this glabellar insulating film 6, and a glabellar insulating film 7 is formed on top of the second wiring layer 3. Here, a contact hole 9 is opened at a predetermined position as shown in FIG. 1(b). At this time, the interlayer insulating film 7 is first anisotropically etched with a carbon tetrachloride (CF4) gas, then the second wiring layer 3 is anisotropically etched with a chlorine (CI) gas, and then The interlayer insulating film 6 and the first wiring layer 1 are made of carbon tetrachloride (
Anisotropic etching is performed sequentially in the same manner using CF4)-based and chlorine (ce)-based gases. When the contact hole 9 is opened in this manner, a portion of the second wiring layer 3 and the first wiring N1 are respectively cut off [see FIG. 1(c)].

Therefore, for example, if a conductive material is grown on the entire surface of the semiconductor substrate including the inner wall of the contact hole 9 using a low pressure CVD method and the inside of the contact hole 9 is filled with the conductive material, the common contact 8 is formed and the first and second The distance between the wiring layers is shown in Figure 1 (b
) and (C). Therefore, by patterning this third conductive material into a predetermined shape, the third wiring layer 5 is formed.

In the above embodiment, the case of a three-layer wiring structure was described, but it is of course possible to implement the case of a multilayer wiring of three or more layers, and it is also possible to form each wiring layer with the same material or with each other. It is also possible to form it from different materials.

FIGS. 3(a) and 3(b) are a plan view and a cross-sectional view taken along the line BB' of a wiring connection portion showing another embodiment of the present invention, respectively. In the previous embodiment, the first degree second degree. Although the case where all the third wiring layers are connected has been described, in this embodiment, the connections are made in the first... A case is shown in which it is limited to only between the second wiring layers. That is, according to this embodiment, the first and second wiring layers 1 and 3 are connected to the common contact 8'' as in the previous embodiment.
However, the third wiring layer is formed independently on the relatively thin insulating film 10 formed on the interlayer insulating film 7. The case where the position of the wiring layer 5 is slightly shifted is shown, but of course the first. If such a connection structure is adopted, which may be located on the second common contact 8', an increase in the area occupied by the contact formation area can be extremely effectively suppressed, and as in the previous embodiment, the wiring density can be improved. The structure of this embodiment, which can produce great effects, can also be easily formed by the following procedure.

FIGS. 4(a) to 4(b) are partial process diagrams for manufacturing the above-mentioned other embodiment of the present invention.

The first layer is laminated as in the previous example. Contact holes (not shown) are selectively opened in the second wiring layers 1 and 3 and the two interlayer insulators M6 and 7, and the contact holes are filled with a conductive material 11. Next, this conductive substance 1
A photoresist 12 is coated on the substrate 1 (see FIG. 4), and the entire surface of the substrate is anisotropically etched. At this time, the conductive material 11 in the contact hole is etched so as to remain lower than the upper surface of the interlayer insulating film 7 and higher than the upper surface of the second conductive layer 3, thereby forming a common contact 8'. here,
A silica film 13 is applied to the entire surface of the substrate so as to fill the four parts above the formed common contact 8 (see Fig. 4).Next, this is baked to convert it into an insulating film 10, and a third wiring layer is formed again. 5, the structure of this embodiment is completed.

〔Effect of the invention〕

As described above in detail, the semiconductor integrated circuit device of the present invention includes a wiring connection structure that connects the upper wiring layer and the lower wiring layer at their respective side portions through the common contact.
There is no need to widen the width of the lower wiring layer when forming contact holes as in the conventional method, and the number of contact holes in multilayer wiring of three or more layers can be significantly reduced.
Since not only the wiring pitch but also the area occupied by the contact hole forming portion can be significantly reduced, a remarkable effect can be achieved in realizing high-density wiring.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are a plan view, an AA' cross-sectional view and a connection state diagram of a wiring connection part showing one embodiment of the present invention, and FIGS. 2(a) to (b) are 3(a) to 3(b) are partial process diagrams for manufacturing the above embodiment, and FIG. (a) to (b) are partial process diagrams for manufacturing the above-mentioned other embodiments of the present invention, and Fig. 5 (a) and (b)
1A and 1B are a plan view and a cross-sectional view of a wiring connection portion in a conventional semiconductor integrated circuit device, respectively. 1... First interconnection layer, 3... Second interconnection layer, 5
...Third wiring layer, 6, 7... Interlayer insulating film, 8, 8
'...Common contact, 9...Contact hole, 10
... Insulating film, 11 ... Conductive substance, 12 ... 7 Otoresist, 13 ... Silica film. Agent: Susumu Uchihara, patent attorney. Pit Z diagram (υ) Kudzu 3 bad

Claims (1)

[Claims] A semiconductor substrate, a plurality of wiring layers formed on the semiconductor substrate through interlayer insulating films, and at least one pair of upper and lower wiring layers of the wiring layers are connected to each other via a common contact at the side surfaces of the wiring layers. 1. A semiconductor integrated circuit device, comprising: a wiring connection portion that connects the device.