JPS6255962A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6255962A JPS6255962A JP19632985A JP19632985A JPS6255962A JP S6255962 A JPS6255962 A JP S6255962A JP 19632985 A JP19632985 A JP 19632985A JP 19632985 A JP19632985 A JP 19632985A JP S6255962 A JPS6255962 A JP S6255962A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- aluminum
- approx
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特に三層構造の金属配線を億えた
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a semiconductor device, and particularly to a semiconductor device including a three-layer metal wiring structure.
従来の技術
従来の半導体装置は第２図に承りように、シリコン半導
体基板１上にアルミニウムとシリコンとの合金膜（ＡＱ
−３１ｖ）２を付着後、シンターづる。この結束、シリ
コンのアルミニウム中への拡散を減少させ、従ってアル
ミニウムがシリコンの拡散跡に浸透して、接合を短絡刃
る等の事故を未然に防止できる。2. Prior Art As shown in FIG. 2, a conventional semiconductor device includes an alloy film of aluminum and silicon (AQ
-31v) After attaching 2, sinter. This bundling reduces the diffusion of silicon into the aluminum, thereby preventing accidents such as short-circuiting of the bond due to aluminum penetrating into the silicon diffusion trace.
発明が解決しようとｌる問題点
半導体素子の高集積化に伴い、配線も１μｔからサブミ
クロンへと非常に細く形成していかなければならない。Problems to be Solved by the Invention As semiconductor devices become more highly integrated, wiring must also be made extremely thin, from 1 .mu.t to submicron.
従来のような構造ではアルミニウム中のシリコンがシン
ターにより偏析し、非常に細い配線では断線が起ったり
抵抗が高くなるという問題がある。In conventional structures, the silicon in the aluminum segregates due to sintering, causing problems such as disconnection and high resistance in very thin interconnects.
本発明はこのような問題点を解決するもので、一様な抵
抗を持った配線が得られ、断線等を防止できるようにす
ることを目的とするものである。The present invention is intended to solve these problems, and aims to provide wiring with uniform resistance and to prevent wire breakage and the like.
問題点を解決するための手段
この問題点を解決するために本発明は、シリコン基板上
に下層がアルミニウムとシリコンの合金膜、中間層がシ
リコン膜、上層がアルミニウム膜より構成されている金
属配線を有するものである。Means for Solving the Problem In order to solve this problem, the present invention provides metal wiring on a silicon substrate, the lower layer of which is an alloy film of aluminum and silicon, the middle layer of which is a silicon film, and the upper layer of which is an aluminum film. It has the following.
作用
この構成により、従来の方法で起ったシリコンの偏析に
よる金属配線の断線を防ぐことができ、−揉な抵抗を持
った金属配線を得ることができるようになった。Function: With this configuration, it is possible to prevent disconnection of the metal wiring due to segregation of silicon that occurs in the conventional method, and it has become possible to obtain a metal wiring with a reasonable resistance.
実施例
以下、本発明の一実施例について、図面（第１図）に基
づいて説明する。EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings (FIG. 1).
先ず、第１図（＾）に示すように、シリコン基板１１上
にスパッタ蒸着法によりＡｊ２−８ｉ（１％）膜１２を
厚さ１０００人程度形成し、次に第１図（８）に示すよ
うにへΩ−３ｉ膜１２上にシリコン膜１３を蒸着により
厚キ５００形成度形成し、最後に第１図（Ｃ）に示すよ
うにシリコン基板１１上に高純度のアルミニウムｒｆＡ
１４を蒸着により厚さ１ｏｏｏｏ人程度形成する。First, as shown in FIG. 1(^), an Aj2-8i (1%) film 12 with a thickness of about 1,000 layers is formed on a silicon substrate 11 by sputter deposition, and then as shown in FIG. 1(8). Then, a silicon film 13 is formed on the Ω-3i film 12 to a thickness of 500 mm by vapor deposition, and finally, as shown in FIG.
14 is formed to a thickness of about 100 mm by vapor deposition.
その後４５０℃で３０分間シンターを行なう。これによ
り本発明の半導体装置が得られた。Thereafter, sintering is performed at 450°C for 30 minutes. As a result, a semiconductor device of the present invention was obtained.
発明の効宋
以上のように本発明によれば、中間層のシリコン膜から
下層のＡρ−８ｉ膜にシリコンが拡散するために、その
分基板から下層のＡρ−３ｉ膜に対するシリコンの拡散
が抑えられて、アルミニウムの基板の浸透による接合乃
絡事故を減少させることができる。又、上層のアルミニ
ウム膜はシリコンを含／Ｖでいないので、中間層のシリ
コンの拡散の程度では従来ＡＪ２−８ｉ膜に見られたＩ
Ｉｌ線化に伴うシリコンの偏析に起因する断線、局所的
高抵抗化の問題が生じることがなく、一様な抵抗を持つ
金屑配線を形成できる。Effects of the Invention Song As described above, according to the present invention, since silicon diffuses from the intermediate silicon film to the lower Aρ-8i film, the diffusion of silicon from the substrate to the lower Aρ-3i film is suppressed. As a result, it is possible to reduce bonding accidents caused by penetration of the aluminum substrate. In addition, since the upper aluminum film does not contain silicon and does not have a /V, the degree of diffusion of silicon in the intermediate layer is lower than that seen in the conventional AJ2-8i film.
This eliminates the problems of wire breakage and localized high resistance caused by segregation of silicon that accompanies the use of Il wires, and it is possible to form gold scrap wiring with uniform resistance.
第１図（Ａ）〜（Ｃ）は本発明の一実施例による単導体
装置の製造工程図、第２図は従来例を示す断面図である
。
１１・・・シリコン基板、１２・・・Δに一８１膜、１
３・・・シリコン膜、１４・・・アルミニウム膜
代理人 森 本 残 弘
第１図
第２図1A to 1C are manufacturing process diagrams of a single conductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. 11...Silicon substrate, 12...181 film on Δ, 1
3... Silicon film, 14... Aluminum film agent Hiroshi Morimoto Figure 1 Figure 2
Claims (1)
合金膜、中間層がシリコン膜、上層がアルミニウム膜よ
り構成されている金属配線を有する半導体装置。1. A semiconductor device having metal wiring on a silicon substrate, the lower layer being an alloy film of aluminum and silicon, the middle layer being a silicon film, and the upper layer being an aluminum film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19632985A JPS6255962A (en) | 1985-09-05 | 1985-09-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19632985A JPS6255962A (en) | 1985-09-05 | 1985-09-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6255962A true JPS6255962A (en) | 1987-03-11 |
Family
ID=16356011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19632985A Pending JPS6255962A (en) | 1985-09-05 | 1985-09-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6255962A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01130544A (en) * | 1987-11-17 | 1989-05-23 | Nec Corp | Wiring of semiconductor device |
-
1985
- 1985-09-05 JP JP19632985A patent/JPS6255962A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01130544A (en) * | 1987-11-17 | 1989-05-23 | Nec Corp | Wiring of semiconductor device |
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