JPH05109845A - Semiconductor device - Google Patents

Abstract

PURPOSE:To put the formation area of a vacant pad to effective use and enable the formation of a property evaluation element by providing the property evaluation element in place of a vacant pad, in at least one place of the regions where vacant pads are made of the surface of a semiconductor substrate. CONSTITUTION:Though the basic cell of a semiconductor chip 1 is made, an islandshaped impurity diffusion layer 2 is made all in the making position of the pad for signal takeout at the surface of a semiconductor substrate at formation of the impurity diffusion layer formation. After formation of the basic cell, a PSG film is stacked, and contact holes 3 are made similar to an inner element at both ends of the island-shaped diffusion layer 2 lying in the position in which to form a contact resistance evaluation element in place of a vacant pad. And, the island-shaped impurity diffusion layers are wired in series, and patterning is performed so that a probe needle pad may be made at both ends. That is, the contact resistance evaluation element is made in the position to form a vacant pad. Hereby, an required element for property evaluation can be formed even if integration advances.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device requiring a characteristic evaluation element.

[0002]

2. Description of the Related Art Generally, a semiconductor device having a gate array, a standard cell or the like has a variety of designs as a device by having a regular element structure in a chip and changing only the connection with an external electrode. I am trying to get it. In the above semiconductor device, in order to enable various designs, as shown in FIG.
A large number of signal extraction pads 14 are provided in advance, and some of the signal extraction pads 1 are provided depending on the design.
A signal lead-out line 15 connected to the external electrode is bonded to 4. Therefore, the empty pad 18 that does not necessarily need to be connected to the external electrode is generated.

[0003]

In recent years, in a semiconductor device having a gate array or a standard cell, high integration and diversification of input / output terminals are progressing, and a place for forming a characteristic evaluation element or an alignment mark on a semiconductor chip is extremely large. It is becoming narrower. However, due to the complexity of semiconductor processes and the ease of failure analysis, there is an increasing need to provide a characteristic evaluation element on a chip. However, for the above reasons, there is a problem in that all the required characteristic evaluation elements cannot be formed in the chip.

[0004]

The semiconductor device of the present invention comprises:
At least one of the positions where empty pads are placed,
A characteristic evaluation element is provided instead of the empty pad.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a first embodiment of the present invention, showing a case where a contact resistance evaluation element is formed.

First, a basic cell is formed on the semiconductor chip 1 by the existing method. When the impurity diffusion layer is formed, the island-shaped impurity diffusion layer 2 is also formed at all signal extraction pad formation positions on the surface of the semiconductor substrate. After forming the basic cell, the PSG film is applied to about 5
Then, a contact hole 3 similar to the internal element is formed at both ends of the island-shaped impurity diffusion layer 2 at a position where a contact resistance evaluation element is to be formed instead of an empty pad by using a photolithography technique. Form.
Next, in order to form a metal wiring, for example, aluminum is deposited by sputtering to a thickness of about 1.0 μm, and the island-shaped impurity diffusion layer 2 having the contact holes 3 formed therein is connected in series by using a photolithography technique. The patterning is performed so that the probe pads (about 60 μm × 60 μm) are formed on both ends thereof.

As described above, according to the first embodiment, the contact resistance evaluation element can be formed at the position where the conventional empty pad is formed.

Although the contact resistance evaluation element is formed in the first embodiment, the island-shaped impurity diffusion layer 2 is formed in the second embodiment.
Instead, an island-shaped polysilicon layer is formed. Therefore, a contact resistance evaluation element on the polysilicon layer can also be formed.

In the first embodiment, the single layer metal wiring is described, but in the semiconductor device having the multilayer wiring structure as the third embodiment, the interlayer connection hole evaluation element is formed instead of the empty pad. It is also possible.

[0010]

As described above, according to the present invention, by utilizing the space of the empty pad, it is possible to form an element for characteristic evaluation which is required even when high integration and other pins are advanced.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing an example of a conventional semiconductor device.

[Explanation of symbols]

 1,11 Semiconductor chip 2 Island-like impurity diffusion layer 3 Contact hole 4,14 Signal extraction pad 5,15 Signal extraction line 6 Probe pad 7 Wiring metal 18 Empty pad

Claims (1)

[Claims] 1. A semiconductor device comprising a characteristic evaluation element provided at least at one location in a region where an empty pad is formed on the surface of a semiconductor substrate.