JPH02178942A - Semiconductor device having multilayer interconnection structure - Google Patents
Semiconductor device having multilayer interconnection structureInfo
- Publication number
- JPH02178942A JPH02178942A JP33151588A JP33151588A JPH02178942A JP H02178942 A JPH02178942 A JP H02178942A JP 33151588 A JP33151588 A JP 33151588A JP 33151588 A JP33151588 A JP 33151588A JP H02178942 A JPH02178942 A JP H02178942A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- polycrystalline silicon
- semiconductor device
- analysis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000000523 sample Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 22
- 238000004458 analytical method Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線構造半導体装置に関し、特に多結晶ポ
リシリコン配線及び上層に２つのアルミニウム配線層を
存する多層配線構造半導体装置の解析用探針接触部に関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device with a multilayer wiring structure, and in particular to a probe for analyzing a semiconductor device with a multilayer wiring structure that has a polycrystalline polysilicon wiring and two upper aluminum wiring layers. Regarding contact parts.
半導体装置の開発過程において発生ずるさまざまな不具
合を解析するためには、半導体装置の内部配線上の信号
を測定する必要がある。この測定は通常は微小な針（探
針）を内部配線に当てて行なうため、測定する配線の解
析用探針接触部は針を当てることかできる最上層の配線
を使用するようになっていた。例えは第４図に示すよう
に配線層として多結晶シリコン層］−１〜１−４とその
」二層に２つのアルミニウム層２−１〜ｌ−３，３を有
する多層配線構造半導体装置においては、配線の解析用
探針接触部は、多結晶シリコン層１−１〜１−４（内部
配線）とそれぞれのコンタク１へ六８−１〜８−４で接
続された最」二層のアルミニウム層（第２のアルミニウ
ム層）からなるコンタク１〜パツドからなっている。In order to analyze various defects that occur during the development process of semiconductor devices, it is necessary to measure signals on the internal wiring of the semiconductor device. This measurement is usually performed by applying a minute needle (probe) to the internal wiring, so the top layer of wiring that can be touched with the probe is used as the contact part of the analysis probe of the wiring to be measured. . For example, as shown in FIG. 4, in a multilayer wiring structure semiconductor device having polycrystalline silicon layers]-1 to 1-4 and two aluminum layers 2-1 to 1-3, 3 as wiring layers, as shown in FIG. The probe contact portion for wiring analysis is connected to the polycrystalline silicon layers 1-1 to 1-4 (internal wiring) and the two layers connected to each contact 1 by 68-1 to 8-4. It consists of contacts 1 to pads made of an aluminum layer (second aluminum layer).
上述した従来の多層配線構造半導体装置において解析用
探針接触部は最上層の第２のアルミニウム層で形成され
ているため、解析対象となる配線は多結晶シリコン層及
び第１のアルミニウム層だ（すである場合であっても、
解析用探針接触部として第２のアルミニウム層を含まな
ければならない。従って第１のアルミニウム層と第２の
アルミニウム層をつなぐコンタクトか必要てあり、配線
領域の増大、配線自由度の低下という欠点がある。 本
発明の目的はこのような欠点のない多層配線構造半導体
装置を提供することにある。In the conventional multilayer wiring structure semiconductor device described above, the analysis probe contact part is formed of the second aluminum layer on the top layer, so the wiring to be analyzed is the polycrystalline silicon layer and the first aluminum layer ( Even if
A second aluminum layer must be included as an analytical probe contact. Therefore, a contact is required to connect the first aluminum layer and the second aluminum layer, which has the disadvantage of increasing the wiring area and reducing the degree of freedom in wiring. An object of the present invention is to provide a multilayer wiring structure semiconductor device free from such drawbacks.
本発明の多層配線構造半導体装置は、多結晶シリコン又
は金属シリサイドからなる内部配線を覆う絶縁層に開口
を設けて前記内部配線の所定箇所を露出させた解析用探
針接触部を備えているというものである。The multilayer wiring structure semiconductor device of the present invention is said to be equipped with an analytical probe contact portion that exposes a predetermined portion of the internal wiring by forming an opening in an insulating layer covering the internal wiring made of polycrystalline silicon or metal silicide. It is something.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の第１の実施例を示す配線レイア
ウト図、第１図（ｂ）は第１図（ａ）のＹ−Ｙ’線相当
部て切断した半導体チップの断面図である。FIG. 1(a) is a wiring layout diagram showing a first embodiment of the present invention, and FIG. 1(b) is a cross-sectional view of the semiconductor chip taken along the line Y-Y' in FIG. 1(a). It is.
この実施例は、解析用探針接触部として多結晶シリコン
層］−０１−１〜］、 Ｏ］、−３＜内部配線）上の絶
縁層（第１の絶縁層１０６．第２の絶縁層１０７）に平
面形状か長方形の開口１０４を設げたものである。In this example, insulating layers (first insulating layer 106, second insulating layer 107) is provided with a planar or rectangular opening 104.
次に、この実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.
第２図（ａ）〜（ｃ）は第１の実施例の製造方法を説明
するための工程順に配置した半導体チップの断面図であ
る。FIGS. 2(a) to 2(c) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment.
基板コ０５（半導体基板に素子分離絶縁膜や拡散層等を
設けたもの）上に厚さ４００〜６００ｎｍで、所定形状
にパターニングした多結晶シリコン層１０１−１〜１０
１−４．厚さ１〜１．２μｍのＰＳＧ（リンケイ酸カラ
ス）等の第１−の絶縁層１．０６を形成したのち、解析
に必要な多結晶シリコン層上の第１の絶縁層を除去し、
厚さ１μｍの第１のアルミニウム層１．０２−１を形成
する。次に所定形状にパターニング゛して配線用の第１
−のアルミニウム層１０２−１〜１．０２−３を形成す
る。このときアルミニウム用のＣＣ，＆、系のエツチン
グカスは多結晶シリコンと１０倍程度の選択比をもつた
め、前述の第１の絶縁膜を除去した部分ては、第１のア
ルミニウム層はエツチングされ、多結晶シリコン層か露
出しほとんどそのまま残る。その後、厚さ１〜５μｍの
ポリイミド等の平坦性の良い第２の絶縁層１０７を形成
する（第２図（ｂ））。次に前述の多結晶シリコン層上
の第２の絶縁層１０７を除去して開口１０４を形成した
後、厚さ１μｍの第２のアルミニウム層１０３を形成す
る（第２図（ｃ））。最後に第２のアルミニウム層１０
３をパターニングしてアルミニウム配線層とするととも
に開口１０４部に多結晶シリコン層１０１−１〜１０
］、 −３を露出させて残す（第１図（ａ）、（ｂ））
。Polycrystalline silicon layers 101-1 to 10 which are 400 to 600 nm thick and patterned into a predetermined shape on a substrate 05 (a semiconductor substrate provided with an element isolation insulating film, a diffusion layer, etc.)
1-4. After forming a first insulating layer 1.06 of PSG (phosphosilicate glass) or the like with a thickness of 1 to 1.2 μm, the first insulating layer on the polycrystalline silicon layer necessary for analysis is removed,
A first aluminum layer 1.02-1 with a thickness of 1 μm is formed. Next, it is patterned into a predetermined shape and the first
- aluminum layers 102-1 to 1.02-3 are formed. At this time, the CC, &, system etching residue for aluminum has a selectivity of about 10 times that of polycrystalline silicon, so the first aluminum layer is not etched in the area where the first insulating film mentioned above has been removed. , the polycrystalline silicon layer remains exposed and almost intact. Thereafter, a second insulating layer 107 of polyimide or the like having a thickness of 1 to 5 μm and having good flatness is formed (FIG. 2(b)). Next, after removing the second insulating layer 107 on the polycrystalline silicon layer to form an opening 104, a second aluminum layer 103 with a thickness of 1 μm is formed (FIG. 2(c)). Finally a second aluminum layer 10
3 is patterned to form an aluminum wiring layer, and polycrystalline silicon layers 101-1 to 10 are formed in the opening 104.
], -3 are left exposed (Fig. 1 (a), (b))
.
内部配線である多結晶シリコン層１−０１−１〜１．０
１−３の一部分を露出させるだけであるのて、配線領域
の増大、配線自由度の低下をほとんど伴うことなく、解
析用探針接触部を設けることができる。Polycrystalline silicon layer 1-01-1 to 1.0 as internal wiring
Since only a portion of the probe 1-3 is exposed, the analytical probe contact portion can be provided without increasing the wiring area or reducing the degree of freedom of the wiring.
第３図（ａ＞は本発明の第２の実施例を示す配線レイア
ウト図、第３図（ｂ）は第３図（ａ）のＹ−Ｙ′線相当
部で切断した半導体チップの断面図である。FIG. 3(a) is a wiring layout diagram showing a second embodiment of the present invention, and FIG. 3(b) is a cross-sectional view of the semiconductor chip taken along the line Y-Y' in FIG. 3(a). It is.
この実施例は、第１の多結晶シリコン層２０Ｆ、−１，
，２０］、−２、第２の多結晶シリコン層２１０−１〜
２１０〜３、第１のアルミニウム層２０２−］、、２０
２−２、第２のアルミニウム層２０３を有する。第１と
第２の多結晶シリコン層の間の絶縁層２１１は厚さ３０
〜５０ｎｍの酸化シリコン膜である。第］、第２の多結
晶シリコン層２０１−２．２１０−３はそれぞれ第１の
アルミニウム層２０２−１，２０２’−２と接続されて
いる。この実施例では多結晶シリコン層か２層あるが、
とちらも解析用探針接触部として使用できるため、配線
自由度か一層向上する利点がある。In this embodiment, first polycrystalline silicon layers 20F, -1,
, 20], -2, second polycrystalline silicon layer 210-1~
210-3, first aluminum layer 202-], 20
2-2, it has a second aluminum layer 203. The insulating layer 211 between the first and second polycrystalline silicon layers has a thickness of 30 mm.
It is a silicon oxide film with a thickness of ~50 nm. The second polycrystalline silicon layers 201-2 and 210-3 are connected to the first aluminum layers 202-1 and 202'-2, respectively. In this example, there are two polycrystalline silicon layers,
Since both can be used as the analytical probe contact part, there is an advantage that the degree of freedom in wiring is further improved.
以」二の説明において、多結晶シリコン層の代りに金属
シリサイド層を使用することができるのはいうまでもな
い。In the following explanation, it goes without saying that a metal silicide layer can be used instead of the polycrystalline silicon layer.
以上説明したように本発明は、内部配線を構成する多結
晶シリコン層又は金属シリサイド層上の絶縁層に開口を
設けて解析用探針接触部とすることにより、解析用配線
が第２のアルミニウム層を含む必要がないため、回路機
能上必要のないコンタク１へをなくし、多層配線構造半
導体装置の配線領域の増大、配線自由度の低下を防くこ
とかできる効果かある。As explained above, the present invention provides an opening in the insulating layer on the polycrystalline silicon layer or metal silicide layer constituting the internal wiring to serve as the analytical probe contact part, so that the analytical wiring can be connected to the second aluminum layer. Since there is no need to include a layer, it is possible to eliminate contacts 1 that are not necessary for the circuit function, and to prevent an increase in the wiring area of a multilayer wiring structure semiconductor device and a decrease in the degree of freedom in wiring.
第１図（ａ、 ）は本発明の第１の実施例を示す配線レ
イアウト図、第１図（ｂ）は第１１図（ａ）のＹ−Ｙ′
線線素当部切断した半導体チップの断面図、第２図（ａ
）〜（ｃ）は第１の実施例の製造方法を説明するための
工程順に配置した半導体チップの断面図、第３図（ａ）
は第２の実施例を示す配線レイアウト図、第３図（ｂ）
は第３図（ａ＞のＹ−Ｙ′線線素当部切断した半導体チ
ップの断面図、第４図は従来例を示す配線１４７９１〜
図である。
１−１〜１．−／ｌ−，１０１−１〜１０１−４ ・多
結晶シリコン層、２０１．−１，２０１−２・・第１の
多結晶シリコン層、２−］］〜２−３．１．０２１〜１
０２−３２０２−１〜２０２−２・・・第１のアルミニ
ウム層、３．１．０３，２０Ｂ第２のアルミニウム層、
１．０４，２０４・開口、１．０５，２０５・・・基板
、１．０６，２０６・・・第１の絶縁層、１０７，２０
７・・・第２の絶縁層、８−１〜８．−４ １０８ ２
０８−１，２０８−２・・・コンタクト穴、９−１〜９
−４・・・コンタク１〜パツド、２１０−］−〜２ ］
−０−３・・第２の多結晶シリコン層。1(a,) are wiring layout diagrams showing the first embodiment of the present invention, and FIG. 1(b) is Y-Y' of FIG. 11(a).
A cross-sectional view of the semiconductor chip cut at the wire element contact part, Fig. 2 (a
) to (c) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment, and FIG. 3(a)
is a wiring layout diagram showing the second embodiment, FIG. 3(b)
Figure 3 is a cross-sectional view of the semiconductor chip cut at the line Y-Y' line element abutment part of Figure 3 (a), Figure 4 is a diagram showing the conventional example of wiring 14791~
It is a diagram. 1-1~1. -/l-, 101-1 to 101-4 - Polycrystalline silicon layer, 201. -1,201-2...first polycrystalline silicon layer, 2-]]~2-3.1.021~1
02-3202-1 to 202-2... first aluminum layer, 3.1.03, 20B second aluminum layer,
1.04,204・Opening, 1.05,205・Substrate, 1.06,206・First insulating layer, 107,20
7... Second insulating layer, 8-1 to 8. -4 108 2
08-1, 208-2...Contact hole, 9-1 to 9
-4...Contact 1~pad, 210-]-~2]
-0-3...Second polycrystalline silicon layer.
Claims (1)
を覆う絶縁層に開口を設けて前記内部配線の所定箇所を
露出させた解析用探針接触部を備えていることを特徴と
する多層配線構造半導体装置。A semiconductor device with a multilayer wiring structure, characterized in that it is equipped with an analytical probe contact portion that has an opening in an insulating layer covering internal wiring made of polycrystalline silicon or metal silicide to expose a predetermined portion of the internal wiring. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33151588A JPH02178942A (en) | 1988-12-29 | 1988-12-29 | Semiconductor device having multilayer interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33151588A JPH02178942A (en) | 1988-12-29 | 1988-12-29 | Semiconductor device having multilayer interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02178942A true JPH02178942A (en) | 1990-07-11 |
Family
ID=18244509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33151588A Pending JPH02178942A (en) | 1988-12-29 | 1988-12-29 | Semiconductor device having multilayer interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02178942A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120309A (en) * | 1992-09-30 | 1994-04-28 | Nippon Steel Corp | Semiconductor integrated circuit and test method therefor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57106143A (en) * | 1980-12-24 | 1982-07-01 | Hitachi Ltd | Semiconductor chip |
-
1988
- 1988-12-29 JP JP33151588A patent/JPH02178942A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57106143A (en) * | 1980-12-24 | 1982-07-01 | Hitachi Ltd | Semiconductor chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120309A (en) * | 1992-09-30 | 1994-04-28 | Nippon Steel Corp | Semiconductor integrated circuit and test method therefor |
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