JP2551077B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2551077B2 JP2551077B2 JP63014302A JP1430288A JP2551077B2 JP 2551077 B2 JP2551077 B2 JP 2551077B2 JP 63014302 A JP63014302 A JP 63014302A JP 1430288 A JP1430288 A JP 1430288A JP 2551077 B2 JP2551077 B2 JP 2551077B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- insulating film
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路装置に関し、特に、配線層
の層構成方式に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a layer structure system of wiring layers.
従来の技術 従来、半導体集積回路装置の素子および回路間を接続
する層配線は、例えば第２図に示す如く、単独の二層配
線構造を採る場合に、基板１上に下層配線２を、その上
に層間絶縁膜３を成膜し、その上に上層配線４を配置す
る構造となっていた。2. Description of the Related Art Conventionally, when layer wirings connecting elements and circuits of a semiconductor integrated circuit device have a single two-layer wiring structure as shown in FIG. 2, for example, a lower layer wiring 2 is formed on a substrate 1. The structure is such that the interlayer insulating film 3 is formed thereon and the upper layer wiring 4 is arranged thereon.
発明が解決しようとする課題点 上述した従来の層配線においては、下層配線２の段差
部における上層配線４の段線あるいは層間絶縁膜３のカ
バレッジ不足による下層配線２と上層配線４間の層配線
間短絡などが生じるという欠点がある。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-described conventional layer wiring, the layer wiring between the lower layer wiring 2 and the upper layer wiring 4 due to insufficient coverage of the step line of the upper layer wiring 4 or the interlayer insulating film 3 in the step portion of the lower layer wiring 2. There is a drawback that short circuit occurs between them.
本発明は従来の上記実情に鑑みてなされたものであ
り、従って本発明の目的は、従来の技術に内在する上記
欠点を解消することを可能とした新規な半導体集積回路
装置を提供することにある。The present invention has been made in view of the above conventional circumstances, and therefore an object of the present invention is to provide a novel semiconductor integrated circuit device capable of solving the above-mentioned drawbacks inherent in the conventional technology. is there.
発明の従来技術に対する相違点 上述した従来の半導体集積回路装置の層配線構造に対
し、本発明は層配線を複数段に分割して構成するという
相違点を有する。Differences from the Prior Art of the Invention The present invention has a difference from the above-described conventional layer wiring structure of the semiconductor integrated circuit device in that the layer wiring is divided into a plurality of stages.
課題を解決するための手段 本発明の半導体集積回路装置は、第１配線層と、該第
１配線層を覆うように形成し、かつ前記第１配線層上を
前記第１配線層よりも狭い幅で除去した部分に設けた第
２配線層と、前記第１絶縁膜および前記第２配線層の上
に形成した第２絶縁膜とを有することを特徴とする。Means for Solving the Problems A semiconductor integrated circuit device according to the present invention is formed with a first wiring layer and a first wiring layer so as to cover the first wiring layer, and the first wiring layer is narrower than the first wiring layer. It is characterized in that it has a second wiring layer provided in a portion removed by the width and a second insulating film formed on the first insulating film and the second wiring layer.
実施例 次に、本発明をその好ましい一実施例について図面を
参照して具体的に説明する。Embodiment Next, the present invention will be described in detail with reference to the drawings for a preferred embodiment thereof.
第１図は本発明の一実施例を示す断面図である。 FIG. 1 is a sectional view showing an embodiment of the present invention.
第１図において、基板１上に下層配線をパターンニン
グするに当たり、下層第１配線12をパターンニングし、
その下層第１配線12の上に層間第１絶縁膜13を成膜し、
下層第１配線12上の第１絶縁膜13を後述の下層第２配線
22の面積だけ除去し、次いで、下層第１配線12上に下層
第２配線22を下層第１配線12よりやや狭い幅でパターン
ニングすることにより下層配線を構成する。その下層配
線の上に層間第２絶縁膜23を成膜し、その上に上層配線
４をパターンニングする。In FIG. 1, when patterning the lower layer wiring on the substrate 1, the lower layer first wiring 12 is patterned,
An interlayer first insulating film 13 is formed on the lower first wiring 12 and
The first insulating film 13 on the lower layer first wiring 12 is formed on the lower layer second wiring described later.
The area of 22 is removed, and then the lower-layer second wiring 22 is patterned on the lower-layer first wiring 12 with a width slightly narrower than that of the lower-layer first wiring 12 to form the lower-layer wiring. An interlayer second insulating film 23 is formed on the lower layer wiring, and the upper layer wiring 4 is patterned thereon.
なお、下層第２配線22の幅は下層第１配線12の幅に対
して少なくとも下層第１配線12の厚さ以上細める事が必
要である。It is necessary that the width of the lower second wiring 22 is made thinner than the width of the lower first wiring 12 by at least the thickness of the lower first wiring 12.
発明の効果 以上説明したように、本発明によれば、下層配線のパ
ターンニングを複数回に分けて行うことにより、配線段
差に傾斜を持たせ、上層配線の段線また、層間絶縁膜の
カバレッジ不足による上層配線と下層配線間の配線間短
絡を防止できる効果が得られる。EFFECTS OF THE INVENTION As described above, according to the present invention, the patterning of the lower layer wiring is performed in a plurality of times to make the wiring step have an inclination, and the step line of the upper layer wiring and the coverage of the interlayer insulating film are provided. It is possible to obtain an effect of preventing a short circuit between the upper layer wiring and the lower layer wiring due to the shortage.
第１図は本発明の層間の一実施例を示した断面図、第２
図は従来の層間を示した断面図である。 １……基板、２……下層配線、３……層間絶縁膜、４…
…上層配線、12……下層第１配線、22……下層第２配
線、13……層間第１絶縁膜、23……層間第２絶縁膜FIG. 1 is a sectional view showing an embodiment of the interlayer of the present invention, and FIG.
The figure is a cross-sectional view showing a conventional interlayer. 1 ... Substrate, 2 ... Lower layer wiring, 3 ... Interlayer insulating film, 4 ...
... Upper layer wiring, 12 ... Lower layer first wiring, 22 ... Lower layer second wiring, 13 ... Interlayer first insulating film, 23 ... Interlayer second insulating film
Claims (1)
形成し、かつ前記第１配線層上を前記第１配線層よりも
狭い幅で除去した第１絶縁膜と、前記第１配線層上の前
記第１絶縁膜を除去した部分に設けた第２配線層と、前
記第１絶縁膜および前記第２配線層の上に形成した第２
絶縁膜とを有することを特徴とする半導体集積回路装置1. A first wiring layer, a first insulating film formed so as to cover the first wiring layer, and removed on the first wiring layer with a width narrower than the first wiring layer; A second wiring layer provided on a portion of the first wiring layer where the first insulating film is removed, and a second wiring layer formed on the first insulating film and the second wiring layer
A semiconductor integrated circuit device having an insulating film
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014302A JP2551077B2 (en) | 1988-01-25 | 1988-01-25 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014302A JP2551077B2 (en) | 1988-01-25 | 1988-01-25 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01189136A JPH01189136A (en) | 1989-07-28 |
| JP2551077B2 true JP2551077B2 (en) | 1996-11-06 |
Family
ID=11857302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63014302A Expired - Lifetime JP2551077B2 (en) | 1988-01-25 | 1988-01-25 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2551077B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197829A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Heat treatment method for compound semiconductor |
| JPS5929441A (en) * | 1982-08-10 | 1984-02-16 | Mitsubishi Electric Corp | Multilayer wiring structure of semiconductor device |
| JPS5968952A (en) * | 1982-10-13 | 1984-04-19 | Sanyo Electric Co Ltd | Formation of wiring |
| JPS62245654A (en) * | 1986-04-18 | 1987-10-26 | Fuji Xerox Co Ltd | Semiconductor device and manufacture thereof |
-
1988
- 1988-01-25 JP JP63014302A patent/JP2551077B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01189136A (en) | 1989-07-28 |
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