JPH01189136A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent upper and lower layer wirings from short-circuiting therebetween by composing layer wirings in one wiring layer at a plurality of stages. CONSTITUTION:In order to pattern lower layer wirings on a substrate 1, lower layer first wirings 12 are patterned, an interlayer first insulating film 13 is grown on the wirings 12, and the film 13 on the wirings 12 is removed only in the area of lower layer second wirings 22. Then, the wirings 22 are patterned on the wirings 12 in slightly narrower width than that of the wirings 12, thereby forming lower layer wirings. An interlayer second insulating film 23 is grown on the lower layer wirings, and upper layer wirings 4 thereon are patterned. The width of the wirings 22 is reduced at least more than the thickness of the wirings 12 with respect to the width of the wirings 12. Thus, the upper and lower layer wirings are prevented from short-circuiting therebetween.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a layer structure system for wiring layers.

2. Description of the Related Art Conventionally, layer wiring connecting elements and circuits of a semiconductor integrated circuit device has a single two-layer wiring structure as shown in FIG. The structure was such that a glabellar insulating film 3 was formed thereon, and an upper layer wiring 4 was arranged thereon.

The problem to be solved by the invention, ′.

The above-mentioned conventional layer wiring has the disadvantage that a short circuit between the lower layer wiring 2 and the upper layer wiring 4 occurs due to the dashed line of the upper layer wiring 4 at the stepped portion of the lower layer wiring 2 or insufficient coverage of the glabella insulating film 3. be.

The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the present invention is to provide a novel semiconductor integrated circuit device that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Difference between the present invention and the prior art The present invention differs from the layer wiring structure of the conventional semiconductor integrated circuit device described above in that the layer wiring is divided into multiple stages.

Means for Solving the Problems In order to achieve the above object, the wiring layer structure of the semiconductor integrated circuit device according to the present invention is characterized in that the wiring layer is divided into a plurality of stages to form one wiring layer.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention.

In FIG. 1, when patterning the lower layer wiring on the substrate 1, the lower layer first wiring 12 is patterned,
The first wiring below! 2, the first insulating film 13 on the lower first interconnect 12 is removed by the area of the lower second interconnect 22, which will be described later, and then the first interlayer insulating film 13 on the lower first interconnect 12 is removed. The lower layer wiring is formed by patterning the lower layer second wiring 22 to have a slightly narrower width than the lower layer first wiring 12. A second interlayer insulating film 23 is formed on the lower layer wiring, and the upper layer wiring 4 is patterned thereon.

Note that the width of the lower layer second wiring 22 is the same as that of the lower layer first wiring! 2, it is necessary to reduce the thickness by at least the thickness of the lower layer first wiring 12.

As described in detail, according to the present invention, by performing patterning of the lower layer wiring in multiple steps, the wiring steps are made to have an inclination, and the stepped lines of the upper layer wiring and the coverage of the interlayer insulating film are The effect of preventing inter-wiring short circuit between the upper layer wiring and the lower layer wiring due to insufficient wiring can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing one embodiment of the interlayer structure of the present invention;
The figure is a sectional view showing a conventional interlayer. ■... Substrate, 2... Lower layer wiring, 3... Interlayer insulating film, 4... Upper layer wiring, 12... Lower layer first wiring, 22...
. . . Lower layer second wiring, 13 . . . Interlayer first insulating film, 23.
...Second interlayer insulating film patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai

Claims (1)

[Claims] 1. A semiconductor integrated circuit device characterized in that, in wiring connecting elements and circuits of the semiconductor integrated circuit device, one wiring layer is composed of a plurality of layers of layer wiring.