JPS58123739A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent disconnection at steps and to reduce wiring capacity by a method wherein resists are partially retained on a substrate surface to ensure a less rugged surface whereupon wiring conductors are built thereby interlayer insulating layer becomes unnecessary. CONSTITUTION:A negative-type resist pattern 8 is formed in a region of a wiring pattern 4 with possible disconnection and in a region of wirings crossing each other. A positive-type wiring resist pattern 7 is formed for the formation of wiring materials. Lift-off is performed and the positive and negative resists are removed for the formation of wiring bridges 8, 9. A passivation SiO2 film 5 is then formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device in a multi-layered structure without causing fracture even on a surface with severe steps.
(2) Prior Art and Problems Conventionally, in wiring pattern formation in the manufacture of semiconductor devices, the entire device pattern formed on the substrate is coated with an interlayer insulating layer. After the formation, a connection part (contact hole formation) was formed, and a wiring pattern was formed thereon.

This method has eight drawbacks: it requires an interlayer insulating layer, it requires forming a contact hole, and ovrr@ may occur at the stepped portion. Also, the ninth stage of multilayer arrangement is to form interlayer films and contact holes.

One way to solve the above problem is that wiring pattern formation must be repeated.
In 998I, a polymer resin film is applied to the entire surface of the substrate, and the process of patterning the arrangement is repeated to remove all of the VK-polymer resin film that has formed a multilayer structure.Finally, the glass film is coated as a conductor. Adheres to the surface・JP-A-14-14
In the l-axis No. 1, the glass is formed by the usual vapor phase growth method.On the other hand, as an attempt at two-layer deposition using a resist, in the s@Kai-Sho 64-115 OII, the glass is formed by thickly covering the cyst in the first layer. Meri 1! (3) Purpose of the Invention The object of the present invention is to create a metal tt using an interlayer insulating layer, and then form a p-wiring using a lift-off method. A negative resist is formed on the parts and the stepped parts to connect by process without forming contact holes ■Provides a high-yield method of pattern formation that forms wiring crossing patterns and does not cause disconnections in wiring patterns. do.

(4) Structure of the Invention According to the present WIi4VC, the above-mentioned object is achieved by leaving a resist partially on the surface of a semiconductor substrate having an uneven surface in a shape that makes the uneven surface gentle as a whole, and then applying a gentle ridged resist and A method of manufacturing a semiconductor device characterized by forming a wiring conductor on the surface of a semiconductor substrate is achieved. To summarize the present invention, 1. The present invention is a method for manufacturing a semiconductor device characterized by forming a wiring conductor on the surface of a semiconductor substrate. 0M8 etc.)
Taking advantage of the fact that the exposure-drawn resist pattern does not dissolve even in other liquids, and the edges of the resist pattern are relatively gently sloped, this resist pattern is used to form bridges at intersections. It is used as a base to fill in the stepped recesses formed on the i9 board, and a pattern is formed on it to form disconnection-free connections and bridge wiring *'t-.

＠ 11al Book (b) is a cross-sectional view showing the principle of the present invention. In FIG. 1(a), for example, a negative type electron beam resist (ml) is applied to the lower layer conductor 8 provided with the semiconductor substrate IK,
IA image. This negative resist pattern 6 is shown in FIG.
), it has a gentle edge pattern with 47 tails, and it remains undissolved even with other developers, so it is possible to form wiring patterns without disconnections by photo-etching.
For example, the wiring pattern is lifted off using an electron beam positive resist pattern. At that time, negative resist 8
can be simultaneously peeled off and then formed by OVD, an interlayer insulating layer can also be formed at the same time.

This is OVD 810. 4. For which sample surface does the film grow? This means that the thickness of the interlayer insulating layer shown in FIG. 1 is possible with sgIt, which is the thickness tl of the pad page 12 layer. Also, the dragon
can be determined by the thickness k of the negative resist 8.

Normally tl and t are several thousand A, but in order to reduce the capacitance with the wiring, K11t@ should be made as large as possible◎However,
': I had difficulty forming intertatoholes.

In the present invention, the meaning 1 (pudge page s + ol (6 o 1 [
Thickness) is 1oooom, then 1. 〇Next, in the part where one layer connection is formed, it is enough to leave the negative resist S only on the edge part of the device pattern S of wJl, and it is hot because the disconnection is also spun. . Furthermore, it is understood that it is sufficient to similarly form negative resist 1 on the lower stage side to prevent disconnection at the level difference in the substrate itself (FIG. 8 (-K multiplied by point 1lW)). Another characteristic point in Figure I is that the board l and
This is the plane 6 that the pattern meeting is in contact with. However, in general semiconductor devices, there is an insulating layer 810 on the substrate surface to separate the active layer of the element. There are many places where it is acceptable to create a tactile surface 6.

As described above, the wiring pattern formation according to the method of the present invention eliminates the need for forming an insulating layer between the eyebrows and forming a contact hole, and allows the capacitance between wirings to be reduced to - compared to the conventional method without any interruption. (5) Implementation of the Invention Let's explain the above Pro 7th step by step with reference to Figure 3.
In Figure fib), a negative resist pattern 8 is formed where a wiring pattern number is formed and a fault is considered, and where the wiring pattern intersects.This makes the board surface smooth.In amstbl, a positive JIK wiring resist is used. Forming a pattern to form wiring material (electrode material)0
Then, when lift-off is performed in Figure 5 (cJ), the positive and negative resists are peeled off.

A wiring bridge S is formed at the intersection, and a front bridge as shown in 9 is formed near the step. Therefore, if the padge page is opened at 8i0.film with 0VDi, 810- is also formed and buried in the bridge 8*9. ], the other surfaces 1G can be bridged. These bridges and contact surfaces are determined by a negative resist pattern drawn with an electron beam. Figure 3 shows this state. (- indicates top view %) (l is a cross-sectional view.

The negative resist 8 may have a pattern that sufficiently covers the area where the wiring pattern is to be formed, as shown in the figure.

The state of the wiring pattern 4 formed thereon is determined by the mutual overlap of the device pattern 2, the negative resist pattern 8, and the wiring pattern (AND); 5AND4 is the contact part 11, and 8AND4 is the step part. 9) in the bridge (Fig. 11c) is MANO I AND
8 AND 4 results in the formation of 8) by wiring intersection bridges and bridges (Fig. Z lc). In addition.

In the laJ diagram, the dotted line indicates the edge of the groove in the substrate. Now, a comparison between the conventional process and the process according to the present invention will be explained in the flow below.

Conventional process 1 1.0 V D Si's deposition process 2, contact resist balloon Y type a & contact formation (810,
Etching) table Electrode resist pattern formation (positive type)
5. Electrode material deposition process 1 Lift-off (positive resist peeling) F. Badge page release (OVD 8i0. Deposition process) Invention process 1. Negative resist pattern formation (steps and wiring bridge parts) S tW resist pattern formation ( Positive type) 8, Electrode material deposition table Lift-off (negative, positive resist peeling) i, Pad page change [) VD 810. Debojishi, n) i.e.
Conventionally, there are seven processes for forming wiring patterns. On the other hand, in the process using the present invention, OV D
810. It can be seen that the interlayer insulating layer formation and contact formation, which require a deposition process, are no longer necessary and can be achieved in one process. This flowchart takes wiring pattern formation by lift-off as an example, but formation by etching is also possible.In this case, a negative resist pattern 3 is formed as a protective layer in the areas where etching affects the substrate, and the wiring pattern is formed over the entire surface. All that is required is to deposit the material and then form the wiring pattern by etching.

Now, if we consider the multilayer arrangement 41, conventionally 1. of the above flowchart. From 6. tP] repeating becomes K. However, the present invention has 1. This is possible by repeating from 41).

Make the process even more efficient and busy.

As described above, the present invention eliminates the need for one interlayer insulating layer and its contact hole formation in the formation of a detailed wiring pattern, and enables the formation of a negative resist pattern with an electron beam to form wiring that eliminates disconnections due to steps, etc., and further reduces the capacitance between wirings. It can also be used as an interlayer insulating film. Further, there is an effect that a multilayer wiring method can be easily implemented. In the present invention, Fig. 11m)
As shown in Figure 3, it is necessary to leave the resist partially, but as mentioned above, exposure data can be easily created automatically, so it can be easily accomplished by employing electron beam exposure technology.

The figure is a further development of the present invention, and differs from Figure 1 in Figure 3 by a wiring intersection 8 and a surface 6 where contact between the board and the wiring pattern is allowed (an insulating layer surface that is not an active part in a semiconductor device but is separated from it). By forming a portion 1zt to support the bridge, it is possible to cross wiring in a device pattern S having a large width.

In addition, a bridge is formed also on the surface 6, which has the effect of reducing the capacitance to the substrate. 18 indicates a hollow pattern portion.

In fact, the limit for the length of bridging the wiring pattern is lo
#m-BOpm requires support @ At the intersection of both wirings, device pattern sI/c like [41-]
A portion 1111B that requires a support is left open and a support 17t' of the wiring bridge is formed to make it cross over a long length.

In the latter case, the wiring capacitance with the substrate is reduced by providing 1 g of supports at intervals of about 10 m.

(6) Effects of the invention According to the present invention, one interlayer insulating layer and its processing are unnecessary,
In addition, it is possible to prevent WfrIllIII at the stepped portion and further reduce the wiring capacitance, and also to easily make multilayer wiring devices KWJI'@, ii! Effective in streamlining the manufacturing process and improving yield

[Brief explanation of drawings]

FIG. 11al, 弽) is a cross-sectional view illustrating the steps of a method for manufacturing a semiconductor device that shows the S principle of the present invention.
81alt(bj
In another embodiment of the present invention, the negative resist is partially exposed and left in the next top view and cross-sectional view. A cross-sectional view and a top view are shown in which a bridge is provided for wiring. In the figure, 1 is a semiconductor substrate, 2 is a device pattern, 8 is a negative resist, 4 is a wiring conductor, 6 is an oxide film grown in a vapor phase, and 7 is a top view. 8 and 9 are positive resists, 11 is a contact portion, 11 is a bridge support portion, and 18 is a hollow pattern portion for forming a bridge. 1-7 is

Claims (1)

[Claims] (1) On the surface of a semiconductor substrate having an uneven surface, a resist is left partially in a shape that makes the uneven surface gentle as a whole. 1. Next, the friendship resist is made gentle and a conductor is formed on the surface of the semiconductor substrate. Method for manufacturing a semiconductor device ◎ +21 $11 The wiring conductor is placed in the electrically layered wiring part,
Method 0 of manufacturing a semiconductor device according to claim 1, characterized in that the semiconductor device is a bridge.