JPS6076142A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6076142A JPS6076142A JP18475383A JP18475383A JPS6076142A JP S6076142 A JPS6076142 A JP S6076142A JP 18475383 A JP18475383 A JP 18475383A JP 18475383 A JP18475383 A JP 18475383A JP S6076142 A JPS6076142 A JP S6076142A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- insulating film
- groove
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の属する技術分野の説明
本発明は半導体装置における配線層の構造に関するもの
である０
（２）従来技術の説明
従来、半導体装置の配線層の形成は半導体基板上の絶縁
層にコンタクト孔を形成しその上に配線物質を付着させ
フォトエツチング法によシ配線層を形成する構造をとっ
ている。この構造によると配線層において配線のある部
分と配線のない部分で段差が生じ、特に二層以上の配線
層をもつ半導体装置においては、配線残シあるいは配線
段切れとなる可能性が高くなシこれが多層配線を持つ半
導体集積回路の配線の信頼性を低下させるような欠点が
あった。Detailed Description of the Invention (1) Description of the technical field to which the invention pertains The present invention relates to the structure of a wiring layer in a semiconductor device.0 (2) Description of the prior art Conventionally, the formation of a wiring layer of a semiconductor device is The structure is such that a contact hole is formed in an insulating layer on a substrate, a wiring material is deposited thereon, and a wiring layer is formed by photo-etching. With this structure, a difference in level occurs between the part with wiring and the part without wiring in the wiring layer, and there is a high possibility that wiring remains or breaks in the wiring, especially in semiconductor devices with two or more wiring layers. This has the drawback of lowering the reliability of wiring in semiconductor integrated circuits having multilayer wiring.
（３）発明の詳細な説明
本発明は従来の半導体装置の製造設備を用い半導体基板
上の絶縁膜に配線層を収容する溝を形成し、配線ノーの
段差を平担化することによって、配線残シをなくしさら
に多層配線時の下１６段差による配線段切れを防止する
ことができる多層配線の配線構造を提供することを目的
とするものである。(3) Detailed Description of the Invention The present invention uses conventional semiconductor device manufacturing equipment to form a groove for accommodating a wiring layer in an insulating film on a semiconductor substrate, and flattens the level difference in the wiring layer. It is an object of the present invention to provide a wiring structure of multilayer wiring which can eliminate residual traces and prevent wiring step breakage due to the lower 16 level difference in multilayer wiring.
（４）発明の構成
半導体基板上の絶縁膜にコンタクト孔を形成しその上に
配線層を形成する半導体装置において、絶縁膜に配線層
を収容する溝を形成することによシ配線残シを防止し、
配線段差を平担化することによシ配線段切れを防止する
ことができる配線層構造を有することを特徴とした半導
体装置である。(4) Structure of the Invention In a semiconductor device in which a contact hole is formed in an insulating film on a semiconductor substrate and a wiring layer is formed thereon, remaining wiring can be avoided by forming a groove in the insulating film to accommodate the wiring layer. prevent,
The present invention is a semiconductor device characterized by having a wiring layer structure that can prevent wiring step breakage by flattening wiring steps.
（５）実施例の説明 次に本発明の実施例について図面を参照して説明する。(5) Description of examples Next, embodiments of the present invention will be described with reference to the drawings.
第１図は従来技術により形成した一層配線系のコンタク
ト部分の断面図である。半導体基板１０１上に絶縁膜１
０２を付着させ所望の位置にコンタクト孔１０３を形成
する。その後配線物質１０４を付着させて配線層を形成
し最後に保護膜１０５を付着させている。FIG. 1 is a sectional view of a contact portion of a single-layer wiring system formed by a conventional technique. Insulating film 1 on semiconductor substrate 101
02 is attached to form a contact hole 103 at a desired position. Thereafter, a wiring material 104 is deposited to form a wiring layer, and finally a protective film 105 is deposited.
第２図は本発明の一実施例を示すものでおる。FIG. 2 shows an embodiment of the present invention.
例として一層配線構造の場合を示す。半導体基板２０１
上に付着させた絶縁膜２０２にフォト−・チング、法を
用いて配線層を収容する溝２０３を形成し所望め位置に
コンタクト孔２０４を形成した後、十分膜厚のある配線
物質を付着させる。この配線物質を適切にエツチングし
前記で形成した溝にのみ配線物質を残すことによって平
担化された配線層が形成される。その後保護膜２０８を
付着させると一層配線は終了する。以上一層配線系の構
造について説明したが本発明は二層三層等の多層配線構
造の場合にも適応でき、多層となるほど配線段差が緩和
される構造となるので配線残シによる線間短絡や下層段
差による配線段切れなどを防止することができ信頼性の
高い多層配線構造を実現することができる。As an example, a case of a single layer wiring structure is shown. Semiconductor substrate 201
After forming a groove 203 for accommodating a wiring layer in the insulating film 202 deposited on top by photo-etching and forming a contact hole 204 at a desired position, a sufficiently thick wiring material is deposited. . A flattened wiring layer is formed by appropriately etching this wiring material and leaving the wiring material only in the grooves formed above. After that, a protective film 208 is attached to complete the wiring. Although the structure of a single-layer wiring system has been described above, the present invention can also be applied to a multi-layer wiring structure such as a two-layer or three-layer wiring structure. It is possible to prevent wiring steps from being broken due to lower layer steps, and to realize a highly reliable multilayer wiring structure.
第３図は本発明の二層配線構造の例を示すものである。FIG. 3 shows an example of the two-layer wiring structure of the present invention.
−
−（６）発明の詳細な説明
本発明は以上説明したようにコンタクト孔を開孔する前
に絶縁膜に配線層を収容する溝を形成することによって
段差のない高信頼性の配線構造を形成することができる
効果がある。- - (6) Detailed Description of the Invention As explained above, the present invention provides a highly reliable wiring structure with no steps by forming a groove for accommodating a wiring layer in an insulating film before forming a contact hole. There are effects that can be formed.
第１図は従来技術によ多形成した一層配線構造のコンタ
クト部の断面図、第２図（Ａ）〜（切は本発明の一層配
線構造の一実施例を示すコンタクト部の断面図、第３図
は本発明の二層配線構造の一実施例を示す断面図である
。
尚、図において、１ｏ１・・・・・・半導体基板、１ｏ
２・・・・・・絶縁膜、１０３・・・・・・コンタクト
孔、１ｏ４・・・・・・配線物質、ｌＯ５・・・・・・
保護膜、２０１・・・・・・半導体基板、２０２・・・
・・・絶縁膜、２０３配線層を収容する溝、２０４・・
・・・・コンタクト孔、２０５・・・・・・配線物質、
２０６・・・・・・パターニングされたフォトレジスト
、２０７・・・・・・整形された配線物質、２０８・・
・・・・保護膜、３０１・・・・・・半導体基板、３０
２・・・・・・絶縁膜、３０３・・・・・・整形された
一層目の配線物質、３０４・・・・・・二層目の絶縁膜
、３０５・・・・・・整形された二層目の配線物質、３
０６・・・・・・保護膜である。
８ｚ図
豹２ 図
第３図FIG. 1 is a cross-sectional view of a contact portion of a single-layer wiring structure formed in accordance with the prior art, and FIGS. Figure 3 is a cross-sectional view showing an embodiment of the two-layer wiring structure of the present invention. In the figure, 1o1...semiconductor substrate, 1o
2... Insulating film, 103... Contact hole, 1o4... Wiring material, lO5...
Protective film, 201... Semiconductor substrate, 202...
...Insulating film, 203 Groove for accommodating wiring layer, 204...
... Contact hole, 205 ... Wiring material,
206...Patterned photoresist, 207...Shaped wiring material, 208...
...Protective film, 301...Semiconductor substrate, 30
2... Insulating film, 303... Shaped first layer wiring material, 304... Second layer insulating film, 305... Shaped Second layer wiring material, 3
06...Protective film. 8z Diagram Leopard 2 Diagram 3
Claims (1)
配線層を形成する半導体装置において、絶縁膜に配線層
を収容する溝を有することを特徴とした半導体装置。A semiconductor device in which a contact hole is formed in an insulating film on a semiconductor substrate and a wiring layer is formed thereon, characterized in that the insulating film has a groove for accommodating the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18475383A JPS6076142A (en) | 1983-10-03 | 1983-10-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18475383A JPS6076142A (en) | 1983-10-03 | 1983-10-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6076142A true JPS6076142A (en) | 1985-04-30 |
Family
ID=16158738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18475383A Pending JPS6076142A (en) | 1983-10-03 | 1983-10-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076142A (en) |
-
1983
- 1983-10-03 JP JP18475383A patent/JPS6076142A/en active Pending
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